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Full text of "Sony Semiconductor IC CCD Camera & Peripheral Data Book 1990"


® i 




@ 



Semiconductor IC 





MCMXCVn 



L 



Semiconductor Integrated Circuit Data Book 

1990 



List of Model Names/ 
Index by Usage 



Description 

CCD Camera 
(Black/White) 

CCD Camera (Color) 
CCD Imager System 



IC for Scanning System 
of Video Camera 

Signal Processing IC 
for Video Camera 



CCD Delay Line 











SUE" Ql (^1S<+I 



Semiconductor Integrated Circuit Data Book 

1990 



List of Model Names/ 
Index by Usage 



Description 

CCD Camera 
(Black/White) 

CCD Camera (Color) 
CCD Imager System 



IC for Scanning System 
of Video Camera 

Signal Processing IC 
for Video Camera 



CCD Delay Line 











Semiconductor Integrated Circuit Data Book 

1990 



SONY. 



PREFACE 



This is the 1990 version of the Sony semiconductor IC data book. This book covers all the 
semiconductor products manufactured and marketed by Sony. 

In preparation of this data book, as much characteristic and application data as possible have 
been collected and added with a view of making this book a convenient reference for users of 
Sony products. If, however, you are dissatisfied with this book in any way, please write; we 
welcome suggestions and comments. 



The contents of this data book although accurate and complete at the time of publication, 
are subject to change in order to incorporate improvements on the products. 

Circuits shown are typical examples illustrating the operation of the devices. They are not 
meant to convey any patents or other rights. Sony cannot assume responsibility for any 
problems arising out of the use of these circuits. 



Copyright 1990 by Sony Corporation 



Contents 

Page 

1. List of Model Names 6 

2. Index by Usage 7 

3. IC Nomenclature 15 

4. Precautions for IC Application 17 

1) Absolute maximum ratings 17 

2) Protection against electrostatic breakdown 18 

3) Mounting method 22 

5. Quality Assurance and Reliability 24 

6. Data Sheets o^ 

1) CCD Camera (Black/White) 31 

2) CCD Camera (Color) 1 47 

3) CCD Imager System 295 

4) IC for Scanning System of Video Camera 311 

5) Signal Processing IC for Video Camera 449 

6) CCD Delay Line 67 1 



-5 



1. List of Model Names 



Type 


Page 


Type 


Page 


Type 


Page 


CX20053 


465 


CXD1156Q/R 


380 


ICX022AL-3 


61 


CX20055 


484 


CXD1158M 


322 


ICX022AN-3 


197 


CX20056 


503 


CXD1159Q 


332 


ICX024AK-3 


179 


CX20095A 
CX20186 


664 


CXD1217M 


341 


ICX024AL-3 


75 


CX20151 


521 


CXD1250M 


441 


ICX024AN-3 


214 


CX20180 


415 


CXD1251Q 


393 


ICX026BK 


231 


CX23039 


546 


CXD1255Q 


398 


ICX026BL 


89 


CX23047B 


353 


CXL1008P/M 


682 


ICX027BK 


246 


CXA1065M 


426 


CXL1009P 


673 


ICX027BL 


102 


CXA1072Q-Z/R 


616 


CXL1503M 
CXL1505M 


640 


ICX038AK 


261 


CXA1270N 


656 


CXL1504M 


648 


ICX038AL 


115 


CXA1310AQ 


451 


CXL5001P/M 


694 


ICX039AK 


278 


CXA1337Q-Z/R 


559 


CXL5002P/M 


701 


ICX039AL 


131 


CXA1338Q-Z/R 


577 


CXL5003P/M 


707 


IU018CK-AB 
IU021CK-AB 


161 


CXA1339Q-Z/R 


598 


CXL5005P/M 


714 


IU022AK-30A/40A 
IU024AK-30A/40A 


194 


CXB0026AM 


412 


ICX018CK/021CK 


149 


IS018/021CL 


297 


CXD1030M 


313 


ICX018CL 


33 


IS026BK/027BK 


301 


CXD1035BQ-Z 


364 


ICX021CL 


47 






CXD1141M 


376 


ICX022AK-3 


164 







2. Index by Usage 



1) CCD Camera (Black/White) 



Type 


Application 


Function 


Page 


Optical 

size 

(inch) 


TV 
System 


Picture 

elements 

(HXV) 


Remarks 


ICX018CL 


CCD Image Sensor 
for B/W 


2/3 


EIA 


510X492 




33 


ICX021CL 


2/3 


CCIR 


500X582 




47 


ICX022AL-3 


CCD Image Sensor 
for B/W 


2/3 


EIA 


768X493 




61 


ICX024AL-3 


CCD Image Sensor 
for B/W 


2/3 


CCIR 


756X581 




75 


ICX026BL 


CCD Image Sensor 
for B/W 


1/2 


EIA 


510X492 


600mil shrink package 


89 


ICX027BL 


CCD Image Sensor 
for B/W 


1/2 


CCIR 


500X582 


600mil shrink package 


102 


ICX038AL 


CCD Image Sensor 
for B/W 


1/2 


EIA 


768X494 


600mil shrink package 


115 


ICX039AL 


CCD Image Sensor 
for B/W 


1/2 


CCIR 


752X582 


600mil shrink package 


131 



2) CCD Camera (Color) 



Type 


Application 


Function 


Page 


Optical 

size 

(inch) 


TV 
System 


Picture 

elements 

(HXV) 


Remarks 


ICX018CK 


CCD Image Sensor 
for color 


2/3 


NTSC 


510X492 




149 


ICX021CK 


2/3 


PAL 


500X582 




IU018CK-AB 


CCD Image Sensor 
for color unit 


2/3 


NTSC 


510X492 


Optical low-pass filter 
IR cut filter 


161 


IU021CK-AB 


2/3 


PAL 


500X582 


Optical low-pass filter 
IR cut filter 


ICX022AK-3 


CCD Image Sensor 
for color 


2/3 


NTSC 


768X493 




164 


ICX024AK-3 


CCD Image Sensor 
for color 


2/3 


PAL 


756X581 




179 


IU022AK-30A 
IU022AK-40A 


CCD Image Sensor 
for color unit 


2/3 


NTSC 


768X493 


Optical low-pass filter 
IR cut filter 


194 


IU024AK-30A 
IU024AK-40A 


2/3 


PAL 


756X581 


Optical low-pass filter 
IR cut filter 


ICX022AN-3 


CCD Image Sensor 
for color 


2/3 


NTSC 


768X493 




197 


ICX024AN-3 


CCD Image Sensor 
for color 


2/3 


PAL 


756X581 




214 


ICX026BK 


CCD Image Sensor 
for color 


1/2 


NTSC 


510X492 


600mil shrink package 


231 


ICX027BK 


CCD Image Sensor 
for color 


1/2 


PAL 


500X582 


600mil shrink package 


246 


ICX038AK 


CCD Image Sensor 
for color 


1/2 


NTSC 


768X494 


600mil shrink package 


261 


ICX039AK 


CCD Image Sensor 
for color 


1/2 


PAL 


752X582 


600mil shrink package 


278 



-7- 



3) CCD Imager System 



Type 


Application 


Function 


Page 


IS018CL 


CCD imager system kit 
for B/W camera 


ICX018CL and three peripheral hybrid 
ICs, for EIA 


297 


IS021CL 


ICX018CL and three peripheral hybrid 
ICs, for CCIR 


IS026BK 


CCD imager system kit 
for color camera 


ICX018CL and five peripheral hybrid 
ICs, for NTSC 


301 


IS027BK 


ICX018CL and five peripheral hybrid 
ICs, for PAL 



4) IC for Scanning System of Video Camera 



Type 


Application 


Function 


Page 


CXD1030M 


Sync signal generator 


14MHz (18MHz) demultiplier, for 
NTSC, PAL 


313 


CXD1158M 


Sync signal generator 


14MHz (18MHz) demultiplier, for 
NTSC, PAL sub carrier output X 3 


322 


CXD1159Q 


Sync signal generator 


14MHz (18MHz) demultiplier, for 
NTSC, PAL window pulse output 


332 


CXD1217M 


Sync signal generator 


Compatible with the respective systems, 
NTSC, PALM, PAL and SECAM 
color framing by the respective systems, 
NTSC, PALM, PAL and SECAM 


341 


CX23047B 


Timing pulse generator 
for scanning system 


CCD drive timing pulse generation, sig- 
nal processing pulse generation, for 
ICX018CK/CL, ICX021CK/CL 


353 


CXD1035BQ-Z 


Timing pulse generator 
for scanning system 


CCD drive timing pulse generation, sig- 
nal processing pulse generation, for 
ICX022AK/AL, ICX024AK/AL 


364 


CXD1141M 


Variable electric shut- 
ter timing generator 


Variable electronic shutter timing gener- 
ation (1/60 to 1/10000 sec.) for 
ICX022AK/AL, ICX024AK/AL 


376 


CXD1156Q/R 


Timing Generator for 
CCD driving Camera 


CCD drive timing pulse generation, Vari- 
able electronic shutter timing generation 
(1/60 to 1/10000 sec,) for ICX026BK/BL, 
ICX027BK/BL 


380 


CXD1251Q 


Blemish compensation 
timing generator 


Blemish compensation timing generator, 
for ICX026BK/BL, ICX027BK/BL 


393 


CXD1255Q 


Timing Generator for 
CCD driving Camera 


CCD drive timing pulse generation, sig- 
nal processing pulse generation, for 
ICX038AK/ICX039AK 
variable electronic shutter timing gener- 
ation (1/60—1/10000 sec) 


398 


CXB0026AM 


CCD clock driver 


CCD imager driver x 2, compatible with 
high frequency operation 


412 


CX20180 


Vertical clock drive 


CCD imager driver X 4, lead-out genera- 
tion inverter, negative voltage genera- 
tion inverter 


415 


CXA1065M 


Vertical clock drive 


CCD imager driver X 4, lead-out genera- 
tion inverter, negative voltage genera- 
tion inverter 


426 


CXD1250M 


Vertical clock drive 


CCD imager driver x 4, lead-out genera- 
tion inverter 


441 



5) Signal Processing IC for Video Camera 



Type 


Application 


Function 


Page 


CXA1310AQ 


Monochrome camera 


Single Chip Processing for CCD Mono- 
chrome camera 


451 


CX20053 


Sample hold 


CDS, color separation, color mix correc- 
tion, y correction, blanking, white clip, 
pedestal setting 


465 


CX20055 


Encoder 


Aperture correction, blank cleaning, 
white clip, chroma mod, fader, finder, 
switcher, 75fi driver 


484 


CX20056 


Auto iris, auto white 
balance 


Iris drive, RB line seq. signal separation, 
auto white balance, low light alarm 


503 


CX20151 


Matrix 


Color differential, signal forming, 
luminance signal forming, multiplexer 


521 


CX23039 


1H delay line x 4 


1H delay line x 4, S/H, delay line driver 


546 


CXA1337Q-Z/R 


Sample hold 


CDS ,AGC, Color separation, chroma sup- 
press 


559 


CXA1338Q-Z/R 


Signal processing 


From color compensation (Mg, G, Cy, 
Ye) interleave coding, R, G, B sythetic 
and Y signal processing 


577 


CXA1339Q-Z/R 


Matrix 


Matrix, white balance, y correction, 
negative/positive inversion 


598 


CXA1072Q-Z/R 


Encoder 


Aperture, auto-corrier balance, 
negative-positive reverse, fader, chroma 
suppression, BLK cleaning 


616 


CXL1503M 
CXL1505M 


For matrix 1H delay 

line 

Signal Processing 


1H CMOS-CCD delay line x 4 


640 


CXL1504M 


Luminous signal 1H 
delay line 


1H CMOS-CCD delay line 


648 


CXA1270N 


Vertical outline com- 
pensation 


Signal generation during, Vertical Out- 
line Compensation 


656 


CX20095A 
CX20186 


Video output 


6dB amp, video driver, bilateral video 
driver 


664 



6) CCD Delay Line 



Type 


Application 


Function 


Page 


CXL1009P 


Video disk 


CMOS-CCD delay line for time base 
corrector, 300mil shirink-DIP 


673 


CXL1008P/M 


VCR 


NTSC skew compensate 


682 


CXL5001P/M 


General purpose 


NTSC 1H CMOS-CCD delay line 


694 


CXL5002P/M 


General purpose 


NTSC 1/2H CMOS-CCD delay line 


701 


CXL5003P/M 


General purpose 


PAL 1H CMOS-CCD delay line 


707 


CXL5005P/M 


General purpose 


NTSC 1H CMOS-CCD delay line, with 
PLL 


714 



-9- 



CCD COLOR CAMERA BLOCK DIAGRAM FOR 2/3" LENS SYSTEM 



ICX018CK 

ICX021CK 

CCD color image sensor 

IU018CK-AB 

IU021CK-AB 

CCD color image sensor unit 



[ 





CX20180 

V driver 










CXB0026AM 

H driver 





ROM 



CX23047B 

Timing 
generator 



CX20056 

Auto iris, Auto 
white balance 



IT 



CX20053 

Sample hold 



CXD1030M 
CXD1159Q 

Sync signal 
generator 



CX20151 

Matrix 



CX20055 

Encoder 



-(8) Video output 



CX23039 

1 H delay 
line 



CCD B/W CAMERA BLOCK DIAGRAM FOR 2/3" LENS SYSTEM 



ICX018CL 
ICX021CL 
CCD image sensor 



C 



ROM 







CX20180 

V driver 






* L 












CXB0026AM 


„ r 






H driver 





CX23047B 

Timing pulse 
generator 



CXD1217M 
CXD1030M 

Sync signal 
generator 



CXA1310AQ 

Signal 
Processing 



-^) Video output 



- 10 



CCD COLOR CAMERA BLOCK DIAGRAM FOR 2/3" LENS SYSTEM 



ICX022AK/ICX024AK 

CCD color image sensor 
IU022AK/IU024AK 

CCD color image sensor unit 





CXA1065M 

V driver 




| ROM | 










4 . 




$ 




CXD1030M 
CXD1159Q 

Sync signal 
generator 








CXD1035BQ-Z 

Timing 










CXB0026AM 

H driver 






generato 


r 


k 
























CXD1141M 

Shutter 
control 












< 















CXA1337Q-Z/R 

Sample hold 



CXA1339Q-Z/R 

Signal 
processing 



CXA1072Q-Z/B 

Encoder 



^S> 



Video 
output 



CXA1Z70N 

Vertical adge 
compensation 



CCD COLOR CAMERA BLOCK DIAGRAM FOR 2/3" LENS SYSTEM 



ICX022AN/ICX024AN 

CCD color image semsor 
IU022AN/IU024AN 

CCD color image sensor unit 



CXA1065M 

V driver 



CXB0026AM 

H driver 



CXA1337Q-Z/R 

Sample hold 



ROM! 



CXD1251Q 

Blemish 
compensation 
timing generator 




CXD1149Q 

Timing generator •- 
shutter control 



CXL1505M 

1 H delay line 



CXA1338Q-Z/R 

Matrix 



CXD1030M 
CXD1159Q 

Sync signal 
generator 



CXA1339Q-Z/R 

Signal processing 



CXA1072QZ/R 

Encoder 



(S3) Video output 



CXL1504M 

1 H delay line 



- 11 



CCD B/W CAMERA BLOCK DIAGRAM FOR 2/3" LENS SYSTEM 

ICX022AL-3 
ICX024AL-3 

CCD image sensor 



CXA1065M 

V driver 



CXB0026AM 

H driver 



CXD1141M 

Shutter 
control 



ROM 

31 



CXD1035BQ-2 

Timing 
generator 



CXA1310AQ 

Signal 
processing 



CXD1217M 
CXD1030M 

Sync signal 
generator 



Video output 



CCD COLOR CAMERA BLOCK DIAGRAM FOR 1/2" LENS SYSTEM 



ICX026BK/ICX027BK 

CCD color image sensor 



ROM 



CXD1251Q 

Blemish 
compensation 
timing generator 









t 






CXD1030M 
CXD1159Q 

Sync signal 
generator 




CXD1250M 

V driver 


„ 


CXD1156Q/R 

Timing 
generator 













































CXA1337QZ/R 

Sample hold 



CXL1503M 

1 H delay line 



CXA1338QZ/R 

Matrix 



CXL1504M 

1 H delay line 



CXA1339Q-Z/R 

Signal 
processing 



CXA1072QZ/R 

Encoder 



Video 
output 

Ho) 



-12- 



CCD B/W CAMERA BLOCK DIAGRAM FOR 1/2" LENS SYSTEM 



ICX026BL 
ICX027BL 

CCD image sensor 



[ 



CXD1251Q 

Blemish 
compensation 
timing generator 



ROM 



CXA1310AQ 

Signal 
Processing 









I 




CXD1217M 
CXD1030M 

Sync signal 
generator 




CXD1250M 

V driver 




CXD1156Q/R 

Timing pulse 
generator 




4 





















-(g) Video output 



I CCD COLOR CAMERA BLOCK DIAGRAM FOR 1/2" LENS SYSTEM 

ICX038AK 
ICX039AK 

CCD image sensor 



c 



CXD1250M 

V driver 



*74HC04 |+- 

H driver 



CXA1337QZ7R 

Sample hold 



CXD1255Q 

Timing generator 



CXD1251Q 

Blemish 
compensation 
timing generator 



ROM 



CXL1505M 

1 H delay line 



I 



CXA1338QZ/R 

Matrix 



CXD1030M 
CXD1159Q 

Sync Signal 
generator 



CXA1339QZ/R 

Signal processing 



CXA1072Q-Z/R 

Encoder 



Video 
output 



-© 



CXL1504 

1 H delay line 



♦ Standard CMOS logic IC 



-13- 



CCD B/W CAMERA BLOCK DIAGRAM FOR 1/2" LENS SYSTEM 



c 



ICX038AL 
ICX039AL 

CCD image 


sensor 






CXD1250M 

V driver 




















CXD1255Q 

Timing 
generator 




CXD1217M 
CXD1030M 

Sync signal 
generator 
















• 74HC04 

H driver 








< 


* 1 




♦ 










CXD1251Q 

Blemish 
compensation 
Timing 
generator 












♦ 








ROM 
















CXA1310AQ 


Vide 


o output 










Si 
pr 


Dcessing 









* Standard CMOS logic IC 



14- 



3. IC Nomenclature 



1) Nomenclature of IC product name 

Currently, both the conventional and new nomenclature systems are mixed in naming IC 
products. 
a) Conventional nomenclature system 

[Example] C X 2 0_L_L A 



b) 



New nomenclature 

[Example] CX A 1 00 1 



A P 



Improvement mark 

"A" is affixed when specifications are partially 

improved. 
Product number 

Identifies individual product. 
Category number 

Indicates the product category in one or two digits. 
Bipolar IC: 0, 1, 8, 10, 20, 22 
MOS IC : 5, 7, 23, 79 
Sony IC mark 



Package mark 

P : Plastic Dual In-line Package 

D : Ceramic Dual Inline Package 

M : Small Outline L-Leaded Package 

L: Single In-line Package 

Q: Quad Flat L-Leaded Package 

S : Shrink Dual In-line Package 

N : Very Small Outline Package (SSOP) 

R : Very Small Quad Flat Package 
Improvement mark 

"A" is affixed when specifications are improved. 
Product number 

Identifies the individual product. 
Product category mark 

A: Bipolar IC 

B: Bipolar digital IC 

D : MOS logic IC 

K: Memory, Mask ROM 

P, Q: Microcomputer, Microprocessor 

L: CCD signal processor 
Sony IC mark 



I 



15- 



2) Nomenclature of CCD Imager 

(Example) I CX 2 6 A K - 3 



Product rank 

Filter or package symbol 

Version 

Product number 

CCD imager symbol 



3) Nomenclature of CCD Imager Block 
a) Conventional nomenclature system 

(Example) I U 1 8 C K A A 



Block parts category 

Block optical parts category mark 

Imager device filter or package 

Imager device version 

Imager device product number 

CCD imager symbol 



b) New Nomenclature 

(Example) IU022AK-3 OA 



n 



4) Nomenclature of CCD Imager System 

(Example) IS026AK-30A 



Block parts category 
Imager device rank 
Imager device filter or package 
Imager device version 
Imager device product number 
CCD imager symbol 



HIC combination symbol 

HIC version 

Imager device rank 

Imager device filter or package 

Imager device version 

Imager device product number 

CCD imager symbol 



16- 



4. Precautions for IC Application 



1) Absolute maximum ratings 

The maximum ratings for semiconductor 
devices are normally specified by "absolute 
maximum ratings". The values shown in the 
maximum ratings table must never be ex- 
ceeded even for a moment. 

If the maximum rating is ever exceeded, 
device deterioration or damage will occur 
immediately. Then, even if the affected 
device can operate, the life will be consider- 
ably shortened. 

Maximum rating must never be reached for 
any TWO items at the SAME time. 

IC maximum ratings 

The following maximum ratings are used 
for ICs. 

(1) Maximum power supply voltage Vcc 
(Vdd) 

The maximum voltage that can be applied 
between the power supply pin and ground pin. 

This power supply voltage rating is directly 
related to the dielectric voltage of transistors 
in the internal circuit, the transistors may be 
destroyed if this voltage is exceeded. 

(2) Allowable power dissipation Pd 

The maximum power consumption allowed 
in IC. 

In the circuit design the absolute maximum 
ratings must not be exceeded, and it must be 
designed only after considering the worst 
situations among the following : 

• Fluctuation in source voltage 

• Scattering in the electrical characteris- 
tics of electrical parts (transistors, resis- 
tors, capacitors, etc.) 

• Power dissipation in circuit adjustment 

• Ambient temperature 

• Fluctuation in input signal 

• Abnormal pulses 

If this allowable power dissipation is ex- 
ceeded, electrical and thermal damage may 
result. 

This value varies with amount of IC inte- 
gration in package types. 



(3) Operating ambient temperature Topr 

The temperature range within which IC can 
operate satisfactorily. 

Even if this temperature range is exceeded 
and some deterioration in operating charac- 
teristics is noted, the IC is not always 
damaged. 

For some ICs, the electrical characteristics 
at Ta = 25°C are not guaranteed even in this 
temperature range. 

(4) Storage temperature Tstg 

The temperature range for storing the IC 
which is not operating. 

This temperature is restricted by the pack- 
age material, and the intrinsic properties of 
the semiconductor. 

(5) Other values 

The input voltage Vin, output voltage Vout, 
input current lin, output current lout and 
other values may be specified in some ICs. 

The relationship among these maximum 
ratings for IC is shown below. 

Vcc 
16 



12 

10 

i 

8 
-55 



Assurance of 
non-destruction 



-10 



No assurance 



, PD-Ta curve 




Topr 



125 



Tstg 
Ambient temperature (°C) 



17 



2) Protection against 

electrostatic breakdown 

There have been problems concerning 
electrostatic destruction of electronic devices 
since the 2nd World War. Those are closely 
related to the advancement made in the field 
of semiconductor devices; this is, with the 
development of semiconductor technology, 
new^ problems in electrostatic destruction 
have arisen. This situation, perhaps, can be 
understood by recalling the case of MOS FET. 

Today, electrostatic destruction is again 
drawing people's attention as we are entering 
the era of LSI and VLSI. Here are our sugges- 
tions for preventing such destruction in the 
device fabrication process. 

Factors causing electrostatic 
generation in manufacture process 

A number of dielectric materials are used in 
manufacture process. Friction of these mate- 
rials with the substrate can generate static 
electricity which may destroy the semicon- 
ductor device. 

Factors that can cause electrostatic 
destruction in the manufacture process are 
shown below: 



Causes of electrostatic destruction of 
semiconductor parts in manufacture 
process 



Input 

i 



Item 



semi- l 
conductor 1 Parts 
resistor | mounting 
capacitor J 


• belt conveyer 

• work table 

• human body 

• Parts box 


i 




solder dipping 


• dipping machine 


i 




visual correction 


• work table 

• human body 

• soldering iron 


I 




lead cutting 


• cutting machine 


1 




sand blasting 


• sand blasting 
machine 


1 




soldering correction 


i 


i 


• belt conveyer 


rear side mounting 
of parts 
frame assembly 


• work table 

• human body 

• parts box 


i 


• soldering iron 


inspection and repair 





I 

Output 



- 1! 



Handling precautions for the prevention of 
electrostatic destruction 

Explained below are procedures that must 
be taken in fabrication to prevent the 
electrostatic destruction of semiconductor 
devices. 

The following basic rules must be obeyed. 
©Equalize potentials of terminals when tran- 
sporting or storing. 
©Equalize the potentials of the electric 
device, work bench, and operator's body 
that may come in contact with the semi- 
conductor device. 
©Prepare an environment that does not 
generate static electricity. 
One method is keeping relative humidity in 
the work room to about 50%. 

Operator 

(1) Clothes 

Do not use nylon, rubber and other mate- 
rials which easily generate static electricity. 
For clothes, use cotton, or antistatic-treated 
materials. Wear gloves during operation. 

(2) Grounding of operator's body 

The operator should connect the specified 
wrist strap to his arm. If the wrist strap is 
not available, then the operator should touch 
the grounding point with his hand, before 
handling and semiconductor device. 

example of grounding band 

cotton glove 




grounding wire 



When using a copper wire for grounding, 
connect a 1MO resistance in series near the 
hand for safety. 



(3) Handling of semiconductor device 

Do not touch the lead. Touch the body of 
the semiconductor device when holding. 
Limit the number of handling times to a 
minimum. Do not take the device out of the 
magazine or package box unless it is abso- 
lutely necessary. 

holding of semiconductor device 




I 



DIP type 



can type 



Equipment and tools 

(1) Grounding of equipment and tools 

Ground the equipments and tools that are 
to be used. Check insulation beforehand to 
prevent leakage. 
[Check point] 

• measuring instrument 

• conveyer 

• electric deburr brush 

• carrier 

• solder dipping tank 

• lead cutter 

• shelves and racks 

grounding of carrier 

conductive sheet 




-19- 



(2) Grounding of work table 

Ground the work table as illustrated. Do 
not put anything which can easily generate 
static electricity, such as foam styrol, on the 
work table. 

grounding of work table 

conductive sheet 



grounding wire 




(3) Semiconductor device case 

Use a metal case, or an antistatic plastic 
case (lined with conductive sheet). 

plastic case for 
semiconductor devices 



conductive sheet 




plastic 



(4) Insertion of semiconductor device 

Insert the semiconductor device during the 
mounting process or on the belt conveyer. 
The insertion should be done on a conductive 
sheet, or on a wood or on a metal carrier. 

(5) Operation in energized state 

When the substrate is checked while energ- 
izing the substrate where the delicate semi- 
conductor device is mounted, be sure to place 
the substrate on corrugated cardboard, 
wood, or on a metal carrier. 



(6) Other points of caution 

Take note of the kind of brush material 
used for removing lead chips. Use metal or 
antistatic-treated plastic brushes. 

Transporting, storing and packaging 

methods 

(1) Magazine 

Use metal, or antistatic-treated plastic IC 
magazines. 

Plastic magazines used for shipping ICs 
are antistatic-treated, and they can be used 
for storing ICs. 

magazine 




conductive magazine 



(2) Bag 

Use a conductive bag to store ICs. If the 
use of vinyl bag is unavoidable, be sure to 
wrap the IC with aluminum foil. 



bag 




conductive bag 



20 



(3) Handling of delivery box 

The delivery box used for carrying sub- 
strates must be made of wood or corrugated 
cardboard. Do not use a vinyl chloride or 
acrylic delivery box, otherwise static electric- 
ity will be generated. 

handling of delivery box 

wooden or corrugated 
cardboard box 




grounding plate 

(4) Treatment after vehicle transport 

After truck transport, place the magazine, 
package box or delivery box on the grounded 
rack, work table, or concrete floor for dischar- 
ging. Do not pull the delivery box for more 
than 1 meter except on a concrete or a 
wooden floor. 

(5) Handling of mounted substrates 
Wear cotton gloves when handling. As far 

as possible, avoid touching soldered faces. 
When handling mounted substrates individu- 
ally, be sure to use a conductive or paper bag. 
Do not use a polyethylene bag. 

handling of mounted substrate 

.cotton glove 




Soldering operation 

(1) Soldering iron 

Use a soldering iron with a grounded metal 
part or a soldering iron with an insulation 
resistance greater than lOMfi (DC 500V) 
after five minutes from energizing. 

(2) Operation 

After inserting the semiconductor device 
into the substrate, solder it as quickly as 
possible. Do not carry the substrate with the 
inserted semiconductor device by car. 

(3) Correction 

When correcting parts (semiconductor 
device and CR parts) after solder-dipping, be 
sure to wear cotton gloves. Also, connect the 
grounding band to the arm, or touch the 
grounding point before operation. 

(4) Manual soldering 

Solder with wrist strap connected to the 
hand, or by touching the grounding point 
from time to during operation. 

(5) Removing semiconductor device 

Do not use the Solder-Pult when removing 
the semiconductor device. Use a Solder-wick 
or equivalent. 



I 



solder remover 



solder-wick 



soler pult 





(6) Soldering work table 

Use a grounded work table, corrugated 
cardboard, or wooden work table for solder- 
ing. Do not solder on foam styrol, vinyl, or 
decorative board. 



conductive bag or - 
paper bag 



-21 - 



3) Mounting method 
Soldering and solderability 
(1) Solderability by JIS 

JIS specifies solderability of an IC terminal 
(lead) in "JIS-C7022 Test Procedure A-2". 
An abstract of this standard follows: 

• Rosin flux must be used, and the terminal 
must be dipped in it for 5-10 seconds. 

• H63A or equivalent solder must be used, 
and the terminal must be dipped in the 
solder which been heated to 230°C±5°C 
for 5±1 seconds. 

• Using a microscope, measure the area 
(%) deposited with solder. JIS specifies 
that more than 95% of the total area 
should be coated with solder. 



(2) Area for soldering warranty 

Soldering is warranted for a specific por- 
tion of the terminal. The warranted portion is 
shown in the following figure. 

The tie-bar cut portion also serves as a 
dam to prevent the sealing resin flowing out 
during device fabrication ; it is cut off at the 
end of the process. Since the terminal is 
exposed at the cut-off end, the area for sol- 
dering is restricted. The portion near the 
resin is often covered with burrs when sealing 
with resin ; it is not in the soldering warranty 
area. 



warranty area for soldering 

tie-bar cut portion 



device main body 




warranty range 



Resistance to soldering heat 
(1) Specification of JIS 

JIS specifies the method for testing the 
resistance to soldering heat. This method is 
used for guaranteeing the IC resistance 
against thermal stresses by soldering. An 
abstract of this standard is as follows: 
• Dip the device terminal only once for 
10±1 seconds in a solder bath of 
260°C±5°C, or for 3±g- 5 seconds in a 
solder bath of 350°C±10°C, for a dis- 
tance of up to 1 to 1.5 mm from the 
main body. 



For the solder flow system temperature 
should be 260°C±5°C. To solder by 
soldering iron temperature should be 
350°C±10°C. 

• Leave the device for more than two 
hours after dipping, then measure the 
device characteristics. 

• Normally, the warranty is limited to 10 
seconds at 260°C±5°C. The distance 
between the device main body and solder 
bath is 1.6 mm. 



22- 



(2) Resistance to soldering heat when 
mounting infrared reflow. 

When surface mount Devices (SOP, QFP 
etc) are dipped directly into a solder pot. 

The device moisture resistance may deteri- 
orate and thermal stress generate cracks in 
the pallet. 

Carefully observe the mounting conditions. 

Recommended temperature profile when 
mounting infrared reflows is shown in the 
figure below. 



a> 


120'C^^ 


235'C fc 

3 to 4*C/sec. / \ 

— »y \ 

170'C / \ 




.8 

> 


50 to 300sec 






"O 








/ 






\ 
\ 
\ 



I 



preheated part 



reflow part -> time 



23 



5. Quality Assurance and Reliability 



The Concept to Quality Assurance 



There are 2 fundamental principles guiding 
Sony Semiconductors. 

1. Customer satisfaction 

2. Top level performance 

What comes first is the ability to respond 
convincingly to given requirements in terms 
of Quality, Delivery, Cost and Servicing. This 
involves all operations involved in the proc- 
ess. The second requisite is the quest for 
superior accomplishment. Here, talent is 
demanded to fulfill customer expectations, 
where quality is concerned, and pursue relat- 
ed activities. 

To this effect an elaborate system of qual- 
ity assurance is firmly established. From the 
early stages of research and development 
well into production, sales and servicing, 



orderly control is applied for the maintenance 
of high standards and further improvement. 
Systematization and automation are pushed 
ahead to provide a stable output of high 
quality production. 

In this respect, the force in charge of im- 
plementing the program is nonetheless sub- 
ject to constant polishing. Gifted people well 
aware of the problems inherent to their tasks 
are at the core of the excellence reflected on 
their yield. 

With the aim of providing the most eco- 
nomical, the most useful and at the same 
time the most gratifying products where 
quality is the criterion, Sony keeps fueling a 
relentless urge for achievement. 



-24- 



Quality assurance system of semiconductor products 



Customer 


Sales Dept. 


Planning and 
Control Dept. 


Technical Dept. 


Manufacturing Dept. 


Quality Assurance 
Dept. 


i, 




h 






Requirments — 
Survey stage 


>4 Market survey 


>i Product planning 




< 




r*\ Product DlanninE 


o 






' review 






" 






Decision on | 
specification planning j 




♦ 




Development planning 




4 




a 

Development 

and 

experimental 

production 

stage 


Tria 








Development design 




Design rev 




i 


C\ <"» 


l6W 


t 


\J 








Trial 
manufacturing 


J 1 




1 Evaluation | 




t 








i 




-j yua i y approva ( j | 


i 




t 








/-\ 


review 


(J 








Experimental mass production — M Evaluation 




'' 






j j 


Production f > 
approval \J 


I 


: 


f 


) 


n 


^-N 


<r 








Mass 

production 

stage 


♦ 










Sales planning V 


1 u 1 


J Materials 


-^| mULLIIUI^ (JUII.IIUJ-. p 


i 


*| acceptance test | 














Production planningh 




i 










T 


' 






Shipment planning 




Wafer process 


<*- 








' 




♦ * 










Assembly 




-1 ipnr-i i 






-J IPQC [ 




* 






Final test 






L. 


1 


Storage 


r* 






; 




I 








J Shipment 


" 








a' ' 


r 










1 Cust 


omer 




Port sale service 


| accer. 


tance | 








.' 


' 






In 1 j 1 


Information sample ; 












| Analysis 


Usage ' 
stage 

Report 


i 




c 


■s r\ d 


J 


i 




4 Corrective measures | 










" 

















I 



*1. IPQC: In Process Quality Control 
*2. QAT: Quality Assurance Test 



-25- 



Quality assurance criteria and 

reliability test criteria 

1) Quality assurance in shipping 

Establishing quality in the design and in 
fabrication is essential to keep the quality 
and reliability levels of the semiconductor 
devices at a high level. This is done by the 
"Zero-defect" (ZD) movement. Further sam- 
pling checks, in units of shipping lot, is done 
on products that have been "totally- 



inspected" at the final fabrication stage, thus 
ensuring no detective items. This sampling 
inspection is done in accordance with MIL- 
STD-105D. 

2) Reliability 

The reliability test is done, periodically, to 
confirm reliability level. 



Periodic Reliability Test 



Item 


Testing time 


LTPD 


Electrical Characteristics Test 


In order to know the initial quality 
level, some types are selected and 
tested again. 


Life Test 


high temperature operation 
high temperature and high 

humidity with bias 
pressure cooker 


up to 1000 h 

up to 1000 h 
up to 200 h 


10% 

10% 
10% 


Environmental Test 


soldering heat resistance 
heat cycle 


10s 
1 00 cycles 


15% 
15% 


Mechanical Test 


solderability 
length strength 


Japan Industrial 
Standard (JIS) 


15% 
15% 


Other Tests 


•If necessary, tests are selected according to 
JIS C7021 C7022 and EIAJ SD121 IC121. 





•These tests are selected by sampling standard. 
LTPD: Lot Tolerance Percent Defective 



These tests and inspection data are useful not only to improve design and wafer processes, but 
also serve to forecast reliability at the consumer level. 



-26 



Reliability Test Standards 



Types of test 


Condition 


Supply 
voltages 


Testing time 


LTPD 


High temperature 
operation 


Ta = 125°C, 150°C 


Typical 


lOOOh 


5% 


High temperature 
with bias 


Ta = 125°C, 150°C 


Typical 


lOOOh 


5% 


High temperature 
storage 


Ta = 150"C 


lOOOh 


5% 


Low temperature 
storage 


Ta = -65°C 


lOOOh 


5% 


High temperature and 
high humidity storage 


Ta=85°C 85% RH 


lOOOh 


5% 


High temperature and 
high humidity with bias 


Ta=85°C 85% RH 


Typical 


lOOOh 


5% 


Pressure cooker 


Ta = 121°C 100%RH 

30 pounds per square inch 


200h 


5% 


Temperature cycle 


Ta = -65°C to + 150°C 


100c 


10% 


Heat shock 


Ta = -65°C to+150°C 


100c 


10% 


Soldering heat resistance 


T solder=260°C 


10s 


10% 


Solderability 


T solder=230°C (rosin type flux) 


5s 


10% 


Mechanical shock 


X, Y, Z 1500G 

Half part of sinusoidal wave of 0.5ms 


3times for 
each direction 


10% 


Vibration 


X, Y, G 20G 

10Hz to 2000Hz to 10Hz (4min) 

Sinusoidal wave vibration 


16minut.es for 
each direction 


10% 


Constant acceleration 


X, Y, Z 20.000G 
Centrifugal acceleration 


lminute 

for each direction 


10% 


Free fall 


Free fall from the height of 75cm to maple 
plate 


3times 


10% 


Lead strength 
(bend) 
(pull) 


based on JIS 


10% 


Electrostatic strength 


Device must be designed again, when electrostatic 
strength below standard supplying surge voltage to each pin 
under the condition of C=200pF and Rs=0a 



I 



LTPD: Lot Tolerance Percent Defective 



-27 



Flow Chart from Development to Manufacturing 

Sony attains high quality and high reliability of semiconductor products by designing 
devices with quality and reliability from the initial steps of development and evaluating 
them sufficiently in each step of the development. 



C 



Product Planning 



Business Planning 



Product Planning Review 



Examination of 
Desired Specification 



Development Planning 



Development Design 



Design Review 



Small Scale Fabrication 



Evaluation 



Acceptance of Quality 
and Reliability (I) 



Trial Manufacturing Review 



Large Scale Trial 
Manufacturing 



Evaluation 



Acceptance of Quality 
and Reliability (II) 



Production Approval 



Production 



Shipping 



Function, Characteristics, Quality and Reliability 

Schedule, Quantity and Cost 

Circuit, Mask, Wafer Process and Packaging 



Characteristics, Quality and Reliability 
Acceptance of Quality and Reliability for Design 



Customer Evaluation 



Characteristics, Quality and Reliability 

Acceptance of Quality and Reliability for Production 



-28- 



Package Name 







Package name 


Package 


Features 




Symbol 


Description 


Material* 


Lead pitch 


Lead shape 


Lead pull 
out direction 


■o 

01 


Standard 


D I P 


DUAL 

IN-LINE 

PACKAGE 


^ip 


P 
C 


2.54mm 
(100MIL) 


Through 

Hole 

Lead 


2-direction 


S I P 


SINGLE 
IN-LINE 
PACKAGE 


w 


P 


2.54mm 
(100MIL) 


Through 

Hole 

Lead 


1 -direction 


Z I P 


Zig-Zag 

IN-LINE 

PACKAGE 





P 


2.54mm 

(100MIL) 
Zig Zag 
inline 


Through 

Hole 

Lead 


1-direction 


PGA 


PIN 

GRID 

ARRAY 


^w 


c 


2.54mm 
(100MIL) 


Through 

Hole 

Lead 


Package 
side 


PIGGY 
BACK 


PIGGY 
BACK 


^ 


c 


2.54mm 
(100MIL) 


Through 

Hole 

Lead 


2-direction 


Shrink 


SDIP 


SHRINK 
DUAL 
IN-LINE 
PACKAGE 


^00 


p 


1.778mm 
(70MIL) 


Through 

Hole 

Lead 


2-direction 


SZIP 


SHRINK 
Zig-Zag 
IN-LINE 
PACKAGE 





p 


1.778mm 

(70MIL) 
Zig Zag 
inline 


Through 

Hole 

Lead 


1-direction 


•o 

3 
O 

E 

M 
t 

3 


Standard flat 
package 


Q F P 


QUAD 
FLAT 
L-LEADED 
PACKAGE 


^WIP 


p 


1.0mm 
0.8mm 
0.65mm 


Gull- 
Wing 


4-direction 


SOP 


SMALL 
OUTLINE 
L-LEADED 
PACKAGE 


^fl^ 


p 


1.27mm 
(50MIL) 


Gull- 
Wing 


2-direction 


Standard 
2-direction 
chip carrier 


S J 


SMALL 
OUTLINE 
J-LEADED 
PACKAGE 


40 


p 


1.27mm 
(50MIL) 


J-Lead 


2-direction 


Shrink flat 
package 


VQFP 


VERY 

SMALL 

QUAD 

FLAT 

PACKAGE 


^ 


p 


0.5mm 


Gull- 
Wing 


4-direction 


VSOP 


VERY 
SMALL 
OUTLINE 
PACKAGE 


^t* 


p 


0.65mm 


Gull- 
Wing 


2-direction 


Standard chip 
carrier 


Q F J 

(PLCC) 


QUAD 
FLAT 
J-LEADED 
PACKAGE 


+> 


p 


1.27mm 
(50MIL) 


J-Lead 


4-direction 


Q F N 
(LCC) 


QUAD 
FLAT 

NON-LEADED 
PACKAGE 


^^ 


c 


1.27mm 
(50MIL) 


Lead less 


Package 
side 



*P Plastic. C Ceramic 



29 




CCD Camera (Black/White) 




1) CCD Camera (Black/White) 



Type 


Application 


Function 


Page 


Optical 

size 

(inch) 


TV 
System 


Picture 

elements 

(HXV) 


Remarks 


ICX018CL 


CCD Image Sensor 
for B/W 


2/3 


EIA 


510X492 




33 


ICX021CL 


2/3 


CCIR 


500X582 




47 


ICX022AL-3 


CCD Image Sensor 
for B/W 


2/3 


EIA 


768X493 




61 


ICX024AL-3 


CCD Image Sensor 
for B/W 


2/3 


CCIR 


756X581 




75 


ICX026BL 


CCD Image Sensor 
for B/W 


1/2 


EIA 


510X492 


600mil shrink package 


89 


ICX027BL 


CCD Image Sensor 
for B/W 


1/2 


CCIR 


500X582 


600mil shrink package 


102 


ICX038AL 


CCD Image Sensor 
for B/W 


1/2 


EIA 


768X494 


600mil shrink package 


115 


ICX039AL 


CCD Image Sensor 
for B/W 


1/2 


CCIR 


752 X 582 


600mil shrink package 


131 



-32 



SONY. 



ICX018CL 



Solid-State Image Device for EIA B/W TV System 



Description 

ICX18CL is an interline transfer CCD solid-state 
imaging device developed for one-chip B/W cameras. 

Features 

• Number of effective picture elements 

510(H)x492 (V) 

• Number of optical black elements 
Horizontal (H) direction 

2 picture elements in front 
20 picture elements in back 
Vertical (V) direction 

12 picture elements in front 

• High sensitivity 

• Low smear 

• Anti-blooming 

• Low lag, no burning 

• Resistance to electro-magnetic field and micro- 
phonic noise 

• Precise image geometry 

• 7 characteristic: 1 



Package Outline 



(Unit: mm) 



20 pin DIP 



2-02.5 



31.4 max. 






q 




"itmmr 


1 1 I 








1 




0.46 


c 
E 
in 




1 1.27 



■ 



\ 




1 


1 


'////////, 


'//, 


12 pic 
Eleme 




_ <e — H 




|J 



2 picture 
Elements 



20 picture 
Elements 



Fig. 1 Layout of Optical Black Elements 



Device Organization 

• Interline transfer CCD image sensor 

• Unit cell size 17jum (H) x 13jum (V) 

• Number of dummy bits 8 bits horizontal, 1 bit vertical (even field only) 

• Chip size 10.0 mm (H) x 9.3 mm (V) 

• Thin polysilicon gate MOS diode sensor using the multi-layer interference effect 

• On-chip, high-sensitivity output amplifier 

• P-sub, P-well structure 



50185A-TO 



33 



SONY® 



ICX018CL 



Absolute Maximum Ratings 

• Supply voltages Vddi. Vqd2' an d Wd 

• Horizontal and vertical clock pins - SUB 

• Between horizontal clocks, between vertical clocks 

• Horizontal and vertical clock pins - Sensor gate 

• Pins other than those listed above 

• Storage temperature 

• Operating temperature 



-0.3 to +30V 1 
-20 to +20V 
22V 
18V 
-0.3 to +20V , 
-30 to +80°C 
-10 to+55°C 



(SUB = 0V) 



Block Diagram 




(1 5 >1l6j-il8Hl7 
PG HOG H 01 H 02 



* Note) — | | : Photosensor 



-34 



SONY® 



ICX018CL. 



Pin Configuration (Top View) 



Pin Description 



V*4 


1 


V 3 


v 2 i 


V 2 


< 3 / 


SUB 


[A 


v*i 


5, 


SG 


J5, 


OFD 


<L; 


ED 


K 


V DD1 


S 


V DD2 


*10 



Fig. 2 



■ 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V04 


Vertical register transfer clock input 


11 


OUT 


Signal output * 


2 


V03 


Vertical register transfer clock input 


12 


V G G 


Output amplifier gate bias * 


3 


V 2 


Vertical register transfer clock input 


13 


v S s 


Output amplifier source bias * 


4 


SUB 


Substrate 


14 


PD 


Output reset drain * 


5 


V01 


Vertical register transfer clock input 


15 


PG 


Output reset clock * 


6 


SG 


Sensor gate bias 


16 


HOG 


Horizontal register read out control bias * 


7 


OFD 


Anti-blooming bias * 


17 


"*2 


Horizontal register transfer clock input 


8 


ED 


Edge drain bias * 


18 


H*1 


Horizontal register transfer clock input 


9 


V DD1 


Power supply * 


19 


NC 




10 


V DD2 


Power supply * 


20 


NC 





Never supply negative voltage to pins. 



-35 



SONY® 



ICX018CL 



DC Bias Conditions 

(Some of the characteristics shown below are determined by the recommended circuit in Fig. 4. Refer to Note 1 through 8.) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


Substrate bias 


V SUB 









V 


V SUB = GND 


Output circuit supply voltages 


Vqd1 


19 


20 


21 


V 


VDD1 = V DD2 


V DD2 


19 


20 


21 


V 


V PD 


17 


18.1 


19.2 


V 


Note 1 


vss 


Grounded with 2.2kft resistor 




Note 2 


vgg 


7 


9 


11 


V 


Note 1 


Anti-blooming bias 


VOFD 


11 


12 


13 


V 


Note 3 


Edge drain bias 


VED 


v OFD 






HOG bias 


vhog 


0.8 


1.0 


1.2 


V 




Sensor gate bias 


V S G 


8.5 


9.5 


10.5 


V 


Note 3 



DC Characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


DC supply current 


IDD 




3.2 


4 


mA 


Note 4 


Input current 1 


Iin1 






1 


M A 


Note 5 


Input current 2 


Iin2 






10 


M A 


Note 6 



36- 



SONY® 



ICX018CL 



Cloct Voltage Conditions 

(Some of the characteristics shown below are determined by the recommended circuit in Fig. 4. Refer to Note 1 through 8.) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


Read out pulse 


v VT 


11.0 


13.0 


14.0 


V 


Note 3 


Vertical transfer clocks 


Low level 


VVL 


-5.5 


-5.0 


-4.5 


V 


Note 3 


Amplitude 


v v 


6.8 


7.5 




V 


Horizontal transfer clocks 


Low level 


V H L 


-4.4 


-4.0 


-3.6 


V 




High level 


v H h 


0.8 


1.0 


4.4 


V 


Note 7 


Amplitude 


V*H 


4.75 


5.0 


8.8 


V 


Note 7 


Output reset clocks 


Low level 


V PGL 


1.0 


1.3 


1.7 


V 


Note 8 


High level 


V PGH 


8.9 


9.3 


10.5 


V 




Amplitude 


v 0PG 


7.2 


8.0 


8.8 


V 





Clock Capacitance 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


Vertical transfer clock vs. GND 


C0V 




6200 




pF 




Between vertical transfer clocks 


C0VV 




1800 




pF 




Output reset clock 


C0PG 




14 




pF 





H02 



777T 777T 

Fig. 3 Horizontal Transfer Clock Equivalent Circuit 



37 



SONY® 



ICX018CL 



Note) 1. V PD , Vqg. and V H0G should be produced from V DD1 and V DD2 . Resistance precision should be ±5%. 
See Figs. 4 and 5. 

2. V ss should be self-biased and should be connected to GND through a 2.2kft (±5%) resistor. 

3. V VH H +5.1^V S g^V vt -1.5 Vvt^Vofd+2 (Unit: V) 

V VH H is the maximum level of the waveforms containing couplings of vertical transfer clocks V 01 to V44 
excluding the period in which a three level VT is pulsed. 

4. Total output amp current, when the load resistance is 2.2 k£2. 

5. The current to the substrate when 20 V is sequentially applied to Pins V 01 , V 2. V,^, V44, H 01 , and H 02 - 

6. The current to the substrate when 20V is applied to SG, ED, OFD, PD, HOG, TP1, and TP2 independently. 
The terminals, which have not been measured, should be connected to the ground. 



IE 
I 



-O V D D1. V DD2 
0.47ju 






-O V PD 
0.47/j 



X 



-O V GG 



0.47m 



IT 



-OVhog 



0.4 In 



7T7T 



Fig. 4 Recommended Circuit for Bias Setting of V DD 1, V DD 2< V PD. V GG» and\HOG 



38- 



SONY® 



ICX018CL 





















































Vs 


V v 
















^ 


^ 


















\v 




























































































-it- 





















16 17 18 19 20 

V PD (V) 



I 









































































$ 


\N 


\ 


s 












| 


^ 


$ 


















§ 


















V 




















































*-ft- 





















16 



18 



19 20 



V PD (V) 

Fig. 5 Bias Setting Range of Vpoi. VdD2. Vpd» and Vqq 

The shaded section is the recommended operating range. 



-39- 



SONY® 



ICX018CL 



Note) 7 V HH , V 0H , and V H l are determined as follows. 



V H H 




Middle point 
Fig. 6 Horizontal Transfer Clock Waveform 

8 VpG L , VpG H , and V p p(3 are determined as follows. 




Fig. 7 Output Reset Clock Waveform. 

V PGL is defined by the maximum level between Points A and B. Be careful not to allow ringing on the low side to be less 
than OV. 



-40 



SONY® 



ICX018CL 



Drive Pulse Waveform Conditions 




Fig. 8 Pulse Waveform 



I 



Symbol 


tWH 


tWL 


tr 


tf 


Unit 


Condition 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


H 1 




42 






42 






10 






10 




ns 


During scanning time 


H 2 




42 






42 






10 






10 




H 1 




6.8 












0.01 






0.01 




*is 


During parallel- 
serial conversion 


H 02 





























PG 


10 


42 






42 






10 






10 




ns 


Normally PG = H^i 


V l/V 02 




61.2 






2.1 






0.1 






0.1 


0.5 


MS 


During scanning time 


V 3/V*4 




3.6 






59.6 






0.1 






0.1 


0.5 


V 1/V 03 




19 












1 






1 




During read out from 
sensor 



Operating Characteristics 



Ta = 25°C See the Test Circuit. 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test method 


Condition 


Sensitivity 


S 


110 


160 


220 


mV 


1 




Saturation Output Voltage 


Vsat 


400 


530 


850 


mV 


2 




Video Signal Shading 


SV1 




10 


19 


% 


3 




Smear 


SM 




0.01 


0.04 


% 


4 




Dark Signal 


Vdt 






13 


mV 


5 


Ta = 55° C 


Dark Signal Shading 


AVdt 






4 


mV 


6 


Ta = 55" C 



-41 - 



SONY® 



ICX018CL 



Test Method 

o Test conditions 

1 ) The device drive conditions in the following measurements should be adjusted to the typical values of the DC and 
clock voltage conditions. (See Fig. 9.) 

2) In measurements mentioned below, blemishes should be excluded. Unless specified, the optical black level should 
be the reference for the signal output, and the value measured at Point B in Fig. 9 should be used. 

o Definition of standard imaging condition 

1 ) Standard imaging condition 1: Use Pattern box (Brightness 706 nt. 3200°K Halogen source) at F8 with FUJINON 
lens H6 x 12. 5D (F1.4). CM-500S (1.0 mmt) should be used as an IR cut filter. 

2) Standard imaging condition 2; Uniformity of a light source within 2%. The light-source color temperature should 
be 3200°K, and CM-500S (1.0 mmt) should be used as an IR cut filter. The quantity of light should be adjusted to 
the average value of output voltage Vs shown in each item. 

1. Set to the standard imaging condition 1 and measure output signal in the center of the screen. 

2. Set to the standard imaging condition 2, adjust the intensity of light, check anti-blooming, then measure the minimum 
value of signal for the whole screen. 

3. After setting up standard imaging condition 2, set the pattern box on the entire screen and measure the maximum and 
minimum output voltages of Channel (Vmax, Vmin) adjusting Vs to 300 mV. 

Vmax - Vmin 

SV, h x 100(%) 

Vs 

4. After setting up standard imaging condition 2, set the pattern box on a vertical 1/10 screen. Measure the average signal 
voltage Vs and maximum value Vsm during vertical blanking. (Vs = 300 mV, 1/10 V method) 







y/A 


W//A 


i 


V 






v///. 


V/10 




• 




^^/ 


t 



SM = — r^x 100 (%) 



vsm 



v s 



Black Level 



5. Average dark signal at ambient temperature of 55°C. 

6. Measure maximum and minimum dark signal (Vdmax, Vdmin). 
Blemishes should be excluded. The temperature should be 55°C. 

AVdt = (Vdmax - Vdmin) 



42- 



SONY® 



ICX018CL 



S/H pulse 



2SK43 



rC.r* 







Cancel pulse 



3.3 M F Wr = = 2pF 



3SK106 



Test point 
output 



777T 



0.47mF 



+20V> a r 



+ 



0.47 



w 



TT 



0.47 



11 12 13 14 15 16 17 18 19 20 

ICX 018CL 
10 9876 5432 1 



+9.5V > 
+12V> 



MMH 
0026 




MMH 
0026 



MMH 
0026 



V H H 

> XH1 

> XH2 
V H L 

V V H 
) XV2 

) XV4 
V VL 
V V T 



I 



| — 0^— OXSG2 

-0^*p— O^-O XSG1 

V V H<=V VL + V 0V > 



Fig. 9 Test Circuit 



Note) XV 1 denotes inverted level of V1. The others are the same. 



43 



SONY® 



ICX018CL 



Typical Spectral Response 













— i — i — i i 




— 1 — i — i — i — 




0.8 
0.7 

n r 




































































0.5 






















0.3 
2 


































0.1 
00 




























i l i i 


i i i i 


_i .... I"Sb»~_ 



700 800 

Wavelength [nm] 



1100 



-44 



SONY® 



ICX018CL 





L 






^2 

-1 
^525 

;520 






E 


E E 


- 












;285 
^280 
:275 
:270 
^265 
^260 






D 


D < 




1 
E 










E 20 
E 15 
E 10 

= 5 
-3 
-2 
~1 
-525 

:520 






E 


E E 




I 

i 
t 

[ 

CN 

o> 

<» 

NT 

c 





I 



Q _l t- CM 

I ID II 



>> >> 



«- CN O 

Q to w «- cm co <fr u 
I XX > > > > O 



45 



SONY® ICX018CL 

Notes on Application 

' 1 ) Electrostatic protection 

It is crucial that static discharge be controlled and minimized. Handle most carefully. 

2) Soldering 

Make sure that the package temperature does not exceed 80°C. Solder dipping in a mounting furnace causes broken 
glass, filter delamination, and other defects. Use a grounded 30 W soldering iron and solder in less than 2 seconds for 
each pin. Cool sufficiently when reworking or remounting. 

3) Glass surface dust 

Do not touch glass plates. Be careful not to have objects contact glass surface. Clean with a cotton bud when the 
glass surface is stained. Do not use an organic solvent other than ethyl alcohol. Store in a special container to prevent 
dust and dirt. To prevent dew condensation, preheat or precool when moving to a room in which temperature differ- 
ence is great. 

4) ROM for blemish compensation 

This device is shipped in a special container together with ROM. Be most careful about combination when remount- 
ing. 

5) Care must be taken to avoid exposure to strong light for a long time. 



46 



SONY. 



ICX021CL 



Solid-State Image Device for CCIR B/W TV System 



Description 

ICX021CL is an interline transfer CCD solid-state 
imaging device developed for one-chip B/W cameras. 

Features 

• Number of effective picture elements 

500 (H) x 582 (V) 

• Number of optical black elements 
Horizontal (H) direction 

2 picture elements in front 
30 picture elements in back 
Vertical (V) direction 

14 picture elements in front 

• High sensitivity 

• Low smear 

• Anti-blooming 

• Low lag, no burning 

• Resistance to electro-magnetic field and micro- 
• phonic noise 

• Precise image geometry 

• y characteristic: 1 



Package Outline 



(Unit: mm) 



20 pin DIP 



2-02.5 





\ 




% 






1 


i 


'////////, 


b 


14 pic 
Elem< 




— H 




|J 



2 picture 
Elements 



30 picture 
Elements 



Fig. 1 Layout of Optical Black Elements 



Device Organization 

• Interline transfer CCD image sensor 

• Unit cell size \1 \xm (H) x 11 /urn (V) 

• Number of dummy bits 8 bits horizontal, 1 bit vertical (even field only) 

• Chip size 10.0 mm (H) x 9.3 mm (V) 

• Thin polysilicon gate MOS diode sensor using the multi-layer interference effect 

• On-chip, high-sensitivity output amplifier 

• P-sub, P-well structure 



-47- 



SONY® 



ICX021CL 



Absolute Maximum Ratings 

• Supply voltages V DD1 , V D D2. and V PD -0.3 to +30V V 

• Horizontal and vertical clock pins - SUB -20 to +20V 

• Between horizontal clocks, between vertical clocks 22V 

• Horizontal and vertical clock pins - Sensor gate 18V 

• Pins other than those listed above -0.3 to +20V, 

• Storage temperature —30 to +80 C 

• Operating temperature —10 to +55 C 



(SUB = 0V) 



Block Diagram 




PQ HOG H 01 H 02 



NC NC 



* Note) — | | : Photosensor 



48- 



SONY® 



ICX021CL 



Pin Configuration (Top View) 



Vt 


JJ 


(20) NC 


V 3 


T) 


@ NC 


V 2 


CD 


(l8) H 01 


SUB 


4J 


©H 02 


V 1 


CD 


U6) HOG 


SG, 


J) 


M5) PG 


OFDl 


CD 


U4)PD 


ED i 


2) 


U3) V SS 


V DD1 I 


jD 


U2)V GG 


V DD2I 


J°) 


Ml) OUT 



Fi 9 . 2 



I 



Pin Description 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V04 


Vertical register transfer clock input 


11 


OUT 


Signal output * 


2 


V03 


Vertical register transfer clock input 


12 


vgg 


Output amplifier gate bias * 


3 


V02 


Vertical register transfer clock input 


13 


vss 


Output amplifier source bias * 


4 


SUB 


Substrate 


14 


PD 


Output reset drain * 


5 


V01 


Vertical register transfer clock input 


15 


PG 


Output reset clock * 


6 


SG 


Sensor gate bias 


16 


HOG 


Horizontal register read out control bias * 


7 


OFD 


Anti-blooming bias * 


17 


H02 


Horizontal register transfer clock input 


8 


ED 


• Edge drain bias * 


18 


H01 


Horizontal register transfer clock input 


9 


V DD1 


Power supply * 


19 


NC 




10 


V DD2 


Power supply * 


20 


NC 





Never supply negative voltage to pins. 



49 



SONY® 



ICX021CL 



DC Bias Conditions 

(Some of the characteristics shown below are determined by the recommended circuit in Fig. 4. Refer to Note 1 through 8.) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


Substrate bias 


V SUB 









V 


V SUB = GND 


Output circuit supply voltages 


V DD1 


19 


20 


21 


V 


VDD1 - VDD2 


VDD2 


19 


20 


21 


V 


Vp D 


17 


18.1 


19.2 


V 


Note 1 


vss 


Grounded with 2.2kC resistor 




Note 2 


V G G 




9 




V 


Note 1 


Anti-blooming bias 


VoFD 


11 


12 


13 


V 


Note 3 


Edge drain bias 


VED 


VOFD 




HOG bias 


Vhog 


0.8 


1.0 


1.2 


V 




Sensor gate bias 


V S G 


8.5 


9.5 


10.5 


V 


Note 3 



DC Characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


DC supply current 


'DD 




3.2 


4 


mA 


Note 4 


Input current 1 


Iin1 






1 


MA 


Note 5 


Input current 2 


Iin2 






10 


HA 


Note 6 



-50- 



SONY® 



ICX021CL 



Clock Voltage Conditions 

(Some of the characteristics shown below are determined by the recommended circuit in Fig. 4. Refer to Note 1 through 8.) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


Read out pulse 


V VT 


11.0 


13.0 


14.0 


V 


Note 3 


Vertical transfer clocks 


Low level 


V VL 


-5.5 


-5.0 


-4.5 


V 


Note 3 


Amplitude 


v 0V 


6.8 


7.5 




V 


Horizontal transfer clocks 


Low level 


Vhl 


-4.4 


-4.0 


-3.6 


V 




High level 


v H h 


0.8 


1.0 


4.4 


V 


Note 7 


Amplitude 


V H 


4.75 


5.0 


8.8 


V 


Note 7 


Output reset clock 


Low level 


V PGL 


1.0 


1.3 


1.7 


V 


Note 8 


High level 


VpGH 


8.9 


9.3 


10.5 


V 




Amplitude 


V<*,PG 


7.2 


8.0 


8.8 


V 





Clock Capacitance 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


Vertical transfer clock vs. GND 


c^v 




6200 




pF 




Between vertical transfer clocks 


C0VV 




1800 




pF 




Output reset clock 


C0PG 




14 




pF 





H01 



777T 



60P 



7777" 



H 2 



Fig. 3 Horizontal Transfer Clock Equivalent Circuit 



51 - 



SONY® 



ICX021CL 



Note) 1. Vpo, Vqg/ and v HOG should be produced from Vqdi ar| d Vdd2- Resistance precision should be ±5%. 
See Figs. 4 and 5. 

2. V ss should be self-biased and should be connected to GND through a 2.2 kQ. (±5%) resistor. 

3. V V HH + 5.1 ^ V SG ^ V VT - 1 .5 V VT ^ Vqfd + 2 (Unit: V) 

V VHH is the maximum level of the waveforms containing couplings of vertical transfer clocks V^ to 
V^4 excluding the period in which a three level VT is pulsed. 

4. Total output amp current, when the load resistance is 2.2 kS2. 

5. The current to the substrate when 20V is sequentially applied to Pins V i , V^. V<*>3' V44, H^ , and H^- 

6. The current to the substrate when 20V is applied to SG, ED, OFD, PD, HOG, TP1, and TP2 independently. 
The pins which have not been measured should be connected to the ground. 



I 



-O Vdd1- v DD2 



0.47ai 






-O V PD 
0.47m 



TX 



-O vqg 

0.47/i 



XT 



-OVhog 

0.47m 



Fig. 4 Recommended Circuit for Bias Setting of Vdqi. VdD2. VpD» Vqq, and V H og 



-52- 



SONY® 



ICX021CL 



22 



Q 
Q 

> 19 



















































^ 


^ 


V V 
















^ 


V 


















^ 




















NX 








































































-<*- 





















16 17 18 19 20 

Vp D (V) 



I 

























































\\\ 


s 
s 














nN 




X X 


s 












\^\ 


^ 


















NN 




















\\ 




















V 
































u- 





















16 17 18 19 20 

V PD (V) 

Fig. 5 Bias Setting Range of V DD1 , V D0 2, Vpo, and V G q 

The shaded section is the recommended operating range. 



-53- 



SONY® 



ICX021CL 



Note) 7 V HH , V,*h. and V HL are determined as follows. 



v H h 




Middle point 
Fig. 6 Horizontal Transfer Clock Waveform 

8 VpG L . V PGH. and V<£pg are determined as follows. 




Fig. 7 Output Reset Clock Waveform. 

V PGL is defined by the maximum level between Points A and B. Be careful not to allow ringing on the low side to be less 
than OV. 



54- 



SONY® 



ICX021CL 



Drive Pufee Waveform Conditions 




Fig. 8 Pulse Waveform 



Symbol 


*WH 


*WL 


tr 


tf 


Unit 


Condition 


Mm. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


H 1 




43 






43 






10 






10 




ns 


During scanning time 


H 2 




43 






43 






10 






10 




H 1 




6.87 












0.01 






0.01 




MS 


During parallel- 
serial conversion 


H 2 





























PG 


10 


43 






43 






10 






10 




ns 


Normally PG = H^ 


V«1/V 02 




61.8 






2.12 






0.1 






0.1 


0.5 


MS 


During scanning time 


V 03 /V04 




3.64 






60.2 






0.1 






0.1 


0.5 


V 1/V 03 




19.2 












1 






1 




During read out from 
sensor 



I 



Operating Characteristics 



Ta = 25 C See the Test Circuit. 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test method 


Condition 


Sensitivity 


S 




130 




mV 


1 




Saturation Output Voltage 


Vsat 


360 


440 


850 


mV 


2 




Video Signal Shading 


SV1 




11 


20 


% 


3 




Smear 


SM 




0.01 


0.04 


% 


4 




Dark Signal 


Vdt 






13 


mV 


5 


Ta = 55° C 


Dark Signal Shading 


AVdt 






4 


mV 


6 


Ta = 55° C 



-55- 



SONY® 



ICX021CL 



Test Method 

o Test conditions 

1 ) The device drive conditions in the following measurements should be adjusted to the typical values of the DC and 
clock voltage conditions. (See Fig. 9.) 

2) In measurements mentioned below, blemishes should be excluded. Unless specified, the optical black level should 
be the reference for the signal output, and the value measured at Point B in Fig. 9 should be used. 

o Definition of standard imaging condition 

1) Standard imaging condition 1: Use pattern box (Brightness 706 nt. 3200°K Halogen source) at F8 with 
FUJINON lens H6 x 12.5D (F1.4). CM-500S (LOmmt) should be used as an IR cut filter. 

2) Standard imaging condition 2: Uniformity of a light source within 2%. The light-source color temperature should 
be 3200°K, and CM-500S (LOmmt) should be used as an IR cut filter. The quantity of light should be adjusted 
to the average value of output voltage Vs shown in each item. 

1. Set to the standard imaging condition 1 and measure output signal in the center of the screen. 

2. Set to the standard imaging condition 2, adjust the intensity of light, check anti-blooming, then measure the minimum 
value of signal for the whole screen. 

3. After setting up standard imaging condition 2, set the pattern box on the entire screen and measure the maximum and 
minimum output voltages of Channel (Vmax, Vmin) adjusting Vs to 300 mV. 

Vmax - Vmin 

SV! = x 100(%) 

Vs 

4. After setting up standard imaging condition 2, set the pattern box on a vertical 1/10 screen. Measure the average signal 
voltage Vs and maximum value V$m during vertical blanking. (Vs = 300 mV, 1/10 V method) 



t 


W//////A 


\ 


I 




/////// 


\ 


V 


/ /// 




//// 


V/10 






y///////// 


t 




1 


////////// 





SM =-^- x 100 (%) 
V s 



V S M 



V S 



Black level 



5. Average dark signal at ambient temperature of 55 C. 

6. Measure maximum and minimum dark signal (Vdmax, Vdmin). 
Blemishes should be excluded. The temperature should be 55°C. 

AVdt = (Vdmax - Vdmin) 



-56- 



SONY® 



ICX021CL 



+20V>_ 



+9.5V >- 
+12V>- 



rti.r* 



Cancel pulse 




S/H pulse 



-* 



2pF 



-rrrr 



0.47 M F 



56K 




mT 7m 



11 12 13 14 15 16 17 18 19 20 

ICX021CL 
10 9876 54 32 1 



X 



PG O- 



MMH 
0026 



PGL 



Fig. 9 Test Circuit 
Note) XV1 denotes inverted level of VI. The others are the same. 



-<+12V 




Test point 



MMH 
0026 



MMH 
0026 



MMH 
0026 



MMH 
0026 



VHH 
5 XH1 

) XH2 
V H L 

' V VH 
) XV2 

> XV4 
V V L 

V VT 

XSG2 

1 XSG1 

V V h(=V V L + V 0V I 

) XV1 
) XV3 
• V VL 



I 




-57- 



SONY® 



ICX021CL 



Typical Spectral Response 



» 0.5 




400 500 



600 700 800 900 

Wavelength [nm] 



1000 1K 



1200 



58- 



SONY® 



ICX021CL 



s§ 



ie30 - 



§25 Z 









3 340 
^335 
^330 
= 325 
= 320 
= 315 
= 310 






D 


i < 


c 












= 25 

= 20 

= 15 

= 10 

= 5 
-3 
-2 
-1 
1625 

Z 620 


= 




E 


E E 


E 


00 

in 





I 



I 00 



>> >> 



_i _ i Q ww i- in n * 
u_ 03 i XX > > > > 



-59- 



SONY® ICX021CL 

Notes on Application 

1 ) Electrostatic protection 

It is crucial that static discharge be controlled and minimized. Handle most carefully. 

2) Soldering 

Make sure that the package temperature does not exceed 80°C. Solder dipping in a mounting furnace causes broken 
glass, filter delamination, and other defects. Use a grounded 30 W soldering iron and solder in less than 2 seconds for 
each pin. Cool sufficiently when reworking or remounting. 

3) Glass surface dust 

Do not touch glass plates. Be careful not to have objects contact glass surface. Clean with a cotton bud when the 
glass surface is stained. Do not use an organic solvent other than ethyl alcohol. Store in a special container to prevent 
dust and dirt. To prevent dew condensation, preheat or precool when moving to a room in which temperature differ- 
ence is great. 

4) ROM for blemish compensation 

This device is shipped in a special container together with ROM. Be most careful about combination when remount- 
ing. 

5) Care must be taken to avoid exposure to strong light for a long time. 



-60- 



SONY. 



ICX022AL-3 



Interline-type CCD Image Sensor 



Description 

ICX022AL-3 is an interline-type CCD image 
sensor designed for B/W video cameras. 

Effective pixels number 768 horizontally and 493 
vertically. 

Features 

• Image size: 2/3 inches (8.8 mm(H) x 6.6 mm(V)) 

• . Effective pixels: 768 (H) x 493 (V) 

• Effective optical black 
Horizontal: Front 5 pixels 

Back 45 pixels 
Vertical: Front 16 pixels 
Back 4 pixels 

• High resolution, high sensitivity and low noise. 

• Low lag and low smear 

• Low dark current 

• Anti-blooming function 

• Electronic shutter function 

• Neither figure distortion nor microphonic noise. 

• y characteristics: 1 



Package Outline 



Unit: mm 



2-4>2.S 



<t>2.0 
Reference hole 



20 pins DIP (Ceramic) 

3 1 0±0 4 Effective picture elements center 



I 





_lk» J 



I 



Element Structure 

• Interline type CCD image sensor 

• Chip size: 10.0 mm(H)x 8.2 mm(V) 

• Unit cell size: 1 1 .0 ^m(H) x 1 3.0 nm(V) 

• Dummy bits: horizontal 22-bits, vertical 1 -bit (even fields only) 

• Built-in high-sensitivity output amplifier 



-(H) 



493 



Pin 11 side - *! 




Pin 1 side 



Fig. 1 Optical block configuration 



81129-YA 



61 



SONY® 



ICX022AL-3 



Imaging Device Function Block and Pin Configuration 




^i 


W+4 


—} 


)v*s 


—s 


)V*2 




)SUB 




)GND 


~J 


)V4,i 



*Note)— I I : Photo sensor 



Pin Description 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V(|>4 


Vertical register transfer clock 


11 


VOUT 


Signal output 


2 


V<|)3 


Vertical register transfer clock 


12 


Vgg 


Output amplifier gate 


3 


V<|>2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (OFD) bias 


14 


GND 


GND 


5 


GND 


GND 


15 


PD 


Pre-charge drain bias 


6 


V<)>1 


Vertical register transfer clock 


16 


PG 


Output reset clock 


7 


Vl 


Protective transistor bias 


17 


Vl 


Protective transistor bias 


8 


NC 




18 


H(|>2 


Horizontal register transfer clock 


9 


NC 




19 


H(|)1 


Horizontal register transfer clock 


10 


Vdd 


Output amplifier drain supply 


20 


GND 


GND 



-62 



SONY® 



ICX022AL-3 



Absolute Maximum Ratings 



Item 


Ratings 


Unit 


Remarks 


SUB - GND 


. -0.3 to +55 


V 




Vdd, PD, Vout, Vss - GND 


-0.3 to +20 


V 




Vdd, PD, Vout, Vss - SUB 


-55 to +10 


V 


Note 1 


Horizontal and vertical transfer clock inputs - - GND 


-15 to +20 


V 




Horizontal and vertical transfer clock inputs - - SUB 


-65 to +10 


V 


Note 1 


Potential difference between vertical transfer clock inputs 


15 


V 


Note 2 


Potential difference between horizontal transfer clock inputs 


17 


V 




H<>1 , H<|>2 - V<H 


-17 to +17 


V 




PG, Vgg -GND 


-10 to +15 


V 




PG, Vgg - SUB 


-55 to +10 


V 


Note 1 


Vl - SUB 


-65 to +0.3 


V 




Pins other than GND, SUB and Vl - Vl 


-0.3 to +27 


V 




Storage temperature 


-30 to +80 


°C 




Operation guarantee ambient temperature 


-10 to +55 


°C 





Note) 1 . This image sensor consists of an N substrate P-Well structure where a protection transistor is 
connected to each pin accordingly. If a voltage exceeding 10 V is applied to pins other than 
Vl against the SUB pin, a punch through current will flow. Since a series resistance Rl is 
located between each pin and SUB, the device will withstand destruction through any rush 
voltage over 10 V. The series resistance Rl must be more than 1 kft between Vp-p and 
SUB, more than 500 £2 between Vout and SUB and more than 5 kft between Vss or PD and 
SUB. The series resistance between other pins (except Vl and GND) and SUB must be 
more than 5kQ. 



■ 



1 ) Vdd, PD, Vout and Vss pins 
Every pin o- 



Vl 
GNDo 



^ 



SUB °- 



2) Pins other than 1 ) (except Vl and GND) 
Every pin °- 



r 




SUB 



Fig. 2 Equivalent circuit 



2. In case of clock width <10 u.s and clock duty factor <0.1%, up to 27 V is guaranteed. 



-63- 



SONY® 



ICX022AL-3 



Electrical Characteristics 
Bias conditions 



Item 



Supply voltage of output circuit 



Substrate voltage adjustable range 



Regulation range after substrate voltage 
adjustment 



Protection transistor bias 



Symbol 



Vdd 



Vpd 



Vgg 



Vss 



VSUB 



VsUB 



Vl 



Min. 



14.55 



14.55 



1.6 



Typ. 



15.0 



15.0 



2.0 



Max. 



15.45 



15.45 



2.4 



Unit 



Ground with a 390 Q resistance 



19 



V 



Remarks 



Note 1 



Note 1 



±5% 



Note 2 



To be the vertical transfer clock low-level clamp bias 



DC characteristics 



Item 



Output circuit current 



Input current 



Symbol 



Idd 



||N1 



Min. 



Typ. 



5.0 



Max. 



10 



Unit 



mA 



HA 



HA 



Remarks 



Note 3 



Note 4 



Note 5 



Note) 1. Vpd and Vdd must have the same voltage. 

2. Indication of the substrate voltage (Vsub) set value: 

The set value is indicated on the rear of the imaging device by a code. Adjust to obtain the 
indicated voltage at the SUB pin. 

Vsub code - Two digit indication □ □ 

t t 

Integral part Decimal part 



The integral code correspond to the following 


actu 


al va 


lues: 








Integral codes 


9 


A 


B 


C 


D 


E 


F 


G 


H 


I 


J 


Numerical value 


9 


10 


11 


12 


13 


14 


15 


16 


17 


18 


19 



EX.) F5 -> 15.5 (V) 

3. Ground Vss with a 390 Q resistance 

4. 1) Current flowing to the ground when a voltage of 20 V is applied to Vdd, PD, Vout, Vss 

and SUB pins. Test ground all the pins other than those under test. 

2) Current flowing to the ground when a voltage of 20 V is applied to V<>1 , V<|)2, V(|>3, V<t>4, 
H(|>1 and H<t>2 pins in the order. Apply pin a voltage of 20 V to the SUB pins and 
ground pins other than those under test. 

3) Current flowing to the ground when a voltage of 15 V is applied to PG and Vgg pins in 
the order. Apply a voltage of 15 V to the SUB pin and ground pins other than those 
under test. 

4) Current flowing to the ground when Vl pin is grounded, GND and SUB pins are open and 
a voltage of 27 V is applied to other pins. 

5. Current flowing to the ground when a voltage of 55 V is applied to the SUB pin. In this 
case ground pins other than those under test. 



-64 



SONY® 



ICX022AL-3 



Clock Voltage Conditions 
Clock voltage 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Read clock voltage 


VVT 


13.0 




15.0 


V 


Note 1 


Vertical transfer clock voltage 


VvHH 






1.3 


V 


Note 2 


VVH 


-0.5 




0.7 


V 


V»v 


8.0 






V 


VVLL 


-10.5 






V 


Horizontal transfer clock voltage 


Vhhh 






5.5 


V 


Note 3 


Vhl 


-3.0 




-1.7 


V 


V„H 


5.2 




8.0 


V 


Vhll 


-3.0 






V 


Output reset clock voltage 


Vpgl 









V 


Note 4 


VoPG 


7.0 




13.0 


V 


Substrate clock voltage 


V»SUB 


23.0 




27.0 


V 


Note 5 



Clock capacitance 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Vertical transfer clock - GND 


C*v 




5000 




PF 




Capacitance between vertical transfer 
clocks 


C«w 




1500 




PF 




Horizontal transfer clock - GND 


C»H 




180 




PF 




Capacitance between horizontal transfer 
clocks 


C*HH 




50 




PF 




Output reset clock - GND 


C»PG 




10 




PF 




Substrate clock - GND 


C«SUB 


. 


500 




PF 





I 



H+i- 



C4HH 

-r II T h+2 



:C*h 



:C+h 



Fig. 4 Equivalent circuit of horizontal transfer clock capacitance 



65- 



SONY® 



ICX022AL-3 



Note) 1 . Read clock voltage 

1 ) The symbol 'V expresses the voltage level while the read clock "Vt" of the vertical transfer clocks 
("V<t>1 " and "V<|)2") is set. The maximum value in the read clock waveform is expressed as "<|>h". 

2) The period in which the voltage level becomes (<|>h - <|>l)/2 is expressed as "tsr". The voltage levels 
at "tst/2" are expressed as "Vn" (at V<>1) and "Vt 3 " (at V<|>3). The smaller of "Vn" and "Vt3" is 
defined as the read clock voltage "Vvt". 



VT1.VT2 




1 + L=V+1,V»3 LEVEL 



Fig. 5 Read clock wave length 



2. Vertical clock voltage (Refer to Fig. 6) 

T = 559 ns (with a horizontal driving frequency of 14.32MHz) 
1 ) Definition of the vertical transfer clock amplitude 



Level 2T after the rising edge of " V<|>3' 
Level T after the falling edge of "V<))i" 
Level 2T after the rising edge of "VV 
Level T after the falling edge of "V<|)2" 
Level 2T after the rising edge of "VcK 
Level T after the falling edge of "V<t>3" 
Level 4T after the rising edge of " \A|>2' 



is expressed as "V3a". 
is expressed as "Vib". 
is expressed as "Via". 
is expressed as "V2b". 
is expressed as "Via". 
is expressed as "V3b". 
is expressed as "V2A". 



Level 3T after the falling edge of "Vfa" is expressed as "V4b". 

V<|)2 Level T after the falling edge of "V<|>r is expressed as "V2c". 
V<t>3 Level T after the falling edge of "V<|>2" is expressed as "Vsc". 
V<)>4 Level T after the falling edge of "V<J>3" is expressed as "Vtc". 
V<))1 Level 3T after the falling edge of "V<t>4" is expressed as "Vic". 

A31 = (V3A + V2C) / 2 - VlB 

A42 = (V»a + Vsc) / 2 - V 2 b 
A13 = (Via + V>c)/2- Vsb 
A24 = (Vja + V 1C ) / 2 - V4B 

The minimum value of these is defined as the vertical transfer clock amplitude "V<t>v". 



2) The maximum value from Via, V2A, V», and V4A, is defined as the high level Vvh of the clock. 

3) The minimum level in a waveform which includes the vertical clock coupling is expressed as "Vvll". 
"Vvhh" expresses the maximum level except in the period where read clock Vt is applied (in V<t>i and 
V<>3 only). 



-66- 



SONY® 



ICX022AL-3 




Fig. 6 Vertical transfer clock waveform 

T = 559ns (with a horizontal driving frequency of 14.32 MHz) 



3. Horizontal transfer clock voltage 

1) For the horizontal transfer clocks "H<J>i" and "H<|)2", the low-level period is expressed as 
"thl" and the high-level period is expressed as "thh". The symbol "tho" expresses the 
overlap period of "thl" and "thh". 

2) The low level at which "thl", "thh" and "tho" satisfy the following time duration is 
expressed as "Hib" and "HW. 

And the high level is expressed as "Hia" and "H2a" 

thl > 10ns, thh > 10ns, tho > 5ns 



A 21 = Hia - H 2B 
A 12 = H 2 a - Hib 

3) The minimum level in the waveform which contains the coupling of the horizontal transfer 
clocks "H<t)1" and "H<t>2" is expressed as "vW" and the minimum level is expressed as 

"Vhhh". 

Vhhh 

H2A-T 




Fig. 7 Horizontal transfer clock waveform 



67- 



SONY® 



ICX022AL-3 



4. Output reset clock voltage 

1) The low level of the output reset clock is to be the GND in the circuit. 

2) The amplitude of the output reset PG clock "V<t>PG" is defined as the maximum value of 
the amplitude which provides a high level period over 10 ns. 



More than 1 ns 



High level 



Low level 




Wpg 



Fig. 8 Waveform of PG clock 



5. Substrate clock voltage 

1) Substrate voltage is expressed as <|>l and the maximum value of the substrate clock 
waveform as <|>h. 

2) The period during which voltage level reaches (4>h - <|>l)/2 is expressed as tsr. The 
difference of voltage level with (|>L at tsr/2 is defined as substrate clock voltage V<|>sub. 




Fig. 9 Substrate clock waveform 
Driving Clock Waveform Conditions 

1) Definition of <h (100%) and <|>l (0%) 

(1) For the horizontal transfer clocks (H<t>i, Hfo), output reset clock (PG<|>) and vertical transfer 
clocks (V<j>i, V<t>2, V<t>3, V<|>4), the maximum value in the clock waveform which includes no 
coupling is expressed as "<|)h" and the minimum value is expressed as "<(m.". 

(2) For the read clock (Vt), the maximum value in the clock waveform is expressed as "<|>h"."<|>l" 
expresses the voltage level while the read clock (Vt) of the vertical transfer clocks (V<>1, V<|>3) is 
applied. 

(3) For the substrate clock (SUB<t>), the maximum value in the clock waveform is expressed as "<K' 
and the substrate voltage (Vsub) as "<t>L". 

2) Standard driving clock conditions (Typ.) 



-68 



SONY® 



ICX022AL-3 



Horizontal drive frequency: 14.32MHz 



Clock 
(Symbol) 


twh 


twl 


tr 


tf 


Unit 


Remarks 


H<|>1 


18 


33.7 


10 


8 


ns 


Imaging period 


H<|> 2 


18 


33.7 


10 


8 


H$i 


4.9 




0.10 


0.01 


^is 


Parallel-serial converting period 


H<()2 




4.9 


0.10 


0.01 


())PG 


12 


53.7 


2 


2 


ns 




v<t»yV(t>2 


61.6 


1.6 


0.1 


0.1 


US 


Imaging period 


V<()3A/<t)4 


2.8 


60.45 


0.05 


0.1 


V^T 


2.4 




0.2 


0.1 


Reading period 


SUB<|> 


1.0 




0.08 


0.1 


US 


Electron sweep-off period 



fi.10%1 




■ 



Fig. 10 Clock waveform 



Imaging Characteristics 



(For the testing circuit, see Fig. 11.) 
Ta=25°C 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Testing method 


Remarks 


Sensitivity 


sg 


140 


190 




mV 


1 




Output saturation signal 


Vsat 


600 






mV 


2 


Note 


Blooming margin 




1000 






times 


3 


Note 


Smear 


Smr 




0.007 


0.015 


% 


4 




Video signal shading 


Svg 






25 


% 


5 




Dark signal output 


Vdt 






2 


mV 


6 


Ta=55°C 


Dark signal shading 


AVdt 






1 


mV 


7 


Ta=55°C 



Note) Saturation signal and blooming margin are guaranteed only when the substrate voltage has been 
set to the voltage indicated on the back of the imaging device. 



69- 



SONY® 



ICX022AL-3 



Test Methods 
Conditions 

1) The conditions required to drive the device through the following tests are converted by the 
bias conditions and the clock voltage conditions. The test circuit shown in Fig. 11 is used for 
evaluating and testing the characteristics. 

2) Blemish are excluded from the following tests and the signal output is based on the optical 
black level unless otherwise specified. The value obtained at the output test point becomes 
the test value. 

Standard imaging conditions 

1) Shoot the PTB-100 pattern box (luminance 706 Nit, color temperature 3200°K) with no pattern, 
using a FUJINON H6 x 12.5D (F1.4) lens at F5.6. Use the CM-500S (1.0 mmt) filter to cut 
off infrared rays. 

2) Shoot a light source (color temperature 3200°K) which provides a uniform brightness within 2% 
over the whole screen. 

For infrared cut-off filter, use the CM-500S (1.0 mmt) 

1. Set the standard imaging condition 1) and test signal voltages the center of the screen. 

2. Set to standard imaging condition 2) and adjust the light intensity to about ten times the intensity 
obtained at a signal voltage of 200 mV. Then obtain the minimum value of the signal voltage 
over the whole screen. 

3. Set to imaging condition 2) and adjust the light intensity to about 1000 times the intensity obtained 
at a signal voltage of 200 mV. At that time make sure there is no blooming and the vertical 
resistor is not saturated. 

4. Set to standard imaging condition 2) and adjust the light intensity so that the signal voltage (Vsg) 
becomes 200 mV. Then, turn Vt off and obtain the maximum value of the signal voltage "Vsm" 
after stopping the horizontal resistor 50 H at the effective picture element. 

Smr = VsM x — x — x 100 (%) 
Vsg 50 10 

(Converted into 1/10 V system) 

5. Set to standard imaging condition 2) and test the signal voltage to obtain maximum (Vg max) and 
minimum (Vg min) values. 

The light intensity is adjusted so that the average value of the signal voltage (Vg average) 
becomes about 200 mV. 

VsGmax - VsGmin .._. . .. 

Svg = x 100 (%) 

Vsg average 

6. Measure the mean voltage of the dark current signal based on the horizontal free-transfer level in 
a light-shaded condition with an ambient temperature of 55°C. 

7. Following measurement 6, test the dark current signal voltage to obtain the maximum (Vdmax) and 
minimum (Vdmin) values. Spot defects are ignored in this test. 



-70 



SONY® 



ICX022AL-3 



Electrical Characteristics Test Circuit 



Output test point 




XSUBJfo 



SUB 
driver 



lOfl 



VSUB o- 



ICX022AL-3 



X 



iifi: 



Vifi: 



10)/ 



PG 
driver 



-o Vpgh 

-oXPG 



1 o Vpgl 

I o Vhh 

J (Vhl+V+h) 



H 
driver 



XH2 

Xhi 



V 
driver 



I0M 



v 

driver 



V+v 

— °XV4 

»XV3 

oXSGI 

oVT 

— <>Vl 
t**Wv 

o Xv2 

— o Xvi 

« XSG2 

o VT 

o VL 



I 



Fig. 11 



Spectrum Sensitivity Characteristics (Typical example, excluding illuminant characteristics) 

With a Fujinon lens H6 x 12.5D 





















0.8 
0.7 
0.6 
0.5 
0.4 
0.3 
0.2 






















































































































































900 1000 tlOO 1200 



Wave length [nm] 



71 



SONY® 



ICX022AL-3 



O 

O) 



j: 



72- 



SONY® 



ICX022AL-3 



Sensor Read Clock Timing Chart 




Unit: us 



■ 



Charge Drain Clock Timing Chart 



Unit: (as 



73- 



SONY® ICX022AL-3 

Handling Instructions 

1. On electric screening 

To prevent damage to the CCD image sensor by static electricity, handle as follows. 

a) Either handle the device with bare hands, or use antistatic gloves and clothes. Conductive 
shoes are also required. 

b) Use a ground lead when directly touching the device. 

c) Cover the floor and working table with a conductive mat or equivalent to avoid static electricity. 

d) Discharge using ionized air is recommended. 

e) To ship the mounted boards, use cartons with antistatic properties. 

2. On soldering 

a) Make sure the package temperature does not exceed 80°C. 

b) Solder-dipping of DIP in a mounting furnace may break glass. Use a grounded 30 W 
soldering iron a each pin for less than 2 seconds. When adjusting or removing soldered parts, 
let the CCD cool sufficiently. 

c) Do not use any solder-aspirating equipment to remove the imaging device. Should an electric 
solder-aspiration device be used, use only a device of the zero-cross type control system and 
be sure to ground the controller. 

3. On contamination 

a) Keep the operation room clean (Class 1000 Will be expected). 

b) Do not touch the glass surface avoid contact with foreign objects. Blow off any dust the 
surface with a blower. (Ionized air is recommended to blow off any object sticking through 
static electricity.) 

c) Wipe off grass spots with an applicator moistened with ethanol. Be careful not to scratch the 
surface. 

d) To eliminate contamination, store the device in an exclusive case. During transportation 
minimize the difference in temperatures between locations to avoid moisture condensation. 

e) When a protection tape has been affixed for shipment, remove it just before use after applying 
appropriate antistatic measures. Do no reuse the removed tape. 

4. Do not subject the device to light sources for extended periods. If a color element is subjected to 
strong light ray for an extended period, the color filter will be discolored. (Store the device in a 
dark place.) 

5. Usage or storage of the device in high temperature or high humidity may seriously affect the 
performance. 

6. The CCD image sensor is a high-precision optical part, that should not be subjected to mechanical 
shocks. 

7. System data write complete ROM (with flow compensation address included) 
System data write complete ROM in equal quantity as ICX022AL-3 is attached. 
Analog those ROM with address for flow compensation have serial No. stuck on. 
Use in conjunction with ICX022AL-3 pairing the same serial No.. 



74- 



SONY. 



ICX024AL-3 



Interline-type CCD Image Sensor 



Description 

ICX024AL-3 is an interline-type CCD image 
sensor designed for B/W video cameras. 

Effective pixels number 756 horizontally and 581 
vertically. 

Features 

• Image size: 2/3 inches (8.8 mm(H) x 6.6 mm(V)) 

• Effective pixels : 756 (H) x 581 (V) 

• Effective optical black 
Horizontal: Front 5 pixels 

Back 55 pixels 
Vertical: Front 19 pixels 
Back 6 pixels 

• High resolution, high sensitivity and low noise. 

• Low lag and low smear 

• Low dark current 

• Anti-blooming function 

• Electronic shutter function 

• Neither figure distortion nor microphonic noise. 

• y characteristics: 1 



Package Outline 



Unit: mm 



20 pins DIP (Ceramic) 



Effective picture elements center 



^ 



i 



% 



ft 



_26.0_ 
27.0 



\ 2 0X2.5 Slot 



IWYWYYYfef 



I 



Element Structure 

• Interline type CCD image sensor 

• Chip size: 10.0 mm(H)x 8.2 mm(V) 

• Unit cell size: 1 1 .0 nm(H) x 1 1 .0 |xm(V) 

• Dummy bits: horizontal 22-bits, vertical 1 -bit (even fields only) 

• Built-in high-sensitivity output amplifier 



(V) 



Pin 1 1 side 



-(H) 



I 1 



756 



Pin 1 side 



581 



19 



55 



Fig. 1 Optical block configuration 



81019-YA 



75 - 



SONY® 



ICX024AL-3 



Imaging Device Function Block and Pin Configuration 




■&— (5>-@M§)- 

H02 H01 GND 



*Note) — □: Photo sensor 
Pin Description 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V<M 


Vertical register transfer clock 


11 


VOUT 


Signal output 


2 


V<()3 


Vertical register transfer clock 


12 


Vgg 


Output amplifier gate 


3 


V<|>2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (OFD) bias 


14 


GND 


GND 


5 


GND 


GND 


15 


PD 


Pre-charge drain bias 


6 


V<|)1 


Vertical register transfer clock 


16 


PG 


Output reset clock 


7 


Vl 


Protective transistor bias 


17 


Vl 


Protective transistor bias 


8 


NC 




18 


H<|)2 


Horizontal register transfer clock 


9 


NC 




19 


H<(>1 


Horizontal register transfer clock 


10 


Vdd 


Output amplifier drain supply 


20 


GND 


GND 



-76- 



SONY® 






ICX024AL-3 


Absolute Maximum Ratings 


Item 


Ratings 


Unit 


Remarks 


SUB - GND 


-0.3 to +5.5 


V 




Vdd, PD, Vout, Vss - GND 


-0.3 to +20 


V 




Vdd, PD, Vout, Vss - SUB 


-55 to +10 


V 


Note 1 


Horizontal and vertical transfer clock inputs - GND 


-15 to +20 


V 




Horizontal and vertical transfer clock input - SUB 


-65 to +10 


V 


Note 1 


Potential difference between vertical transfer clock inputs 


15 


V 


Note 2 


Potential difference between horizontal transfer clock inputs 


17 


V 




H<|>1 , H<|)2 - V<|>4 


-17 to +17 


V 




PG, Vgg -GND 


-10 to +15 


V 




PG, Vgg - SUB 


-55 to +10 


V 


Note 1 


Vl - SUB 


-65 to +0.3 


V 




Pins other than GND, SUB and Vl - Vl 


-0.3 to +27 


V 




Storage temperature 


-30 to +80 


°C 




Operation guarantee ambient temperature 


-10 to +55 


°C 





Note) 1 . This image sensor consists of an N substrate P-Well structure where a protection transistor 
is connected to each pin accordingly. If a voltage exceeding 10 V is applied to pins other 
than Vl against the SUB pin, a punch through current will flow. Since a series resistance Rl 
is located between each pin and SUB, the device will withstand destruction through any rush 
voltage over 10 V. The series resistance Rl must be more than 1 kQ between Vp-p and 
SUB, more than 500 Q between Vout and SUB and more than 5 kQ between Vss or PD and 
SUB. The series resistance between other pins (except Vl and GND) and SUB must be 
more than 5 Q. 



I 



1 ) Vdd, PD, Vout and Vss pins 



Every pin o 



Vlo 



GNDO 



=7 



SUBO- 



r< 



/v. 



Rl 



2) Pins other than 1 ) (except Vl and GND) 
Every pin O 



HC 



Vl _ 
GNDO ^~ 



SUBO 



Fig. 2 Equivalent circuit 



2. In case of clock width <10 ^s and clock duty factor <0.1%, up to 27 V is guaranteed. 



" -77- 



SONY® 



ICX024AL-3 



Electrical Characteristics 
Bias conditions 



Item 



Supply voltage of output circuit 



Substrate voltage adjustable range 



Regulation range after substrate voltage 
adjustment 



Protection transistor bias 



Symbol 



Vdd 



Vpd 



Vgg 



Vss 



VSUB 



N/SUB 



Vl 



Min. 



14.55 



14.55 



1.6 



Typ. 



15.0 



15.0 



2.0 



Max. 



15.45 



15.45 



2.4 



Unit 



Ground with a 390 Q resistance 



-3 



19 



Remarks 



Note 1 



±5% 



Note 2 



To be the vertical transfer clock low-level clamp bias 



DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output circuit current 


Idd 




5.0 




mA 


Note 3 


Input current 


llNl 






1 


uA 


Note 4 


Iin2 






10 


^A 


Note 5 



Note) 1. Vpd and Vdd must have the same voltage. 

2. Indication of the substrate voltage (Vsub) set value: 

The set value is indicated on the rear of the imaging device by a code. Adjust to obtain the 
indicated voltage at the SUB pin. 
Vsub code - Two digit indication 

□ D 

Integral part Decimal part 



The integral code correspond to the following 


actual values: 








Integral codes 


9 


A 


B 


C 


D 


E 


F 


G 


H 


I 


J 
19 


Numerical value 


9 


10 


11 


12 


13 


14 


15 


16 


17 


18 



EX.) F5 -> 15.5 (V) 

3. Ground Vss with a 390 D. resistance 

4. 1) Current flowing to the ground when a voltage of 20 V is applied to Vdd, PD, Vout, Vss 

and SUB pins. Test ground all the pins other than those under test. 

2) Current flowing to the ground when a voltage of 20 V is applied to V<>1 , V<|>2, V03, V<|>4, 
H<t>1 and H<(>2 pins in the order. Apply pin a voltage of 20 V to the SUB pins and 
ground pins other than those under test. 

3) Current flowing to the ground when a voltage of 15 V is applied to PG and Vgg pins in 
the order. Apply a voltage of 15 V to the SUB pin and ground pins other than those 
under test. 

4) Current flowing to the ground when Vl pin is grounded, GND and SUB pins are open and 
a voltage of 27 V is applied to other pins. 

5. Current flowing to the ground when a voltage of 55 V is applied to the SUB pin. In this 
case ground pins other than those under test. 



78 



SONY® 



ICX024AL-3 



Clock Voltage Conditions 
Clock voltage 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Read clock voltage 


VVT 


13.0 




15.0 


V 


Note 1 


Vertical transfer clock voltage 


VVHH 






1.3 


V 


Note 2 


VVH 


-0.5 




0.7 


V 


V*V 


8.0 






V 


VVLL 


-10.5 






V 


Horizontal transfer clock voltage 


Vhhh 






5.2 


V 


Note 3 


Vhl 


-3.0 




-1.7 


V 


V*H 


5.2 




8.0 


V 


Vhll 


-3.0 






V 


Output reset clock voltage 


Vpgl 









V 


Note 4 


V41PG 


7.0 




13.0 


V 


Substrate clock voltage 


V*SUB 


23.0 




27.0 


V 


Note 5 



Clock capacitance 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Vertical transfer clock - GND 


C*v 




5000 




PF 




Capacitance between vertical transfer 
clocks 


C<t>W 




1500 




PF 




Horizontal transfer clock - GND 


Cd>H 




180 




PF 




Capacitance between horizontal transfer 
clocks 


C»HH 




50 




PF 




Output reset clock - GND 


C*PG 




10 




PF 




Substrate clock - GND 


C*SUB 




500 




PF 





■ 



H<|>1 



C<))HI 



dji c<t»H 
w 



4r 



H<)2 



Fig. 4 Equivalent circuit of horizontal transfer clock capacitance 



79- 



SONY® 



ICX024AL-3 



Note) 1. Read clock voltage 

1) The symbol "<)>l" expresses the voltage level while the read clock "Vt" of the vertical 
transfer clocks ("\A|>1" and "V<|>2") is set. The maximum value in the read clock waveform 
is expressed as "<|>h". 

2) The period in which the voltage level becomes (<|>h - <|>l)/2 is expressed as "tsr". The 
voltage levels at "tst/2" are expressed as "Vn" (at V<|>1) and "Vt 3 " (at V<)>3). The smaller 
of "Vn" and "Vt3" is defined as the read clock voltage "Vvt". 



Vn, VT2 




(<|>h - <J>l)/2 



(|)l = V<|)1, V(|)3, Level 



Fig. 5 Read clock wave length 

Vertical clock voltage (Refer to Fig. 6) 

T = 564 ns (with a horizontal driving frequency of 1 4.19MHz) 

1) Definition of the vertical transfer clock amplitude 



Level 2T after the rising edge of "vV 
Level T after the falling edge of "V<f>i" 
Level 2T after the rising edge of "V<|>4' 
Level T after the falling edge of "VV 
Level 2T after the rising edge of "V<|>r 
Level T after the falling edge of "V<|>3" 
Level 4T after the rising edge of "vV 
Level 3T after the falling edge of "V<|>4 



is expressed as "Vja". 
is expressed as "Vib". 
is expressed as "NAa". 
is expressed as "V2B". 
is expressed as "Via". 
is expressed as "Vsb". 
is expressed as "V2A". 
is expressed as "V4b". 



Vc|)2 Level T after the falling edge of "V<t>r is expressed as "V2c". 

V<)>3 Level T after the falling edge of "V<)>2" is expressed as "Vsc". 

V<)>4 Level T after the falling edge of "V<|)3" is expressed as "V4c". 

V<)>1 Level 3T after the falling edge of "V<|)4" is expressed as "Vic" 



A31 
A42 
A13 
A24 



(V3A 
(V4A 
(VlA 
(V2A 



V2C) / 

V3C) / 

V4C) / 

Vic) / 



ViB 
V2B 
V3B 
V4B 



The minimum value of these is defined as the vertical transfer clock amplitude "V<|)v" 



2) The maximum value from Via, V2A, Vsa, and V>a, is defined as the high level Vvh of the 
clock. 

3) The minimum level in a waveform which includes the vertical clock coupling is expressed 
as "Vvll". 

"Vvhh" expresses the maximum level except in the period where read clock Vt is applied 
(in V<(>1 and V<|)3 only). 



80- 



SONY® 



ICX024AL-3 




Fig. 6 Vertical transfer clock waveform 

T = 564ns (with a horizontal driving frequency of 4 fsc) 



3. Horizontal transfer clock voltage 

1) For the horizontal transfer clocks "H<|>r and "H<|>2", the low-level period is expressed as 
"thl" and the high-level period is expressed as "thh". The symbol "tho" expresses the 
overlap period of "thl" and "thh". 

2) The low level at which "thl", "thh" and "tho" satisfy the following time duration is 
expressed as "Hib" and "H2b". 

And the high level is expressed as "Hia" and "H2a" 

thl > 10 ns, thh > 10 ns, tho > 5 ns 

A 21 = Hia - Hze 
A 12 = H 2 a - Hib 



I 



3) The minimum level in the waveform which contains the coupling of the horizontal transfer 
clocks "H<|)1" and "H<|>2" is expressed as "Vhll" and the minimum level is expressed as 

"Vhhh". 

Vhhh 

H2A "T 




Fig. 7 Horizontal transfer clock waveform 



SONY® 



ICX024AL-3 



4. Output reset clock voltage 

1) The low level of the output reset clock is to be the GND in the circuit. 

2) The amplitude of the output reset PG clock "V<|>pg" is defined as the maximum value of 
the amplitude which provides a high level period over 10 ns. 



More than 1 ns 



High level 



! Low level 




V<|)PG 



VPGL 



Fig. 8 Waveform of PG clock 



Substrate clock voltage 

1) Substrate voltage is expressed as <)>l and the maximum value of the substrate clock 
waveform as <|)h. 

2) The period during which voltage level reaches (<|>h - <|>l)/2 is expressed as tsr. The 
difference of voltage level with <t>L at tsr/2 is defined as substrate clock voltage V<|>sub. 




V<|)SUB 



(<|>H - <|>L)/2 
<t>L = Vsub 



Fig. 9 Substrate clock waveform 

Driving Clock Waveform Conditions 

1) Definition of <)>h (100%) and <K (0%) 

(1) For the horizontal transfer clocks (H<t>i, H<t>2), output reset clock (PG<|>) and vertical transfer 
clocks (V<(>i, V<|>2, V(|)3, NAM, the maximum value in the clock waveform which includes no 
coupling is expressed as "<|>h" and the minimum value is expressed as "<|>l". 

(2) For the read clock (Vt), the maximum value in the clock waveform is expressed as "<t»H"."<|>L" 
expresses the voltage level while the read clock (Vt) of the vertical transfer clocks (v>, NAjw) 
applied. 

(3) For the substrate clock (SUB(t>), the maximum value in the clock waveform is expressed as "<t 
and the substrate voltage (Vsub) as "<|>l". 

2) Standard driving clock conditions (Typ.) 



-82 



SONY® 



ICX024AL-3 



Horizontal drive frequency: 1 4.19MHz 



Clock 
(Symbol) 


twh 


twi 


tr 


tf 


Unit 


Remarks 


H<j)i 


18 


33.7 


10 


8 


ns 


Imaging period 


H<(>2 


18 


33.7 


10 


8 


H<t>i 


4.9 




0.10 


0.01 


US 


Parallel-serial converting period 


H(|>2 




4.9 


0.10 


0.01 


(|)PG 


12 


53.7 


2 


2 


ns 




v<t>.7V(i)2 


61.6 


1.6 


0.1 


0.1 


US 


Imaging period 


V<t>3/V())4 


2.8 


60.45 


0.05 


0.1 


V<t>T 


2.4 




0.2 


0.1 


Reading period 


SUB<t> 


1.0 




0.08 


0.1 


RS 


Electron sweep-off period 



<|)L(0%) 



tr ■ 




twh 








7 




\ : 




90%-- 


V -N 


twi 


10%-J 


\ 










\ 



4>H<100%) 



I 



Fig. 10 Clock waveform 



Imaging Characteristics 



(For the testing circuit, see Fig. 11.) 
Ta=25°C 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Testing method 


Remarks 


Sensitivity 


sg 


130 


180 




mV 


1 




Output saturation signal 


Vsat 


500 






mV 


2 


Note 


Blooming margin 




800 






times 


3 


Note 


Smear 


Smr 




0.007 


0.015 


% 


4 




Video signal shading 


Svg 






25 


% 


5 




Dark signal output 


Vdt 






2 


mV 


6 


Ta=55°C 


Dark signal shading 


AVdt 






1 


mV 


7 


Ta=55°C 



Note) Saturation signal and blooming margin are guaranteed only when the substrate voltage has been 
set to the voltage indicated on the back of the imaging device. 



-83- 



SONY® ICX024AL-3 

Test Methods 
Conditions 

1) The conditions required to drive the device through the following tests are converted by the 
bias conditions and the clock voltage conditions. The test circuit shown in Fig. 11 is used for 
evaluating and testing the characteristics. 

2) Blemish are excluded from the following tests and the signal output is based on the optical 
back level unless otherwise specified. The value obtained at the output test point becomes the 
test value. 

Standard imaging conditions 

1) Shoot the PTB-100 pattern box (luminance 706 Nit, color temperature 3200°K) with no pattern, 
using a FUJINON H6 x 1 2.5D (F1 .4) lens at F5.6. Use the CM-500S (1 .0 mmt) filter to cut 
off infrared rays. 

2) Shoot a light source (color temperature 3200°K) which provides a uniform brightness within 2% 
over the whole screen. 

For infrared cut-off filter, use the CM-500S (1.0 mmt) 

1. Set the standard imaging condition 1) and test signal voltages the center of the screen. 

2. Set to standard imaging condition 2) and adjust the light intensity to about eight times the intensity 
obtained at a signal voltage of 200 mV. Them obtain the minimum value of the signal voltage 
over the whole screen. * 

3. Set to imaging condition 2) and adjust the light intensity to about 800 times the intensity obtained 
at a signal voltage of 200 mV. At that time make sure there is no blooming and the vertical 
resistor is not saturated. 

4. Set to standard imaging condition 2) and adjust the light intensity so that the signal voltage (Vsg) 
becomes 200 mV. Then, turn Vt off and obtain the maximum value of the signal voltage "Vsm" 
after stopping the horizontal resistor 50 H at the effective picture element. 

Smr = VsM x — x — x 100 (%) 
Vsg 50 10 

(Converted into 1/10 V system) 

5. Set to standard imaging condition 2) and test the signal voltage to obtain maximum (Vg max) and 
minimum (Vg min) values. 

The light intensity is adjusted so that the average value of the signal voltage (Vg average) 
becomes about 200 mV. 

VsGmax - VsGmin ... .... 

Svg = x 100 (%) 

Vsg average 

6. Measure the mean voltage of the dark current signal based on the horizontal free-transfer level in 
a light-shaded condition with an ambient temperature of 55°C. 

7. Following measurement 6, test the dark current signal voltage to obtain the maximum (Vdmax) and 
minimum (Vdmin) values. Spot defects are ignored in this test. 



-84 



SONY® 



ICX024AL-3 



Electrical Characteristics Test Circuit 




X 



XsuaA <►■ 



Vsus ' 



SUB 
driver 



mix 

Hi*- 



(t iX K X!3X!*X!5X!5Xi!X!2X t9 * 

ICX024AL-3 
(»X9 XflYTYiYsYiYTYz Y 1 j 



"1 



3Ef2k 



3E?ik 



->lf- 



-)r^ 



Vpgh 



PG 
driver 



H 
driver 



-o VPGL 

-o Vhh 

(=Vhl-i-V+h) 

-o XH2 

-o XH1 



>Vhl 



V 
driver 



-M^v 4 v 

o XV4 
o XV3 
o XSG1 



-o VL 



-H-ov*v 



10m 



V 

driver 



>XV2 

= Xv< 

= XSG2 
>VT 



Fig. 11 



Spectrum Sensitivity Characteristics (Typical example, excluding illuminant characteristics) 

With a Fujinon lens H6 x 12.5D 



0.9 
0.8 
0.7 
0.6 
0.5 
0.4 
0.3 
0.2 
0.1 



































































































































































Wave length [nm] 



-85 - 



SONY® 



ICX024AL-3 



O 



XT 



S 5 






£ > > 5 5 



OQ o 
-I > X 



86- 



SONY® 



ICX024AL-3 



Sensor Read Clock Timing Chart 




I 



< EVEN FIELD) 



Unit: us 



Charge Drain Clock Timing Chart 



Unit: ^s 



-87- 



SONY® ICX024AL-3 

Handling Instructions 

1. On electric screening 

To prevent damage to the CCD image sensor by static electricity, handle as follows. 

a) Either handle the device with bare hands, or use antistatic gloves and clothes. Conductive 
shoes are also required. 

b) Use a ground lead when directly touching the device. 

c) Cover the floor and working table with a conductive mat or equivalent to avoid static electricity. 

d) Discharge using ionized air is recommended. 

e) To ship the mounted boards, use cartons with antistatic properties. 

2. On soldering 

a) Make sure the package temperature does not exceed 80°C. 

b) Solder-dipping of DIP in a mounting furnace may break glass. Use a grounded 30 W 
soldering iron a each pin for less than 2 seconds. When adjusting or removing soldered parts, 
let the CCD cool sufficiently. 

c) Do not use any solder-aspirating equipment to remove the imaging device. Should an electric 
solder-aspiration device be used, use only a device of the zero-cross type control system and 
be sure to ground the controller. 

3. On contamination 

a) Keep the operation room clean (Class 1000 Will be expected). 

b) Do not touch the glass surface avoid contact with foreign objects. Blow off any dust the 
surface with a blower. (Ionized air is recommended to blow off any object sticking through 
static electricity.) 

c) Wipe off grass spots with an applicator moistened with ethanol. Be careful not to scratch the 
surface. 

d) To eliminate contamination, store the device in an exclusive case. During transportation 
minimize the difference in temperatures between locations to avoid moisture condensation. 

e) When a protection tape has been affixed for shipment, remove it just before use after applying 
appropriate antistatic measures. Do no reuse the removed tape. 

4. Do not subject the device to light sources for extended periods. If a color element is subjected to 
strong light ray for an extended period, the color filter will be discolored. (Store the device in a 
dark place.) 

5. Usage or storage of the device in high temperature or high humidity may seriously affect the 
performance. 

6. The CCD image sensor is a high-precision optical part, that should not be subjected to mechanical 
shocks. 

7. System data write complete ROM (with flow compensation address included) 
System data write complete ROM in equal quantity as ICX024AL-3 is attached. 
Analog those ROM with address for flow compensation have serial No. stuck on. 
Use in conjunction with ICX024AL-3 pairing the same serial No.. 



SONY* 



ICX026BL 



Solid-State Image Sensor for B/W Camera 



Description 

The ICX026BL is an interline transfer CCD solid- 
state imager suitable for EIA 1/2 inch B/W video 
cameras. High sensitiveness is achieved through the 
adoption of HAD (Hole Accumulation Diode) sensors. 

This chip features a field integration read out 
system and an electronic shutter with variable 
charge-storage time. 

Features 

• High sensitivity (+6 dB compare with ICX026AL) 

• Optical size 1/2 inch format 

• Field integration read out system 

• Low dark current 

• Horizontal register 5V drive 

• High antiblooming 

• Low smear 

• Variable speed electronic shutter 

Device Structure 

• Number of effective pixels 51 (H) x 492 (V) 

• Number of total pixels 537 (H) x 505 (V) 

• Interline transfer CCD image sensor 

• Chip size 7.84 mm (H) x 6.40 mm (V) 

• Unit cell size 1 2.7 urn (H) x 9.8 |im (V) 

• Optical black 

Horizontal (H) direction 
Vertical (V) direction 

• Number of dummy bits 

Horizontal 16 

Vertical 1 (even field only) 

• Substrate material silicon 

Block Diagram 



Package Outline 



Unit: mm 



20 pins DIP (Ceramic) 




, , Effective picture elements center 




Front 2 pixels Rear 25 pixels 
Front 12 pixels Rear 1 pixels 




(pin 11] 
Optical black position 




Note) -□ : Photo sensor 



H01 H02 GNO 



E89922-YA 



-89 



SONY® 



ICX026BL 



Pin Configuration (Top View) 



(29 GND 

©H02 

©H01 

©PG 

®VL 

©PD 

©6ND 

©Vss 

©VGG 

©VOUT 



Pin Description 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V04 


Vertical register transfer clock 


11 


Vout 


Signal output 


2 


V<|>3 


Vertical register transfer clock 


12 


Vgg 


Output amplifier gate bias 


3 


V(t>2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (Overflow drain) 


14 


GND 


GND 


5 


GND 


GND 


15 


PD 


Precharge drain bias 


6 


V<|>1 


Vertical register transfer clock 


16 


Vl 


Protective transistor bias 


7 


Vl 


Protective transistor bias 


17 


PG 


Precharge gate clock 


8 


GND 


GND 


18 


H<>1 


Horizontal register transfer clock 


9 


VDD1 


Output amplifier drain supply 


19 


H<|>2 


Horizontal register transfer clock 


10 


VDD2 


Output amplifier drain supply 


20 


GND 


GND 



Absolute Maximum Ratings 

• Substrate voltage SUB - GND 

• Supply voltage 



Clock input voltage 



Vddi, Vdd2, PD, Vout, Vss - GND 
Vddi, Vdd2, PD, Vout, Vss - SUB 
V<|>1, V<|)2, V<f)3, V<K H<t>l, H<(>2 - GND 
V<(>1, V02, V<f)3, V<|>4, H<>1 , H<S>2 - SUB 

• Voltage difference between vertical clock input pins 

• Voltage difference between horizontal clock input pins 

• H<J>1 , H<|)2 - V<M 

• PG, Vgg - GND 

• PG, Vgg - SUB 

• Vl - SUB 

• Beside GND, SUB, Vl - Vl 

• Storage temperature 

• Operating temperature 

*Note) +27 V (Max.) when clock width < 10 us, duty factor < 0.1% 



-0.3 to +55 V 
-0.3 to +18 V 
-55 to +10 V 

to +20 V 

to +10 V 

15 V* (Max.) 

17 V (Max.) 

to +17 V 
-10 to +15 V 
-55 to +10 V 
-65 to +0.3 V 
-0.3 to +30 V 
-30 to +80°C 
-10 to +55°C 



-15 
-65 



-17 



-90- 



SONY® 



ICX026BL 



Bias Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain voltage 


Vddi, Vdd2 


14.55 


15.0 


15.45 


V 


Vddi = VDD2 


Precharge drain voltage 


Vpd 


14.55 


15.0 


15.45 


V 


Vpd = Vddi = Vdd2 


Output amplifier gate voltage 


Vgg 


1.75 


2.0 


2.25 


V 




Output amplifier source 


Vss 


Ground through 680 £2 resistor 


±5% 


Substrate voltage adjustment 
range 


VSUB 


7 




19 


V 


*1 


Fluctuation range after 
substrate voltage adjustment 


VSUB 


-3 




+3 


% 




Protective transistor bias 


Vl 


*2 





DC Characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain current 


Idd 




2.5 




mA 


Idd = Iddi + Idd2 


Input current 


Iini 






1 


^A 


*3 


Input current 


llN2 






10 


HA 


*4 



Note) *1. Substrate voltage (Vsub) setting value display. 

Substrate voltage setting value is displayed at the back of the device through a code 
address. Adjust so as to obtain the displayed voltage at SUB pin. 



I 



Vsub code address - two digits display 



□ □ 

I I 

Integral part Decimal part 



The relation between code address of integral part and actual numerical values. 



Code address of 
integral part 


7 


8 


9 


A 


B 


C 


D 


E 


F 


G 


H 


I 


J 


Numerical Value 


7 


8 


9 


10 


11 


12 


13 


14 


15 


16 


17 


18 


19 



<Example> F5 -» 15.5 (V) 
*2. Vl setting is Vvl of the vertical transfer clock waveform. 

*3. 1) Current to earth when 18V is applied to pins Vddi, Vdd2, Vout, Vss and SUB pin. 
However, pins that are not tested are grounded. 

2) Current to earth when 20V is sequentially applied to pins V<|>1, V<t>2, V<))3, Vc|>4, H<t>i and 
H<|)2. However, 20V is applied to SUB while pins that are not tested are grounded. 

3) Current to earth when 15V is sequentially applied to pins PG and Vgg. However, 15V 
is applied to SUB while pins that are not tested are grounded. 

*4. 1) Current to earth when 55V is applied to SUB pin. Pins that are not tested are 
grounded. 
2) Current to earth when Vl is grounded, GND and SUB are open and 30V is applied to 
other pins. 



-91 



SONY« 














ICX026BL 


Clock Voltage Conditions 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


No. 


Remarks 




Read out clock voltage 


Vvt 


14.3 


15.0 


15.7 


V 


2,6 


*1 


Vertical transfer clock voltage *2 


Vvm ,VVH2,VVH3,VVH4 


-0.2 





0.2 


V 


1,2,3,6 


Vvh=(Vvhi+Vvh2)/2 




VVL1 ,VVL2,VVL3,VVL4 


-9.6 


-9.0 


-8.3 


V 


1 ,2,3,6 


VVL=(VvL3+VvL4)/2 




V<|>V 


8.1 


9.0 


9.8 


V 


1,2,3,6 


V<|>v=VvHn-\/vLn (n=1 


to 4) 




| VVH1 - VVH2 | 






0.2 


V 


3,6 






VVH3 - VVH 


-0.4 




0.1 


V 


2,3,6 






VVH4 - VVH 


-0.4 




0.1 


V 


1,3,6 






VVHH 






0.8 


V 


1,2,3,6 


High level coupling 




VVHL 






1.0 


V 


1,2,3,6 


High level coupling 




VVLH 






0.8 


V 


1,2,3,6 


Low level coupling 




VVLL 






0.8 


V 


1,2,3,6 


Low level coupling 


Horizontal transfer clock voltage 


V<|)H 


4.7 


5.0 


5.3 


V 


18,19 


*3 




Vhl 


-0.05 





0.05 


V 


18,19 




Precharge gate clock voltage 


V0PG 


8.0 




11.5 


V 


17 


*4 




Vpgl 


-0.1 





0.1 


V 


17 




Substrate clock voltage 


V(|)SUB 


23.0 


32.0 


34.0 


V 


4 


*5 



Note) *1. See Fig. 1. 

*2. See Fig. 2. 

*3. See Fig. 3. 

*4. See Fig. 3. 

*5. See Fig. 4. 

Clock Equivalent Circuit Constant 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Capacitance between vertical transfer clock and GND 


C<|>vi, C0V3 




1000 




PF 




Capacitance between vertical transfer clock and GND 


C<|>V2, C<(>V4 




1200 




pF 




Capacitance between vertical transfer clocks 


C<|)V12, C<|>V34 




1200 




PF 




Capacitance between vertical transfer clocks 


C<|>V23, C<|>V41 




750 




pF 




Capacitance between horizontal transfer clock and GND 


C<t>m, C<|>H2 




70 




pF 




Capacitance between horizontal transfer clocks 


C<(>HH 




50 




pF 




Capacitance between precharge gate clock and GND 


C<|>PG 




8 




PF 




Capacitance between substrate clock and GND 


C<|>SUB 




400 




pF 




Vertical transfer clock serial resistor 


Ri,R2,R3,R4 




33 




ft 




Vertical transfer clock ground resistor 


Rgnd 




15 




ft 




Horizontal transfer clock serial resistor 


R<|>h 




10 




ft 





V*M 



Ov« T- 



V«*2 




W>4 V*3 

Vertical transfer clock equivalent circuit 



n o — *\AAi — t 



Om ^ 



— IH 

Ohh 



R*»h 
-AM o h*2 



-r C*H2 



Horizontal trasfer clock equivalent circuit 



92- 



SONY® 



ICX026BL 



Drive Clock Waveform Conditions 

1. Read out clock waveform 

100 V. 

90% 




ov 



Fig.1 



2. Vertical transfer clock waveform 




V<|>2 



VVHH WHH _ 

T — TV T VVH 

i_ \^Z-~ I v»kl T /\f 




7 



V<J>3 




I 



V<|)4 



VVHH VVHH 




Fig.2 



93 



SONY® 



ICX026BL 



3. Horizontal transfer clock waveform/Precharge gate clock waveform 



Vhl.Vpgl- 




Fig. 3 



Item 


Symbol 


twh 


twl 


tr 


tf 


Unit 


Remarks 


Min. 


Typ. 


Max 


Min. 


Typ. 


Max 


Min. 


Typ. 


Max 


Min. 


Typ- 


Max 


Read out clock 


Vt 


1.5 


1.85 














0.5 






0.5 


MS 


During read out 


Vertical transfer clock 


V$1,V<t>2,V<t>3,V<|>4 


















0.45 


0.015 




0.25 


US 


* 


Horizontal transfer clock 


H0 


37 


41 




38 


42 






12 


15 




10 


15 


ns 


During imaging 


Horizontal transfer clock 


H<t>i 




5.6 












0.012 






0.01 




MS 


During parallel serial 
conversion 


Horizontal transfer clock 


H((>2 










5.6 






0.012 






0.01 




US 


During parallel serial 
conversion 


Precharge gate clock 


<|)PG 


15 


17 




75 


81 






4 






3 




ns 




Substrate clock 


<|>SUB 


1.5 


2.1 














0.5 






0.5 


MS 


During charge drain. 



*Note) When vertical transfer clock driver CXD1250 is in use. 
4. Substrate clock waveform 



VSUB 




Fig. 4 



94 



SONY® ICX026BL 


Operating Characteristics Ta = 25°C 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test 
method 


Remarks 


Sensitivity 


S 


240 


320 




mV 


1 




Saturation signal 


Vsat 


500 






mV 


2 


Ta=55°C 


Smear 


SM 




0.007 


0.015 


% 


3 




Blooming margin 




1000 






times 


4 




Video signal shading 


SH 






20 


% 


5 


Zone 0, 1 






25 


% 


5 


Zone to II' 


Dark signal 


Vdt 






2 


mV 


6 


Ta=55°C 


Dark signal shading 


AVdt 






1 


mV 


7 


Ta=55°C 


Flicker 


F 






2 


% 


8 




Lag 


AVIag 






0.5 


% 


9 





Test Method 
Test conditions 

© Through the following tests the substrate voltage should set to the value displayed on the device, 
while the device drive conditions should be kept within the range of the bias and clock voltage 
conditions. 

© Through the following tests defects are excluded and, unless otherwise specified, the optical black 
level (Hence forth referred to as OPB) is set as the reference. The values obtained at A point 
in the figure of the Drive Circuit are utilized. 



I 



Definition of standard imaging conditions 

© Standard imaging condition I: (As imaging device) Use a pattern box (luminance 706 Nit, 3200K 
Halogen source), at F8 with a typical test lens, and CM-500S (1.0 mmt) for IR cut filter. 

© Standard imaging condition II: Use a light source with uniformity within 2%, color temperature of 
3200K and CM-500S (1.0 mmt) as IR cut filter. The light intensity is adjusted in accordance with 
the average signals (Va) indicated in each item. 

1. Set to standard imaging condition I and measure signal output (S) at the center of the screen. 

2. Set to standard imaging condition II. Adjust light intensity to 10 times when the average signal 
VA=150mV. Then test signal Min. Value. 

3. Set to standard imaging condition II. Adjust light intensity to 500 times when the average signal 
VA=150mV. Stop Read out clock. When the charge drain executed by the electronic shutter at 
the respective H blankings takes place, test the Max. value Vsm of signal output. 

SM = (Vsm/Va) x 7500 x 1 /10 x 100 (%) (7ioV) 

4. Set to standard imaging condition II. Adjust light intensity to 1000 times when the average signal 
VA=150mV. Then check that there is no blooming. 



-95 



SONY® 



ICX026BL 



5. Video signal shading SH 

Set to standard imaging condition II. Test signal Max. (Vmax) and Min. (Vmin) values. Adjust 
light intensity to obtain an average signal (Va) of about 150mV. 

SH = (Vmax - Vmin)/VA x 100 (%) 

6. Test the average signal when the device ambient temperature is at 55°C and light is obstructed 
with horizontal idle transfer level as reference. 

7. Following test 6, test Max. (Vd max) and Min. (Vd min) of signal output. Only keep spot defects 
out of this range. 

AVdt = Vd max - Vd min 

8. Set to imaging condition II. Test the output signal difference (AVf) between even and odd field. 
At that time, adjust light intensity to obtain an average signal (Va) of about 150 mV. 

F = (AVf/VA) x 100 (%) 

9. Light a stroboscopic tube with the following timing and test the residual image. 
AVIag = (Vlag/Vs) x 100 (%) 



FLD 



SG 



,-1 



Jl IL 



SG2 



Strobe light timing 



Output 



Vs 200mV V lag (Residual image) 

n * n ^ n n 



_^"L 



t 



96- 



SONY® 



ICX026BL 



O 




97 



SONY® 



ICX026BL 



Spectral Sensitivity Characteristics 

(Excluding light source characteristics, including lens characteristics) 



1.0 I i i i i 




Using read out clock timing chart 



Wave length [nm] 



Odd Field < 



Even Field < 



HD 



V1 
V2 



V3 
V4 



V1 
V2 



V3 
V4 



Unites 



-98- 



SONY® 



ICX026BL 



082 



^ n; 



(Ti a> 



> 
r 

a 

£ 

o 



s 

2 
' I 
'fiZfi 





*: 




.^ 


<VJ 










Ql- 


a 


_i 


Q 


O 


o 


*— 


(VJ 


to 


<J- 


U Z3 


> 


CD 


I 


tf> 


en 


> 


> 


> 


> 


OO 



-99- 



SONY® 



ICX026BL 



- N Kl 



- 100 



SONY® ICX026BL 

Handling Instructions 

1 ) Static charge prevention 

CCD image sensor are easily damaged by static discharge. Before handling be sure to take the 
following protective measures. 

a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use 
conductive shoes. 

b) When handling directly use an earth band. 

c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. 

d) Ionized air is recommended for discharge when handling CCD image sensor. 

e) For the shipment of mounted substrates use boxes treated for the prevention of static charges. 

2) Soldering 

a) Make sure the' package temperature does not exceed 80°C. 

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 
grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and 
remount cool sufficiently. 

c) To dismount an imaging device do not use a solder pult. When using an electric desoldering 
tool use a thermal controller of the zero cross On/Off type and connect to ground. 

3) Dust and dirt protection 

a) Operate in clean environments (around class 1000 will be appropriate). 

b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. 
Should dirt stick to a glass surface blow it off with an air blow. (For dirt stuck through static 
electricity ionized air is recommended) 

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not 
to scratch the glass. 

d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool 
when moving to a room with great temperature differences. 

e) When a protective tape is applied before shipping, just before use remove the tape applied for 
electrostatic protection. Do not reuse the tape. 

4) Do not expose to strong light (sun rays) for long periods. 

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage 
or usage in such conditions. 

6) CCD image sensor are precise optical equipment that should not be subject to mechanical shocks. 



- 101 - 



SONY* 



ICX027BL 



Solid-State Image Sensor for B/W Camera 



Description 

The ICX027BL is an interline transfer CCD solid- 
state imager suitable for CCIR 1/2 inch B/W video 
cameras. High sensitiveness is achieved through the 
adoption of HAD (Hole Ace. nutation Diode) sensors. 

This chip features a field integration read out 
system and an electronic shutter with variable 
charge-storage time. 

Features 

• High sensitivity (+6 dB compare with ICX027AL) 

• Optical size 1/2 inch format 

• Field integration read out system 

• Low dark current 

• Horizontal register 5V drive 

• High antiblooming 

• Low smear 

• Variable speed electronic shutter 

Device Structure 

• Number of effective pixels 500 (H) x 582 (V) 

• Number of total pixels 537 (H) x 597 (V) 

• Interline transfer CCD image sensor 

• Chip size 7.84 mm (H) x 6.40 mm (V) 

• Unit cell size 1 2.7 urn (H) x 8.3 urn (V) 

• Optical black 

Horizontal (H) direction 
Vertical (V) direction 

• Number of dummy bits 

Horizontal 16 

Vertical 1 (even field only) 

• Substrate material silicon 



Package Outline 



Unit: mm 



20pin DIP (Ceramic) 



18.0"> = 



Front 7 pixels Rear 30 pixels 
Front 14 pixels Rear 1 pixels 





(pin 11) 7 H 30 
Optical black position (Top View) 



Block Diagram 





Note)— Q : Photo sensor 



H01 H02 GNO 



E89923-YA 



102- 



SONY® 



ICX027BL 



Pin Configuration (Top View) 



V04 


V) 


V03 


2 


V02 


® 


SUB 


4 


GNO 


(f 


V01 


® 


Vl 


7 


GNO 


© 


Vdoi 


® 


VDD2(io) 



(20)GND 

©H02 

©H01 

©PG 

©VL 

©PD 

©GND 

©Vss 

©VGG 

©VOUT 



Pin Description 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V<|)4 


Vertical register transfer clock 


11 


Vout 


Signal output 


2 


V<)>3 


Vertical register transfer clock 


12 


Vgg 


Output amplifier gate bias 


3 


V<|>2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (Overflow drain) 


14 


GND 


GND 


5 


GND 


GND 


15 


PD 


Precharge drain bias 


6 


V4>i 


Vertical register transfer clock 


16 


Vl 


Protective transistor bias 


7 


Vl 


Protective transistor bias 


17 


PG 


Precharge gate clock 


8 


GND 


GND 


18 


H<t>i 


Horizontal register transfer dock 


9 


Vddi 


Output amplifier drain supply 


19 


H<t»2 


Horizontal register transfer clock 


10 


VDD2 


Output amplifier drain supply 


20 


GND 


GND 



I 



Absolute Maximum Ratings 

• Substrate voltage SUB - GND 

• Supply voltage 



• Clock input voltage 



Vddi, Vdd2, PD, Vout, Vss - GND 
Vddi, Vdd2, PD, Vout, Vss - SUB 
V01, V<|>2, V<>3, V<|>4, H<|>1, H<|>2 - GND 
V<t>i, V<|>2, V<)>3, V<|>4, H<t>i, H<|>2 - SUB 

• Voltage difference between vertical clock input pins 

• Voltage difference between horizontal clock input pins 

• H<|>1, H<)>2 - V<)>4 

• PG, Vgg - GND 

• PG, Vgg - SUB 

• Vl - SUB 

• Beside GND, SUB, Vl - Vl 

• Storage temperature 

• Operating temperature 

*Note) +27 V (Max.) when clock width < 10 us, duty factor < 0.1% 



-0.3 to +55 

-0.3 to +18 

-55 to +10 

-15 to +20 



V 
V 
V 
V 
-65 to +10 V 



15 
17 



V* (Max.) 
V (Max.) 



-17 to +17 V 
-10 to +15 V 



-55 
-65 



to +10 V 
to +0.3 V 



-0.3 to +30 V 
-30 to +80°C 
-10 to +55°C 



103 



SONY® 



ICX027BL 



Bias Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain voltage 


Vddi, Vdd2 


14.55 


15.0 


15.45 


V 


Vddi = VDD2 


Precharge drain voltage 


Vpd 


14.55 


15.0 


15.45 


V 


Vpd = Vddi = Vdd2 


Output amplifier gate voltage 


Vgg 


1.75 


2.0 


2.25 


V 




Output amplifier source 


Vss 


Ground through 680 Q. resistor 


±5% 


Substrate voltage adjustment 
range 


VSUB 


7 




19 


V 


*1 


Fluctuation range after 
substrate voltage adjustment 


VSUB 


-3 




+3 


% 




Protective transistor bias 


Vl 


*2 





DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain current 


Idd 




2.5 




mA 


Idd = Iddi + Idd2 


Input current 


llN1 






1 


^A 


*3 


Input current 


llN2 






10 


uA 


*4 



Note) *1 . Substrate voltage (Vsub) setting value display. 

Substrate voltage setting value is displayed at the back of the device through a code 
address. Adjust so as to obtain the displayed voltage at SUB pin. 



Vsub code address - two digits display 



□ □ 

f ! 

Integral part Decimal part 
The relation between code address of integral part and actual numerical values. 



Code address of 
integral part 


7 


8 


9 


A 


B 


C 


D 


E 


F 


G 


H 


I 


J 


Numerical Value 


7 


8 


9 


10 


11 


12 


13 


14 


15 


16 


17 


18 


19 



<Example> F5 -> 15.5 (V) 
*2. Vl setting is Vvl of the vertical transfer clock waveform. 

*3. 1) Current to earth when 18V is applied to pins Vddi, Vdd2, Vout, Vss and SUB pin. 
However, pins that are not tested are grounded. 

2) Current to earth when 20V is sequentially applied to pins V<|>1, V<|)2, V<|)3, V<|)4, H<>1 and 
H<|>2. However, 20V is applied to SUB while pins that are not tested are grounded. 

3) Current to earth when 15V is sequentially applied to pins PG and Vgg. However, 15V 
is applied to SUB while pins that are not tested are grounded. 

*4. 1) Current to earth when 55V is applied to SUB pin. Pins that are not tested are 
grounded. 
2) Current to earth when Vl is grounded, GND and SUB are open and 30V is applied to 
other pins. 



- 104 



SONY® 



ICX027BL 



Clock Voltage Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


No. 


Remarks 


Read out clock voltage 


Vvt 


14.3 


15.0 


15.7 


V 


2,6 


*1 


Vertical transfer clock voltage *2 


Vvm , VVH2, VVH3,VVH4 


-0.2 





0.2 


V 


1,2,3,6 


VVH=(VvH1+VVH2)/2 




VVL1 , VVL2,VVL3,VVL4 


-9.6 


-9.0 


-8.3 


V 


1,2,3,6 


VvL=(VVL3+VVL4)/2 




V0V 


8.1 


9.0 


9.8 


V 


1,2,3,6 


V(|>v=VvHn-VvLn (n=1 to 4) 




I Vvm - Vvh2| 






0.2 


V 


3,6 






VVH3 - VVH 


-0.4 




0.1 


V 


2,3,6 






VVH4 - VVH 


-0.4 




0.1 


V 


1,3,6 






VVHH 






0.8 


V 


1,2,3,6 


High level coupling 




VVHL 






1.0 


V 


1,2,3,6 


High level coupling 




VVLH 






0.8 


V 


1,2,3,6 


Low level coupling 




VVLL 






0.8 


V 


1,2,3,6 


Low level coupling 


Horizontal transfer clock voltage 


V<(>H 


4.7 


5.0 


5.3 


V 


18,19 


*3 




Vhl 


-0.05 





0.05 


V 


18,19 




Precharge gate clock voltage 


V())PG 


8.0 




11.5 


V 


17 


*4 




Vpgl 


-0.1 





0.1 


V 


17 




Substrate clock voltage 


V(|>SUB 


23.0 


32.0 


34.0 


V 


4 


*5 



Note) *1. See Fig. 1. 

*2. See Fig. 2. 

*3. See Fig. 3. 

*4. See Fig. 3. 

*5. See Fig. 4. 

Clock Equivalent Circuit Constant 



■ 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Capacitance between vertical transfer clock and GND 


C<|>vi, C0v3 




1000 




pF 




Capacitance between vertical transfer clock and GND 


C0V2, C<)>V4 




1200 




PF 




Capacitance between vertical transfer clocks 


C0V12, C0V34 




1400 




pF 




Capacitance between vertical transfer clocks 


C<|>V23, C<|>V41 




900 




pF 




Capacitance between horizontal transfer clock and GND 


C<|>H1, C<|)H2 




70 




pF 




Capacitance between horizontal transfer clocks 


C(|>HH 




50 




pF 




Capacitance between precharge gate clock and GND 


C<t>PG 




8 




pF 




Capacitance between substrate clock and GND 


C<|>SUB 




400 




pF 




Vertical transfer clock serial resistor 


Ri,R2,R3,R4 




33 




a 




Vertical transfer clock ground resistor 


Rgnd 




15 




Q 




Horizontal transfer clock serial resistor 


R<t>H 




10 




a 





V<*2 




W-4 



V*3 



R*H 

H*M o — W/ — f 



Cs6Hi -r 



-HI- 

Ohh 



R*»H 

t— W/ o H*2 



=r C*H2 



Vertical transfer clock equivalent circuit 



Horizontal trasfer clock equivalent circuit 



- 105 



SONY® 



ICX027BL 



Drive Clock Waveform Conditions 

1 . Read out clock waveform 




Fig.1 



ov 



2. Vertical transfer clock waveform 




A WLL 

WL 



V<|>3 




V<|>2 



V<|>4 



VVHH VVHH 



MN :: - T -^ 



VVH2 WML 





Fig.2 



- 106 



SONY® 



ICX027BL 



3. Horizontal transfer clock waveform/Precharge gate clock waveform 



10 o /« 



Vhl.Vpgl- 









tWh 




«•" tf 




















i 


\ 










\ 












V*h,V*pg\ 


twl 












< 











Fig. 3 



Item 


Symbol 


twh 


twl 


tr 


tf 


Unit 


Remarks 


Min. 


Typ. 


Max 


Min. 


Typ. 


Max 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max 


Read out clock 


Vt 


1.5 


1.85 














0.5 






0.5 


us 


During read out 


Vertical transfer clock 


V(|>1,V<|>2,V<t>3,V<|>4 


















0.45 


0.015 




0.25 


us 


* 


Horizontal transfer clock 


H$ 


38 


42 




38 


42 






12 


15 




10 


15 


ns 


During imaging 


Horizontal transfer clock 


H01 




5.6 












0.012 






0.01 




us 


During parallel serial 
conversion 


Horizontal transfer clock 


H02 










5.6 






0.012 






0.01 




us 


During parallel serial 
conversion 


Precharge gate clock 


0PG 


15 


17 




76 


82 






4 






3 




ns 




Substrate clock 


<|>SUB 


1.5 


2.1 














0.5 






0.5 


us 


During charge drain 



■ 



♦Note) When vertical transfer clock driver CXD1250 is in use. 
4. Substrate clock waveform 



lOOVo -p. 


f^"^ 





i 


. 


9ov. -/r^ 






















0M 








I 


, 


1 i Vtfs 


JB 




0M 
2 






lOVo 1 — ■ 


' 


"" lV 


-w' 


'' 


1 


Vsob— OV. 1 , fwh ^ 


^•i 




■ i 




" H 





Fig. 4 



107- 



SONY® ICX027BL 


Operating Characteristics Ta = 25°C 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test 
method 


Remarks 


Sensitivity 


S 


220 


300 




mV 


1 




Saturation signal 


Vsat 


450 






mV 


2 


Ta=55°C 


Smear 


SM 




0.007 


0.015 


% 


3 




Blooming margin 




1000 






times 


4 




Video signal shading 


SH 






20 


% 


5 


Zone 0, I 






25 


% 


5 


Zone to II' 


Dark signal 


Vdt 






2 


mV 


6 


Ta=55°C 


Dark signal shading 


AVdt 






1 


mV 


7 


Ta=55°C 


Flicker 


F 






2 


% 


8 




Lag 


AVIag 






0.5 


% 


9 





Test Method 
Test conditions 

©Through the following tests the substrate voltage should set to the value displayed on the device, 
while the device drive conditions should be kept within the range of the bias and clock voltage 
conditions. 

©Through the following tests defects are excluded and, unless otherwise specified, the optical black 
level (Hence forth referred to as OPB) is set as the reference. The values obtained at A point in 
the figure of the Drive Circuit are utilized. 

Definition of standard imaging conditions 

©Standard imaging condition I: (As imaging device) Use a pattern box (luminance 706 Nit, 3200 K 
Halogen source), at F8 with a typical test lens, and CM-500S (1.0 mmt) for IR cut filter. 

©Standard imaging condition II: Use a light source with uniformity within 2%, color temperature of 
3200 K and CM-500S (1.0 mmt) as IR cut filter. The light intensity is adjusted in accordance 
with the average signals (Va) indicated in each item. 

1. Set to standard imaging condition I and measure signal output (S) at the center of the screen. 

2. Set to standard imaging condition II. Adjust light intensity to 10 times when the average signal 
VA=150mV. Then test signal Min. Value. 

3. Set to standard imaging condition II. Adjust light intensity to 500 times when the average signal 
VA=150mV. Stop Read out clock. When the charge drain executed by the electronic shutter at 
the respective H blankings takes place, test the Max. value Vsm of signal output. 

SM = (Vsm/Va) x V500 x 710 x 100 (%) (VloV) 

4. Set to standard imaging condition II. Adjust light intensity to 1000 times when the average 
signal VA=150mV. Then check that there is no blooming. 



- 108 



SONY, 



ICX027BL 



5. Video signal shading SH 

Set to standard imaging condition II. Test signal Max. (Vmax) and Min. (Vmin) values. Adjust 
light intensity to obtain an average signal (Va) of about 150mV. 

SH = (Vmax - Vmin)A/A x 100 (%) 

6. Test the average signal when the device ambient temperature is at 55°C and light is obstructed 
with horizontal idle transfer level as reference. 

7. Following test 6, test Max. (Vd max) and Min. (Vd min) of signal output. Only keep spot defects 
out of this range. 

AVdt = Vd max - Vd min 

8. Set to imaging condition II. Test the output signal difference (AVf) between even and odd field. At 
that time, adjust light intensity to obtain an average signal Va of about 150mV. 

F = (AVWa) x 100 (%) 

9. Light a stroboscopic tube with the following timing and test the residual image. 
AVIag = (Vlag/Vs)x 100 (%) 



FLD 



I 



SG1 



Jl 1 



SG2- 



Strobe light timing ■ 



Output 



Vs 200mV V lag (Residual image) 

ruj-_ri_ 1 _i :r _n n_ 

t 



_rr 



t 



109- 



SONY® 



ICX027BL 



L-^M — 




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e? 




110- 



SONY® 



ICX027BL 



Spectral Sensitivity Characteristics 

(Excluding light source characteristics, including lens characteristics) 



1.0 I i i i 




I 



Using Read Out Clock Timing Chart 



Odd Field < 



Even Field < 



HD 



V1 
V2 



V3 
V4 



V1 
V2 



V3 
V4 



J L 



J L 



Unites 



111 



SONY® 



ICX027BL 



ft 



— N 

8 8 



— M K> * U3 -J 

> > > > OO O 



- 112 



SONY® 



ICX027BL 



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113 



SONY® ICX027BL 

Handling Instructions 

1) Static charge prevention 

CCD image sensor are easily damaged by static discharge. Before handling be sure to take the 
following protective measures. 

a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use 
conductive shoes. 

b) When handling directly use an earth band. 

c) Install a conductive mat on the floor or working table to prevent the generation of static 
electricity. 

d) Ionized air is recommended for discharge when handling CCD image sensor. 

e) For the shipment of mounted substrates use boxes treated for the prevention of static charges. 

2) Soldering 

a) Make sure the package temperature does not exceed 80°C. 

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 
grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and 
remount cool sufficiently. 

c) To dismount an imaging device do not use a solder pult. When using an electric desoldering 
tool use a thermal controller of the zero cross On/Off type and connect to ground. 

3) Dust and dirt protection 

a) Operate in clean environments (around class 1000 will be appropriate). 

b) Do not either touch glass plates by hand or have any object come in contact with glass 
surfaces. Should dirt stick to a glass surface blow it off with an air blow. (For dirt stuck 
through static electricity ionized air is recommended) 

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not 
to scratch the glass. 

d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool 
when moving to a room with great temperature differences. 

e) When a protective tape is applied before shipping, just before use remove the tape applied for 
electrostatic protection. Do not reuse the tape. 

4) Do not expose to strong light (sun rays) for long periods. 

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage 
or usage in such conditions. 

6) CCD image sensor are precise optical equipment that should not be subject to mechanical shocks. 



114 



SONY. 



ICX038AL 



Solid-State Image Sensor for B/W Camera 



Description 

ICX038AL is an interline transfer CCD solid- 
state imager suitable for EIA 1/2 inch B/W 
video cameras. High sensitiveness is achieved 
through the adoption of HAD ( Hole - 
Accumulation Diode) sensors. 

This chip features a field integration read out 
system and an electronic shutter with variable 
charge-storage time. 

Features 

• High image, high sensitivity and low dark 
current 

• Consecutive various speed shutter 

1/60sec.(Typ.), 1/100sec. to 1/10000sec. 

• Low smear 

• High antiblooming 

• Horizontal register 5V drive 

• Reset gate 5V drive 



Pakage Outline 



Unit : mm 



20 pin DIP (Ceramic) 

18.0«-3 




Effective EtoiMntV Picture CanUf 




( Unit ; mm ) 



Approx. 380k pixels 



Device Structure 

• Optical size 1/2 inch format 

• Number of effective pixels 

768 (H) X494 (V) 

• Number of total pixels 

811 (H) X508 (V) Approx. 410k pixels 

• Interline transfer CCD image sensor 

• Chip size 7.95mm (H) x 6.45mm (V) 

• Unit cell size 8.4 urn (H) x 9.8 urn (V) 

• Optical black Horizontal (H) direction Front 3 pixels Rear Optical black position (Top View) 

40 pixels 

Vertical (V) direction 

• Number of dummy bits Horizontal 

Vertical 

• Substrate material silicon 



[Pin 11 



Front 12 pixels Rear 2 pixels 
22 
1 (even field only) 




E89X30 - ST 



- 115 



SONY® 



ICX038AL 



Block Diagram 




Pin Description 





Pin Configuration 

(Top View) 


V04 


& 






@» H02 


V03 


© 






© H01 


V02 


® 






@ LH01 


SUB 


© 






@ RG 


6ND 
V01 


® 
W 


TOP 


VIEW 


©RD 
(?» GND 


Vu 


^ 






(k) GND 


GNO 


w 






© Vss 


VDO 


© 






(f£) NC 


VOOT 


® 


/~\ 




(h) Vgo 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V*4 


Vertical register transfer clock 


11 


Vgg 


Output amplifier gate bias 


2 


V4>3 


Vertical register transfer clock 


12 


NC 




3 


V4>2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (Overflow drain) 


14 


GND 


GND 


5 


GND 


GND 


15 


GND 


GND 


6 


V «t> i 


Vertical register transfer clock 


16 


RD 


Reset drain bias 


7 


Vl 


Protective transistor bias 


17 


RG 


Reset gate clock 


8 


GND 


GND 


18 


LH 4> i 


Horizontal register final stage transfer clock 


9 


Vdd 


Output amplifier drain supply 


19 


H4u 


Horizontal register transfer clock 


10 


VOUT 


Signal output 


20 


H<(>2 


Horizontal register transfer clock 



Absolute Maximum 


Ratings 








Item 


Ratings 


Unit 


Remarks 


Substrate voltage SUB-GND 


-0.3 to +55 


V 




Supply voltage 


Vdd, Vrd, Vout, Vss - GND 


- 0.3 to +18 


V 




Vdd. Vrd, Vout, Vss - SUB 


-55 to +10 


V 




Clock input voltage 


V<J>1, V<(>2. V <J> 3, V<j>4- GND 


- 1 5 to +20 


V 




V<}>1, V<(>2, V<M, V<M- SUB 


to +10 


V 




Voltage difference between vertical clock input pins 


to + 15 


V 


* (Max.) 


Voltage difference between horizontal clock input pins 


to + 17 


V 




H <|> i. H<t>2-V<M 


- 1 7 to +17 


V 




LH <J> 1, RG, Vgg - GND 


- 1 to +15 


V 




LH*1, RG, Vgg-SUB 


- 55 to +10 


V 




Vl - SUB 


-65 to +0.3 


V 




Beside GND, SUB-Vl 


-0.3 to +30 


V 




Storage temperature 


-30 to +80 


*£ 




Operating temperature 


- 1 to +60 


°C 





* Note) +27V (Max.) when clock width < 10 us, duty factor < 0.1 %. 



- 116 



SONY® 



Bias Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain voltage 


Vdd 


14.55 


15.0 


15.45 


V 




Reset drain voltage 


Vrd 


14.55 


15.0 


15.45 


V 


Vrd = Vdd 


Output amplifier gate voltage 


Vgg 


1.75 


2.0 


2.25 


V 




Output amplifier source 


Vss 


Ground through 
390 Q resistor 




±5% 


Substrate voltage adjustment range 


VSUB 


9.0 




18.5 


V 


*2 


Fluctuation range after substrate voltage 
adjustment 


A Vsub 


-3 




+ 3 


% 




Reset gate clock voltage adjustment 
range 


Vrgl 


0.5 




5.0 


V 


*2 *6 


Fluctuation range after reset gate clock 
voltage adjustment 


A Vrgl 


-3 




+ 3 


% 




Protective transistor bias 


Vl 


*3 







DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain current 


Idd 




5 




mA 




Input current 


llN1 






1 


HA 


*4 


Input current 


llN2 






10 


uA 


*5 



■ 



* 2) Substrate voltage (Vsub) • reset gate clock voltage (Vrgl) setting value display. 

Setting values of substrate voltage and reset gate clock voltage are displayed at the back 
of the device through a code address. Adjust substrate voltage (Vsub) and reset gate clock 
voltage (Vrgl) to the displayed voltage. Fluctuation range after adjustment is ±3%. 



•— Vsub address code 
' Vrgl address code 

Code addresses and actual numerical values correspond to each other as follows. 



Vsub code address - 1 digit display 
Vrgl code address - 1 digit display 



Vrgl address code 





1 


2 


3 


4 


5 


6 


7 


8 


9 




Numerical value 


0.5 


1.0 


1.5 


2.0 


25 


3.0 


3.5 


4.0 


4.5 


5.0 










Vsub 

address 

code 


E 


f 


G 


h 


J 


K 


L 


m 


N 


P 


Q 


R 


S 


T 


U 


V 


W 


X 


Y 


Z 


Numerical 
value 


9.0 


9.5 


10.0 


10.5 


11.0 


11.5 


12.0 


125 


13.0 


13.5 


14.0 


14.5 


15.0 


15.5 


16.0 


16.5 


17.0 


17.5 


18.0 


18.5 



< Example > "5L" -» Vrgl = 3.0V 
Vsub = 12.0V 

* 3) Vl setting is the Vvl voltage of the vertical transfer clock waveform. 



117- 



SONY® 



* 4) 1. Current to each pin when 18V is applied to Vdd, Vout, Vss and SUB pins, while pins 

that are not tested are grounded. 

2. Current to each pins when 20V is applied sequentially to V0 1, V<t>2, V$3, V<t>4, H <J> 1 
and H 2, while pins that are not tested are grounded. However, 20V is applied to SUB. 

3. Current to each pins when 15V is applied sequentially to pins RG, LH <J> 1 and Vgg, 
while pins that are not tested are grounded. However, 15V is applied to. SUB. 

4. Current to Vl pin when it is grounded, while 30V is applied to all pins except pins 
that are not tested. However, GND and SUB pins are kept open. 

* 5) Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are 

grounded. 

Clock Voltage Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Waveform 
diagram 


Remarks 


Read out clock 
voltage 


Vvt 


14.55 


15.0 


15.45 


V 


1 




Vertical transfer 
clock voltage 


VvH1, VVH2 


-0.05 





0.05 


V 


2 


Vvh = (Vvhi+Vvh2)/2 


VvH3, VVH4 


-0.2 





0.05 


V 


2 




VvL1, VVL2, 
VVL3, VVL4 


-9.6 


-9.0 


-8.5 


V 


2 


VvL = (VvL3 + VvL4)/2 


V(t> V 


8.3 


9.0 


9.65 


V 


2 


V cj> v = VvHn - VvLn 
(n = 1 to 4) 


I VVH1 — VVH2 I 






0.1 


V 


2 




VVH3 - VVH 


-0.25 




0.1 


V 


2 




VVH4 — VVH 


-0.25 




0.1 


V 


2 




VvHH 






0.5 


V 


2 


High level coupling 


VvHL 






0.5 


V 


2 


High level coupling 


VvLH 






0.5 


V 


2 


Low level coupling 


VVLL 






0.5 


V 


2 


Low level coupling 


Horizontal 
transfer clock 
voltage 


V(|>H 


4.75 


5.0 


5.25 


V 


3 




Vhl 


-0.05 





0.05 


V 


3 




Horizontal final 
stage transfer 
clock voltage 


Vlhh 


4.45 


5.0 


5.55 


V 


4 




Vlhl 


-4.7 


-4.0 


-3.5 


V 


4 




V<|)LH 


8.0 


9.0 


10.0 


V 


4 




Reset gate clock 
voltage 


V <|> RG 


4.5 


5.0 


5.5 


V 


5 


* 6 


Vrglh - Vrgll 






0.8 


V 


5 


Low level coupling 


Substrate clock 
voltage 


V 4> sub 


23.0 


24.0 


25.0 


V 


6 





118- 



SONY® 



ICX038AL 



* 6) No adjustment of reset gate clock voltage is necessary when reset gate clock is driven 
as indicated below. In this case, reset gate clock voltage set point displayed on back of 
image sensor has no meaning. 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Waveform 
diagram 


Remarks 


Reset gate clock 
voltage 


Vrgl 


-0.2 





0.2 


V 


5 




V <|> RG 


8.5 


9.0 


9.5 


V 


5 





Clock Equivalent Circuit Constant 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Capacitance between vertical transfer 
clock and GND 


C $ V1, C <|> V3 




1800 




PF 




C <(> V2, C <(> V4 




2200 




PF 




Capacitance between vertical transfer 
clocks 


C <t> V12, C <J> V34 




450 




PF 




C <t> V23, C <t> V41 




270 




PF 




Capacitance between horizontal transfer 
clock and GND 


C <J> H1, C <|> H2 




62 




PF 




Capacitance between horizontal transfer 
clocks 


C $ HH 




47 




PF 




Capacitance between horizontal final 
stage transfer clock and GND 


C ((> LH 




8 




PF 




Capacitance between reset gate clock 
and GND 


C RG 




8 




PF 




Capacitance between substrate clock 
and GND 


C $ SUB 




400 




PF 




Vertical transfer clock serial resistor 


Rl. R2, R3, R4 




68 




Q 




Vertical transfer clock ground resistor 


Rgnd 




15 




Q 





■ 




V04 



V<M 



H01 O- 



77T 



Cg>HH 
C0H1 =T ^ C0H2 



7T7 



-OH(J>2 



Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent 

circuit 



119 



SONY® 



ICX038AL 



Drive Clock Waveform Conditions 



(1) Read out clock waveform 




OV 



(2) Vertical transfer clock waveform 



V4>1 



VVH1 VVHH ..„„ 

. -— . r VVH VVHH 




V<t>3 




VVLS 



V<|)2 



V*4 



VVHH VVHH 



VVM 



VVHH 




VVL 




- 120- 



SONY* 



ICX038AL 



(3) Horizontal transfer clock waveform diagram 



90 V. 




VHL 

(4) Horizontal final stage transfer clock waveform diagram 



VLHH 



VLHL 




I 



(5) Reset gate clock waveform diagram 



RG waveform 

Vrglh h 

Vrgll -► 4 



LH1 waveform 

ov -► 




VR6H 



-♦VR6L+0.5V 
VRGL 



Vrglh is the maximum value and Vrgll the minimum value of the coupling waveform in the 
period from Point A in the diagram above to RG rise. 
Vrgl is the mean value for Vrglh and Vrgll. 

Vrgl= (Vrglh + Vrgll) /2 
Vrgh is the minimum value for twh period. 

V <|> rg = Vrgh — Vrgl 



121 - 



SONY® 



ICX038AL 



(6) Substrate clock waveform 



100% — 
90V. — 




Clock switching characteristics 



Item 


Symbol 


twh 


twl 


tr 


tf 


Unit 


Remarks 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Read out clock 


Vt 


2.3 


2.5 












0.5 






0.5 




MS 


During read 
out 


Vertical transfer 
clock 


V 4> t, V <i> 2, 

V (J) 3, V <J) 4 




















0.015 




0.25 


MS 


*7 


Horizontal transfer 
clock 


H4> 




20 






20 






15 


19 


*8 


15 


19 


ns 


During 
imaging 


Horizontal final 
stage clock 


LH<J> 




24 




22 


27 






10 






9 




ns 


During 
imaging 


Horizontal transfer 
/horizontal final 
stage clock 


H 4> 1, LH 4> 




5.38 












0.01 






0.01 




MS 


During 
parallel 
serial 
conversion. 


Horizontal transfer 
clock 


H4.2 










5.38 






0.01 






0.01 




MS 


Reset gate clock 


4> RG 


11 


13 






51 






3 






3 




ns 




Substrate clock 


4> SUB 


1.5 


1.8 














0.5 






0.5 


MS 


During 
charge drain. 



* 7) When vertical transfer clock driver CXD1250 is in use. 

* 8) tf ^ tr - 2 ns 



Item 


Symbol 


two 


Unit 


Remarks 


Min. 


Typ. 


Max. 


Horizontal transfer clock 


H<t> 


16 


20 




ns 


*9 


Horizontal transfer/ 
horizontal final stage clock 


H 2l LH 


15 


20 




ns 


*10 



* 9) "two" is the overlap period of horizontal transfer clocks H <t> 1 and H 4> 2's twh and twl. 

* 10) "two" is the overlap period of horizontal transfer clock H $ 2's twl and horizontal final 

stage transfer clock LH<J>'s twh' 



- 122- 



SONY® 














ICX038AL 


Operating Characteristics 












(Ta = 25°C) 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test method 


Remarks 


Sensitivity 


S 


150 


190 




mV 


1 




Saturation signal 


Vsat 


500 






mV 


2 


Ta = 60°C 


Smear 


Sm 




0.009 


0.015 


% 


3 




Video signal shading 


SH 






20 


% 


4 


Zone 0, I 






25 


% 


4 


Zone to II' 


Dark signal 


Vdt 






2 


mV 


5 


Ta = 60 < C 


Dark signal shading 


AVdt 






1 


mV 


6 


Ta = 60°C 


Flicker 


F 






2 


% 


7 




Lag 


Lag 






0.5 


% 


8 





Zone chart of Video signal shading 



I— 


4 


14— »j 


Hi_ 




H 
5 


r-i 






T 

12 
494 

10 




1 
V 
TO 


0, I 


H 
8 


(V) 


,H 


n. 


n' 






-r* •- 

V 

TO 


\ ^Ignorir 
N — Effecti 


9 re 
ve p 


gion 
ctur« 


s elements 



■ 



Image Sensor Characteristics Test Method 

©Test conditions 

©Through the following tests the substrate voltage and reset gate clock voltage are set to 
the value displayed on the device, while the device drive conditions are at the typical value 
of the bias and clock voltage conditions. 

(D Through the following tests defects are excluded and, unless otherwise specified, the optical 
black level (Hence forth referred to as OB) is set as the reference, the values obtained at 
® point in the figure of the Drive Circuit are utilized. 



- 123- 



SONY® ICX038AL 



©Definition of standard imaging conditions 

© Standard imaging condition I : (As imaging device) Use a pattern box (luminance 706 Nit, color 
temperature 3200k Halogen source) as a subject. (Pattern for evaluation is not applicable.) 
Use a testing standard lens with CM500S (LOmmt) as IR cut filter and image at F8. At this 
time, light intensity to sensor receiving surface is defined as standard sensitivity testing light 
intensity. Signal output average value in this condition is called Va. 

d) Standard imaging condition II : Image a light source (color temperature of 3200k) which 
uniformity of brightness is within 2% at all angles. Use a testing standard lens with CM500S 
(LOmmt) as IR cut filter. The light intensity is adjusted to the value indicated in each testing 
item by lens diaphragm. 

1 . Sensitivity 

Set to standard imaging condition I and measure signal output (S) at the center of the 
screen. 

2. Saturation signal 

Set to standard imaging condition II. Adjust light intensity to 10 times that of signal output 
average value (Va), then test signal output minimum value. 

3. Smear 

Set to standard imaging condition II. Adjust light intensity to 500 times that of signal 
output average value (Va). Stop read out clock. When the charge drain executed by the 
electric shutter at the respective H blankings takes place, test the maximum value Vsm of 
signal output. 

Sm =^f x 556 x To x,OOW)(,/10v> 

4. Video signal shading 

Set to standard imaging condition II. Adjust light intensity to signal output average value 
(Va) with lens diaphragm at F5.6 to F8. Then test maximum (Vmax) and minimum (Vmin) 
values of signal output. 

SH= (Vmax - Vmin)/V A x 100 (%) 

5. Dark signal 

Test signal output average value Vdt when the device ambient temperature is at 60°C and 
light is obstructed with horizontal idle transfer level as reference. 

6. Dark signal shading 

Following 5, test maximum (Vdmax) and minimum (Vdmin) values of dark signal output. 

A Vdt = Vdmax - Vdmin 



- 124- 



SONY® 



ICX038AL 



7. Flicker 

Set to standard imaging condition II. Adjust light intensity to signal output average value 
(Va). Then test the signal output difference (AVf) between even field and odd field. 

F= (AVf/V A ) x 100 (%) 

8. Residual image 

Adjust signal output value (Vs) by strobe light to 200mV. Then light a stroboscopic tube 
with the following timing and test the residual image (Vlag). 

Lag = (Vlag/Vs) x 100 (96) 



FLD 



SG1 



Strobe light timing 



Output 



_n 



Vs 200mV V lag (Residual image) 

^J.^ 



■ 



n_ 



125 



SONY® 



ICX038AL 



> 




126 



SONY® 



ICX038AL 



Spectral Sensitivity Characteristics 

(Excluding light source characteristics, including lens characteristics) 




600 700 800 

Wave Length (nm) 



I 



Using read out clock timing chart 

HD • 1 



ODD FIELD < 



EVEN FIELD 



VI 
V2 

V3 
V4 



VI 
V2 

V3 
V4 



40.6 



'2.51 

1 ■ ' 



!).6 I 2-5 



I I 
I I 



J-L 



Unit : (is 



127 



SONY® 



ICX038AL 




> 

t 
(0 

.c 
O 

o> 

c 

£ 



> 



128 



SONY* 



ICX038AL 



C 

o 

N 
"C 

o 

I 

t 

(0 

o 

0) 

c 
E 


> 



I 



129 



SONY® ICX038AL 



Handling Instructions 

1) Static charge prevention 

CCD image sensors are easily damaged by static discharge. Before handling be sure to take 
the following protective measures. 

a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use 
conductive shoes. 

b) When handling directly use an earth band. 

c) Install a conductive mat on the floor or working table to prevent the generation of static 
electricity. 

d) Ionized air is recommended for discharge when handling CCD image sensor. 

e) For the shipment of mounted substrates use boxes treated for the prevention of static 
charges. 

2) Soldering 

a) Make sure the package temperature does not exceed 80 °C. 

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. 
Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For 
repairs and remount, cool sufficiently. 

c) To dismount an imaging device do not use a solder suction equipment. When using an 
electric desoldering tool use a thermal controller of the zero cross On/Off type and 
connect to ground. 

3) Dust and dirt protection 

a) Operate in clean environments (around class 1000 will be appropriate). 

b) Do not either touch glass plates by hand or have any object come in contact with glass 
surfaces. Should dirt stick to a glass surface blow it off with an air blow. (For dirt 
stuck through static electricity ionized air is recommended) 

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be 
careful not to scratch the glass. 

d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or 
precool when moving to a room with great temperature differences. 

e) When a protective tape is applied before shipping, just before use remove the tape 
applied for electrostatic protection. Do not reuse the tape. 

4) Do not expose to strong light (sun rays) for long periods, color filters are discolored. 

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid 
storage or usage in such conditions. 

6) CCD image sensor are precise optical equipment that should not be subject to mechanical 
shocks. 

7) Defect compensation ROM 

This is shipped in its own case in pair with the CCD image sensor. 

Pair with the CCD image sensor bearing the same serial number during mounting. When 

the CCD image sensor has no defect, there is no ROM or serial number. 



130- 



SONY. 



ICX039AL 



Solid-State Image Sensor for B/W Camera 



Description 

ICX039AL is an interline transfer CCD solid- 
state imager suitable for CCIR 1/2 inch B/W 
video cameras. High sensitiveness is achieved 
through the adoption of HAD ( Hole - 
Accumulation Diode) sensors. 

This chip features a field integration read out 
system and an electronic shutter with variable 
charge-storage time. 

Features 

• High image, high sensitivity and low dark 
current 

• Consecutive various speed shutter 

1/50sec.(Typ.), 1/100sec. to 1/10000sec. 

• Low smear 

• High antiblooming 

• Horizontal register 5V drive 

• Reset gate 5V drive 



Pakage Outline 



Unit : mm 



20 pin DIP (Ceramic) 
18.0'o.j 





Effective EHmwIj Pictura C«ot«» 




f- 5* 



( Unit ; mm ) 



I 



Device Structure 

• Optical size 1/2 inch format 

• Number of effective pixels 

752 (H) X582 (V) 

• Number of total pixels 

795 (H) X596 (V) 

• Interline transfer CCD image sensor 

• Chip size *7.95mm (H) x 6.45mm (V) 

• Unit cell size 8.6 \im (H) x 8.3 urn (V) 

• Optical black Horizontal (H) direction 

40 pixels 

Vertical (V) direction 

• Number of dummy bits Horizontal 

Vertical 

• Substrate material silicon 



Approx. 440k pixels 
Approx. 470k pixels 




3Hh 



|Pin 111 
Front 3 pixels Rear Optical black position (Top View) 

Front 12 pixels Rear 2 pixels 
22 
1 (even field only) 



E89X34 - ST 



- 131 - 



SONY® 



ICX039AL 



Block Diagram 




v»(5) — • 








HH 




Now 




HH 


5 


HZI 




| 






HZI 




-u 




HZ] 


41 


HZ 


V««(h)— . 






-o 




-a 




-a 


H 


HZ 


NC (li) 


1 
3 






-U 




<D 


J 


-a 


1 


HZ1 


vii X 






T^ 




HH V 










Horizonli 

f 




ONO(|4) 








ON0(js) ,— 






1 













Pin Configuration 

(Top View) 



"0 RO LH»1 H»1 H#l 

Not*) - I 1 : Pholo Mnsor 



Pin Description 



V04 


V 




@)H02 


V03 


(|) 




© H01 


V02 


@) 




(jj) LH01 


SUB 


(4) 




^7) RG 


GNO 
V01 




TOP VIEW 


H6) RD 
HS GND 


Vl 







® GND 


GNO 


® 




(l3) Vss 


VDD 


® 




(g) NC 


VOUT 


® 


/~\ 


(n) Vgg 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V(J)4 


Vertical register transfer clock 


11 


Vgg 


Output amplifier gate bias 


2 


V(|)3 


Vertical register transfer clock 


12 


NC 




3 


V4>2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (Overflow drain) 


14 


GND 


GND 


5 


GND 


GND 


15 


GND 


GND 


6 


V*i 


Vertical register transfer clock 


16 


RD 


Reset drain bias 


7 


Vu 


Protective transistor bias 


17 


RG 


Reset gate clock 


8 


GND 


GND 


18 


LH.J.I 


Horizontal register final stage transfer clock 


9 


Vdd 


Output amplifier drain supply 


19 


H 4> i 


Horizontal register transfer clock 


10 


VOUT 


Signal output 


20 


H<j)2 


Horizontal register transfer clock 



Absolute Maximum 


Ratings 








Item 


Ratings 


Unit 


Remarks 


Substrate voltage SUB-GND 


-0.3 to +55 


V 




Supply voltage 


Vdd, Vrd, Vout, Vss - GND 


- 0.3 to +18 


V 




Vdd, Vrd, Vout, Vss - SUB 


- 55 to +10 


V 




Clock input voltage 


V<(>1, V $ 2, V $ 3. V<M- GND 


-15 to +20 


V 




V<|>1, V<t>2, V4>3, V<M- SUB 


to + 10 


V 




Voltage difference between vertical clock input pins 


to+ 15 


V 


* (Max.) 


Voltage difference between horizontal clock input pins 


to+ 17 


V 




H <J> 1, H <t>2-V<M 


- 1 7 to +17 


V 




LH<D 1, RG. Vgg-GND 


- 1 to +15 


V 




LH<(> 1, RG, Vgg-SUB 


- 55 to +10 


V 




Vl - SUB 


-65 to +0.3 


V 




Beside GND, SUB-Vl 


-0.3 to +30 


V 




Storage temperature 


-30 to +80 


V 




Operating temperature 


- 1 to +60 


°C 





*Note) +27V (Max.) when clock width < 10 us, duty factor < 0.1 %. 



132 



SONY® 



ICX039AL 



Bias Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain voltage 


Vdd 


14.55 


15.0 


15.45 


V 




Reset drain voltage 


Vrd 


14.55 


15.0 


15.45 


V 


Vrd = Vdd 


Output amplifier gate voltage 


Vgg 


1.75 


2.0 


2.25 


V 




Output amplifier source 


Vss 


Ground through 
390 Q resistor 




±5% 


Substrate voltage adjustment range 


VSUB 


9.0 




18.5 


V 


*2 


Fluctuation range after substrate voltage 
adjustment 


A Vsub 


-3 




+ 3 


% 




Reset gate clock voltage adjustment 
range 


Vrgl 


0.5 




5.0 


V 


*2 *6 


Fluctuation range after reset gate clock 
voltage adjustment 


A Vrgl 


-3 




+ 3 


% 




Protective transistor bias 


Vl 


*3 







DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain current 


Idd 




5 




mA 




Input current 


llN1 






1 


HA 


*4 


Input current 


llN2 






10 


uA 


*5 



* 2) Substrate voltage (Vsub) • reset gate clock voltage (Vrgl) setting value display. 

Setting values of substrate voltage and reset gate clock voltage are displayed at the back 
of the device through a code address. Adjust substrate voltage (Vsub) and reset gate clock 
voltage (Vrgl) to the displayed voltage. Fluctuation range after adjustment is ± 3 %. 



Vsub code address — 1 digit display 
Vrgl code address - 1 digit display 



■—Vsub address code 
' Vrgl address code 

Code addresses and actual numerical values correspond to each other as follows. 



Vrgl address code 





1 


2 


'3 


4 


5 


6 


7 


8 


9 




Numerical value 


0.5 


1.0 


1.5 


2.0 


2.5 


3.0 


3.5 


4.0 


4.5 


5.0 






















Vsub 

address 

code 


E 


f 


G 


h 


J 


K 


L 


m 


N 


P 


Q 


R 


S 


T . 


U 


V 


W 


X 


Y 


Z 


Numerical 
value 


9.0 


9.5 


10.0 


10.5 


11.0 


11.5 


12.0 


125 


13.0 


13.5 


14.0 


14.5 


15.0 


15.5 


16.0 


16.5 


17.0 


175 


18.0 


18.5 



Vrgl = 3.0V 
Vsub = 1 2.0V 



< Example > "5L" 
* 3) Vl setting is the Vvl voltage of the vertical transfer clock waveform. 



133- 



SONY® 



ICX039AL 



*4) 1. Current to each pin when 18V is applied to Vdd, Vout, Vss and SUB pins, while pins 
that are not tested are grounded. 

2. Current to each pins when 20V is applied sequentially to V <t> 1, V $ 2, V $ 3, V 4> 4, H $ 1 
and H $ 2, while pins that are not tested are grounded. However, 20V is applied to SUB. 

3. Current to each pins when 15V is applied sequentially to pins RG, LH $ 1 and Vgg, 
while pins that are not tested are grounded. However, 15V is applied to SUB. 

4. Current to Vt_ pin when it is grounded, while 30V is applied to all pins except pins 
that are not tested. However, GND and SUB pins are kept open. 

* 5) Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are 
grounded. 



Clock Voltage Conditions 














Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Waveform 
diagram 


Remarks 


Read out clock 
voltage 


Vvt 


14.55 


15.0 


15.45 


V 


1 




Vertical transfer 
clock voltage 


VvH1, VVH2 


-0.05 





0.05 


V 


2 


Vvh = (Vvhi+Vvh2)/2 


VVH3, VVH4 


-0.2 





0.05 


V 


2 




VvL1, VvL2, 
VvL3, VVL4 


-9.6 


-9.0 


-8.5 


V 


2 


VvL = (VvL3 + VvL4)/2 


V(|> V 


8.3 


9.0 


9.65 


V 


2 


V <t> v = VvHn — Vvi_n 
(n = 1 to 4) 


| VVH1 -VVH2 I 






0.1 


V 


2 




VVH3 — VvH 


-0.25 




0.1 


V 


2 




VVH4 — VVH 


-0.25 




0.1 


V 


2 




VvHH 






0.5 


V 


2 


High level coupling 


VVHL 






0.5 


V 


2 


High level coupling 


VVLH 






0.5 


V 


2 


Low level coupling 


VVLL 






0.5 


V 


2 


Low level coupling 


Horizontal 
transfer clock 
voltage 


V4>H 


4.75 


5.0 


5.25 


V 


3 




Vhl 


-0.05 





0.05 


V 


3 




Horizontal final 
stage transfer 
clock voltage 


Vlhh 


4.45 


5.0 


5.55 


V 


4 




Vlhl 


-4.7 


-4.0 


-3.5 


V 


4 




V<t>LH 


8.0 


9.0 


10.0 


V 


4 




Reset gate clock 
voltage 


V <|> RG 


4.5 


5.0 


5.5 


V 


5 


* 6 


Vrglh — Vrgll 






0.8 


V 


5 


Low level coupling 


Substrate clock 
voltage 


V (t> SUB 


23.0 


24.0 


25.0 


V 


6 





134 



SONY® 



ICX039AL 



* 6) No adjustment of reset gate clock voltage is necessary when reset gate clock is driven 
as indicated below. In this case, reset gate clock voltage set point displayed on back of 
image sensor has no meaning. 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Waveform 
diagram 


Remarks 


Reset gate clock 
voltage 


Vrgl 


-0.2 





0.2 


V 


5 




V 4> rg 


8.5 


9.0 


9.5 


V 


5 





Clock Equivalent Circuit Constant 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Capacitance between vertical transfer 
clock and GND 


C <(> V1, C <J) V3 




1800 




PF 




C $ V2, C V4 




2200 




PF 




Capacitance between vertical transfer 
clocks 


C <j> V12, C 4> V34 




450 




PF 




C <|> V23, C <(> V41 




270 




PF 




Capacitance between horizontal transfer 
clock and GND 


C <t> H1, C H2 




62 




PF 




Capacitance between horizontal transfer 
clocks 


C <t> HH 




47 




PF 




Capacitance between horizontal final 
stage transfer clock and GND 


C <J> LH 




8 




PF 




Capacitance between reset gate clock 
and GND 


C0RG 




8 




PF 




Capacitance between substrate clock 
and GND 


C <t> SUB 




400 




PF 




Vertical transfer clock serial resistor 


Ri, R2, R3, R4 




68 




Q 




Vertical transfer clock ground resistor 


Rgnd 




15 




Q 





■ 



C0V 12 J£<- V02 
R2 




C<*>V4I== xat>v2^c<pvzz 

C0V4/ 



V04 



V<*>3 



H0\ O- 



C0H1 =r 



VT 



C0HH 



:£ C0H2 



Ttr 



-OH<J>2 



Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent 

circuit 



- 135 



SONY® 



ICX039AL 



Drive Clock Waveform Conditions 



(1) Read out clock waveform 









i 


, 


100 Vo 








90 V. 


7i " 


\ 






/T_'_ ^ 


_ j _ _ _ _ _ 


<f>M 




/ ! VVT i \ £M 

1 ' ' \ 2 






HOV. 


/ i - ! H^ :l» 




' tr I twh i tf ' 
i< »i« H« — rt 







ov 



(2) Vertical transfer clock waveform 



V«>1 



VVH1 VVHH yvH 

WS.L.y. 




V + 3 




V<t>2 



V<(.4 



VVHH VVHH 



VVH 




VVHH VVHH 



VVL 



Tc£T\y 




VVL4 



VVL 



- 136 



SONY* 



ICX039AL 



(3) Horizontal transfer clock waveform diagram 



90 V. 



iov. 



VHL 




twh 



V4>H 




(4) Horizontal final stage transfer clock waveform diagram 



VLHH 



VLHL 





(5) Reset gate clock waveform diagram 



RG waveform 

Vrglh-*- 

Vrgll-** 



LH1 waveform 

ov -► 



tr . twh tf 




VRGH 



VRGL+ 0.5V 
VRGL 



Vrglh is the maximum value and Vrgll the minimum value of the coupling waveform in the 
period from Point A in the diagram above to RG rise. 
Vrgl is the mean value for Vrglh and Vrgll. 

Vrgl= (Vrglh + Vrgll) /2 
Vrgh is the minimum value for twh period. 

V <t> rg = Vrgh - Vrgl 



137 



SONY® 



ICX039AL 



(6) Substrate clock waveform 




Clock switching characteristics 



Item 


Symbol 


twh 


twl 


tr 


tf 


Unit 


Remarks 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Read out clock 


Vt 


2.3 


2.5 












0.5 






0.5 




MS 


During read 
out 


Vertical transfer 
clock 


V(J>1, V<f>2, 
V <t> 3. V <t> 4 




















0.015 




0.25 


MS 


*7 


Horizontal transfer 
clock 


H* 




20 






20 






15 


19 


*8 


15 


19 


ns 


During 
imaging 


Horizontal final 
stage clock 


LHd> 




24 




22 


27 






10 






9 




ns 


During 
imaging 


Horizontal transfer 
/horizontal final 
stage clock 


H 4> i, LH 4> 




5.38 












0.01 






0.01 




MS 


During 
parallel 
serial 
conversion. 


Horizontal transfer 
clock 


H4.2 










5.38 






0.01 






0.01 




MS 


Reset gate clock 


<J> RG 


11 


13 






51 






3 






3 




ns 




Substrate clock 


<t> SUB 


1.5 


1.8 














0.5 






0.5 


MS 


During 
charge drain. 



* 7) When vertical transfer clock driver CXD1250 is in use. 
*8) tf ^tr-2 ns 



Item 


Symbol 


two 


Unit 


Remarks 


Min. 


Typ. 


Max. 


Horizontal transfer clock 


H<|> 


16 


20 




ns 


*9 


Horizontal transfer/ 
horizontal final stage clock 


H $ 2, LH $ 


15 


20 




ns 


*10 



* 9) "two" is the overlap period of horizontal transfer clocks H <(> 1 and H 4> 2's twh and twl. 

* 10) "two" is the overlap period of horizontal transfer clock H 4> 2's twl and horizontal final 

stage transfer clock LH<t>'s twh' 



138 



SONY® 



ICX039AL 



Operating Characteristics 












(Ta = 25t) 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test method 


Remarks 


Sensitivity 


S 


140 


180 




mV 


1 




Saturation signal 


Vsat 


450 






mV 


2 


Ta = 60 < £ 


Smear 


Sm 




0.009 


0.015 


% 


3 




Video signal shading 


SH 






20 


% 


4 


Zone 0, 1 






25 


% 


4 


Zone to II' 


Dark signal 


Vdt 






2 


mV 


5 


Ta = 60°C 


Dark signal shading 


AVdt 






1 


mV 


6 


Ta = 60°C 


Flicker 


F 






2 


% 


7 




Lag 


Lag 






0.5 


% 


8 





Zone chart of Video signal shading 



h-12 



752 (H) 



12— H- 



w 



TO 



0,1 



^ 



V 

TO 



^ 



n, n' 



582 (V) 



Ignoring region 

Effective picture elements 



I 



Image Sensor Characteristics Test Method 
©Test conditions 



(D Through the following tests the substrate voltage and reset gate clock voltage are set to 
the value displayed on the device, while the device drive conditions are at the typical value 
of the bias and clock voltage conditions. 

(2) Through the following tests defects are excluded and, unless otherwise specified, the optical 
black level (Hence forth referred to as OB) is set as the reference, the values obtained at 
@ point in the figure at the Drive Circuit are utilized. 



- 139 



SONY® 



ICX039AL 



©Definition of standard imaging conditions 

© Standard imaging condition I : (As imaging device) Use a pattern box (luminance 706 Nit, color 
temperature 3200k Halogen source) as a subject. (Pattern for evaluation is not applicable.) 
Use a testing standard lens with CM500S (LOmmt) as IR cut filter and image at F8. At this 
time, light intensity to sensor receiving surface is defined as standard sensitivity testing light 
intensity. Signal output average value in this condition is called Va. 

(D Standard imaging condition II : Image a light source (color temperature of 3200k) which 
uniformity of brightness is within 2% at all angles. Use a testing standard lens with CM500S 
(LOmmt) as IR cut filter. The light intensity is adjusted to the value indicated in each testing 
item by lens diaphragm. 

1 . Sensitivity 

Set to standard imaging condition I and measure signal output (S) at the center of the 
screen. 

2. Saturation signal 

Set to standard imaging condition II. Adjust light intensity to 10 times that of signal output 
average value (Va), then test signal output minimum value. 

3. Smear 

Set to standard imaging condition II. Adjust light intensity to 500 times that of signal 
output average value (Va). Stop read out clock. When the charge drain executed by the 
electric shutter at the respective H blankings takes place, test the maximum value Vsm of 
signal output. 

Sm = ^ Qx 500 X W Xl00(%)(l/10V) 

4. Video signal shading 

Set to standard imaging condition II. Adjust light intensity to signal output average value 
(Va) with lens diaphragm at F5.6 to F8. Then test maximum (Vmax) and minimum (Vmin) 
values of signal output. 

SH= (Vmax- Vmin)/VA X 100 (%) 

5. Dark signal 

Test signal output average value Vdt when the device ambient temperature is at 60°C and 
light is obstructed with horizontal idle transfer level as reference. 

6. Dark signal shading 

Following 5, test maximum (Vdmax) and minimum (Vdmin) values of dark signal output. 

A Vdt = Vdmax - Vdmin 



- 140- 



SONY® 



ICX039AL 



7. Flicker 

Set to standard imaging condition II. Adjust light intensity to signal output average value 
(Va). Then test the signal output difference (AVf) between even field and odd field. 

F= (AVf/V A ) x 100 (%) 

8. Residual image 

Adjust signal output value (Vs) by strobe light to 200mV. Then light a stroboscopic tube 
with the following timing and test the residual image (Vlag). 

Lag= (Vlag/Vs) x 100 (%) 



FLD 



S61 



Strobe light timing 



Output 



Vs 200mV V lag (Residual image) 

_n n i n j^ n n 

t 



141 



SONY® 



o 




- 142 



SONY® 



ICX039AL 



Spectral Sensitivity Characteristics 

(Excluding light source characteristics, including lens characteristics) 



.9 
.8 


/^ 












I 
























.6 
.5 
.4 
.3 
.2 


1 












I 











































































600 700 800 

Wave Length (nm) 



Using read out c 


ock timing 


chart 










i 


1 1 




1 J" 












u? .. 


1 1 


'2.51 




1 1 




V* 


I l 


1 1 I 


1 I 


ODD FIELD A 


1 1 1 
1 1 1 


1 1 






1 1 


1 ' i 




1 




V4 




1 1 1 






1 i 


| | 






41.8 


'1.5 I2.6]2.5]25 




" 


H 1* |* 












1 1 






V 1 


1 1 










V* 


' ' 




1 


EVEN FIELD < 




' i 
_| 1__ 






1 1 


i 




1 




va. 










1 1 


I 



Unit : \is 



- 143- 



SONY* 



ICX039AL 



3 & 



s a 



> 



(0 

X 

O 

O) 

c 
E 
H 

o 

> 



•- CVI 
CO CD 



Q Q iC Q 

-J > -J I 



O D 
OO 



144- 



SONY® 



ICX039AL 



L 



c 
o 

N 

o 

X 



o 



- 145 



SONY® ICX039AL 



Handling Instructions 

1) Static charge prevention 

CCD image sensors are easily damaged by static discharge. Before handling be sure to take 
the following protective measures. 

a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use 
conductive shoes. 

b) When handling directly use an earth band. 

c) Install a conductive mat on the floor or working table to prevent the generation of static 
electricity. 

d) Ionized air is recommended for discharge when handling CCD image sensor. 

e) For the shipment of mounted substrates use boxes treated for the prevention of static 
charges. 

2) Soldering 

a) Make sure the package temperature does not exceed 80 "C. 

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. 
Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For 
repairs and remount, cool sufficiently. 

c) To dismount an imaging device do not use a solder suction equipment. When using an 
electric desoldering tool use a thermal controller of the zero cross On/Off type and 
connect to ground. 

3) Dust and dirt protection 

a) Operate in clean environments (around class 1000 will be appropriate). 

b) Do not either touch glass plates by hand or have any object come in contact with glass 
surfaces. Should dirt stick to a glass surface blow it off with an air blow. (For dirt 
stuck through static electricity ionized air is recommended) 

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be 
careful not to scratch the glass. 

d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or 
precool when moving to a room with great temperature differences. 

e) When a protective tape is applied before shipping, just before use remove the tape 
applied for electrostatic protection. Do not reuse the tape. 

4) Do not expose to strong light (sun rays) for long periods, color filters are discolored. 

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid 
storage or usage in such conditions. 

6) CCD image sensor are precise optical equipment that should not be subject to mechanical 
shocks. 

7) Defect compensation ROM 

This is shipped in its own case in pair with the CCD image sensor. 

Pair with the CCD image sensor bearing the same serial number during mounting. When 

the CCD image sensor has no defect, there is no ROM or serial number. 



146- 




CCD Camera (Color) 




2) CCD Camera (Color) 



Type 


Application 


Function 


Page 


Optical 

size 

(inch) 


TV 

System 


Picture 

elements 

(HXV) 


Remarks 


ICX018CK 


CCD Image Sensor 
for color 


2/3 


NTSC 


510X492 




149 


ICX021CK 


2/3 


PAL 


500X582 




IU018CK-AB 


CCD Image Sensor 
for color unit 


2/3 


NTSC 


510X492 


Optical low-pass filter 
IR cut filter 


161 


IU021CK-AB 


2/3 


PAL 


500X582 


Optical low-pass filter 
IR cut filter 


ICX022AK-3 


CCD Image Sensor 
for color 


2/3 


NTSC 


768X493 




164 


ICX024AK-3 


CCD Image Sensor 
for color 


2/3 


PAL 


756X581 




179 


IU022AK-30A 
IU022AK-40A 


CCD Image Sensor 
for color unit 


2/3 


NTSC 


768X493 


Optical low-pass filter 
IR cut filter 


194 


IU024AK-30A 
IU024AK-40A 


2/3 


PAL 


756X581 


Optical low-pass filter 
IR cut filter 


ICX022AN-3 


CCD Image Sensor 
for color 


2/3 


NTSC 


768X493 




197 


ICX024AN-3 


CCD Image Sensor 
for color 


2/3 


PAL 


756X581 




214 


ICX026BK 


CCD Image Sensor 
for color 


1/2 


NTSC 


510X492 


600mil shrink package 


231 


ICX027BK 


CCD Image Sensor 
for color 


1/2 


PAL 


500 x 582 


600mil shrink package 


246 


ICX038AK 


CCD Image Sensor 
for color 


1/2 


NTSC 


768X494 


600mil shrink package 


261 


ICX039AK 


CCD Image Sensor 
for color 


1/2 


PAL 


752X582 


600mil shrink package 


278 



- 148 



SONY. 



ICX018CK/ICK021CK 



Solid-State Image Device for NTSC/CCIR Color TV System 



Description 

ICX018CK and ICX021CK are interline transfer 
CCD solid-state imaging devices developed for 
NTSC one-chip color cameras. The color coding of 
G-stripe, R/B line sequential system. 
ICX018CK:for NTSC 
ICX021CK:for CCIR 

Features 

• Number of effective pixels 



Package Outline 



Unit : mm 



ICX018CK :510 (H) x 


492 (V) 




ICX021CK:500 (H) x 


582 (V) 




• Number of optical black 


elements 




Horizontal (H) direction 


ICX018CK 


ICX021CK 


in front 


2 pixels. 


2 pixels 


in back 


20 pixels 


30 pixels 


Vertical (V) direction 






in front 


12 pixels 


14 pixels 


• High sensitivity 






• Low smear 






• Anti-blooming 






• Low lag, no burning 








2-^2.5 



02.0 



20 pin DIP (Plastic) 

27.0 

26.0 _ P.9 



2.54 



9X2.54=22.86 



31.4MAX 



2.0X2.5 




0A6 
1.27 



• Resistance to electro-magnetic field and microphonic noise. 

• Precise image geometry 

• y characteristic 1 

• ROM for blemish compensation and correlated double sampling attached with the device. 



I 



Layout of Optical Black Elements 

w — 



•1 



10 



Pin 11 



fe^i 



Pin 1 



12 Pixels 



- H — 

2 Pixels "*~~ 20 Pixels 

Fig. 1-a. ICX018CK (NTSC) 



Pin 11 



Pin 1 



2-L 



14 Pixels 



[— H — 
2 Pixels ~" — 30 Pixels 
Fig. 1-b. ICX021CK (CCIR) 



Device Organization 

• Interline transfer CCD image sensor 

• Unit cell size ICX018CK ICX021CK 

1 7 nm (H) x 1 3 Mm (V) 1 7 urn (H) x 1 1 um (V) 

• Number of dummy bits 8 bits horizontal, 1 bit vertical (even field only) 

• Chip size 10.0 mm (H) x 9.3 mm (V) 

• Thin polysilicon gate MOS diode sensor using the multi-layer interference effect. 

• On-chip, high-sensitivity output amplifier 

• Hybrid filter, G stripe, R/B line sequential 

• P-sub, P-well structure 



81 103 -ST 



149 



SONY® 



ICX018CK/ICX021CK 



Absolute Maximum Ratings 

• Supply voltages Vddi, Vdd2, and Vpd 

• Horizontal and vertical clock pins - SUB 

• Between horizontal clocks, between vertical clocks 

• Horizontal and vertical clock pins — Sensor gate 

• Pins other than those listed above 

• Storage temperature 

• Operating temperature 



-0.3 to +30 V -, 




- 20 to + 20 V 




22 V 


l- (SUB = 0V) 


18 V 




-0.3 to +20 V J 




- 30 to + 80 ^C 




- 10 to +55 °C 





Block Diagram and Pin Configuration (Top View) 



ICX018CK 



Vddz Vdoi ED OFD SG 



V^l SUB V*2 V*J V*4 



o 
o 



'ii ii * 
ii i ii/ 



"sHiD 
SHU 



O 

o 




OUT V»o Vss PD PG HOG H»2 H$i NC NC 



ICX021CK 



VD02 Vooi ED OFD SG V^i SUB V?2 V^J Vf< 




* Note - | | ; Photosensor 



OUT Vso Vsj P0 PG HOG H»2 H*l NC NC 



- 150- 



SONY® ICX018CK/ICX021CK 


Pin Description 


No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V<(>4 


Vertical register transfer clock input 


11 


OUT 


Signal output* 


2 


V(|>3 


Vertical register transfer clock input 


12 


Vgg 


Output amplifier gate bias* 


3 


V(|>2 


Vertical register transfer clock input 


13 


Vss 


Output amplifier source bias* 


4 


SUB 


Substrate 


14 


PD 


Output reset drain* 


5 


V<|>1 


Vertical register transfer clock input 


15 


PG 


Output reset clock* 


6 


SG 


Sensor gate bias 


16 


HOG 


Horizontal register read out control 
bias* 


7 


OFD 


Anti-blooming bias* 


17 


H<j>2 


Horizontal register transfer clock 
input 


8 


ED 


Edge drain bias* 


18 


H$1 


Horizontal register transfer clock 
input 


9 


Vddi 


Power supply* 


19 


NC 




10 


VDD2 


Power supply* 


20 


NC 





* Note) Never supply negative voltage to pins. 



DC Bias Conditions 

(Some of the characteristics shown below are determined by the recommended circuit in Fig. 4. 
Refer to Note 1 through 8.) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


Substrate bias 


Vsub 









V 


Vsub = GND 


Output circuit supply voltages 


Vddi 


19 


20 


21 


V 


Vddi = VDD2 


VDD2 


19 


20 


21 


V 


Vpd 


17 


18.1- 


19.2 


V 


Note 1 


Vss 


Grounded with 2.2 k Q resistor 




Note 2 


Vgg 


7 


9 


10 


V 


Note 1 


Anti-blooming bias 


VOFD 


11 


12 


13 


V 


Note 3 


Edge drain bias 


Ved 


Ved = Vofd 


HOG bias 


Vhog 


0.8 


1.0 


1.2 


V 




Sensor gate bias 


VSG 


8.5 


9.5 


10.5 


V 


Note 3 



I 



DC Characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


DC supply current 


Idd 




3.2 


4 


mA 


Note 4 


Input current 1 


linl 






1 


HA 


Note 5 


Input current 2 


Iin2 






10 


HA 


Note 6 



- 151 - 



SONY® 



ICX018CK/ICX021CK 



Clock Voltage Conditions 

(Some of the characteristics shown below are determined by the recommended circuit in Fig. 4.) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


Read out pulse 


Vvt 


11.0 


13.0 


14.0 


V 


Note 3 


Vertical transfer clocks 














Low level 


Vvl 


-5.5 


-5.0 ' 


-4.5 


V 


Note 3 


Amplitude 


V<t>v 


6.8 


7.5 




V 


Horizontal transfer clocks 






/ 








Low level 


Vhl 


-4.4 


-4.0 


-3.6 


V 




High level 


Vhh 


0.8 


1.0 


4.4 


V 


Note 7 


Amplitude 


V$H 


4.75 


5.0 


8.8 


V 


Note 7 


Output reset clock 




Low level 


VPGL 


1.0 


1.3 


1.7 


V 


Note 8 


High level 


Vpgh 


8.9 


9.3 


10.5 


V 




Amplitude 


Vpg 


7.2 


8.0 


8.8 


V 





Clock Capacitance 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remark 


Vertical transfer clock vs. GND 


C<J>v 




6200 




PF 




Between vertical transfer clocks 


C<|>w 




1800 




pF 




Output reset clock 


C<|>PG 




14 




PF 





Hrfl- 



60p 

HI r H * 2 



60p4= =f=50p 

7777 7777 



Fig. 3. Horizontal Transfer Clock Equivalent Circuit 

Note) 

1. Vpo, Vgg and Vhog should be produced from Vddi, and Vdd2. Resistance precision should be 
± 5 %. See Figs. 4 and 5. 

2. Vss should be self-biased and should be connected to GND through a 2.2 kQ (±5%) resistor. 

3. Vvhh ± 5.1 £ Vsg ^ Vvt - 1 .5 Vvt ^ Vofd + 2 (unit : V) 

Vvhh is the maximum level of the waveforms containing couplings of vertical transfer clocks 

V <(> 1 to V <t> 4 excluding the period in which a three level VT is pulsed. 

4. Total output amplifier current, when the load resistance is 2.2 kQ. 

5. The current to the substrate when 20V is sequentially applied to pins V $ 1 , V <p 2, V <J> 3, 

V <J> 4, H <|> 1 , and H <t> 2. 



- 152- 



SONY® 



ICX018CK/ICX021CK 



6. The current to the substrate when 20V is applied to SG, ED, OFD, PD and HOG independently. 
The pins which have not been measured, should be connected to the ground. 



1 



0.47,/ 



T 



— t— OVcr. 
it 0.47*. 



1 



0.47ji 



Fig. 4. Recommended Circuit for Bias Setting of VDD1 , VDD2, VPD, VGG, and VHOG. 




17 18 19 

Vpd(V) 




I 



Fig. 5. Bias Setting Range of VDD1 , VDD2, VPD. and VGG. 

The shaded section is the recommended operating range. 

7. Vhh, V*h, and Vhl are determined as follows. 




Middle Point 

Fig. 6. Horizontal Transfer Clock Waveform 



- 153 



SONY® 



ICX018CK/ICX021CK 



8. Vpgl, Vpgh, and V*pg are determined as follows. 




Fig. 7. Output Reset Clock Waveform 

Vpgl is defined by the maximum level between Points A and B. Be careful not to allow ringing 
on the low side to be less than OV. 



Drive Pulse Waveform Conditions (ICX018CK) 














Symbol 


tWH 


tWL 


tr 


tf 


Unit 


Condition 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


hUi 




42 






42 






10 






10 




ns 


During scanning 
time 


H*2 




42 






42 






10 






10 




H*1 




6.8 












0.01 






0.01 




US 


During parallel- 
serial conversion 


H*2 





























PG 


10 


42 






42 






10 






10 




ns 


Normally PG=H*i 


V«1/V*2 




61.2 






2.1 






0.1 






0.1 


0.5 


MS 


During scanning 
time 


V*3/V*4 




3.6 






59.6 






0.1 






0.1 


0.5 


V*1/V»3 




19 












1 






1 




During read out 
from sensor 



Drive Pulse Waveform 


Conditions (ICX021CK) 














Symbol 


tWH 


tWL 


tr 


tf 


Unit 


Condition 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


H*i 




43 






43 






10 






10 




ns 


During scanning 
time 


H*2 




43 






43 






10 






10 




H*i 




6.87 












0.01 






0.01 




MS 


During parallel- 
serial conversion 


H*2 





























PG 


10 


43 






43 






10 






10 




ns 


Normally PG=H*1 


V*l/V*2 




61.8 






2.12 






0.1 






0.1 


0.5 


MS 


During scanning 
time 


V*3/V*4 




3.64 






60.2 






0.1 






0.1 


0.5 


V*1/V*3 




19.2 












1 






1 




During read out 
from sensor 




Fig. 8. Pulse Waveform 



- 154 



SONY® 



ICX018CK/ICX021CK 



Operating Characteristics (ICX018CK) 






Ta = 25'C. 


See the Test Circuit. 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test Method 


Condition 


Sensitivity 


Sg 


75 


110 


145 


mV 


1 






Rr 


0.55 


0.8 


1.0 




1 






Rb 


0.35 


0.5 


0.8 




1 




Saturation output voltage 


Vsat 


400 


530 


850 


mV 


2 




Video signal shading 


SV1 




12 


27 


% 


3 




Non-uniformity between 
color signal channels 


ASrg 






11 


% 


4 




ASbg 






11 


% 


4 




Smear 


SM 




0.01 


0.04 


% 


5 




Dark signal 


Vdt 






13 


mV 


6 


Ta = 55°C 


Dark signal shading 


AVdt 






4 


mV 


7 


Ta = 55°C 


Flicker 


F 






6 


% 


8 





Operating Characteristics (ICX021CK) 






Ta = 25°C. See the Test Circuit. 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test Method 


Condition 


Sensitivity 


Sg 


65 


95 


125 


mV 


1 






Rr 


0.55 


0.8 


1.0 




1 






Rb 


0.35 


0.5 


0.8 




1 




Saturation output voltage 


Vsat 


360 


440 


850 


mV 


2 




Video signal shading 


SV1 




12 


27 


% 


3 




Non-uniformity between 
color signal channels 


ASrg 






11 


% 


4 




ASbg 






11 


% 


4 




Smear 


SM 




0.01 


0.04 


% 


5 




Dark signal 


Vdt 






13 


mV 


6 


Ta = 55°C 


Dark signal shading 


AVdt 






4 


mV 


7 


Ta = 55t 


Flicker 


F 






6 


% 


8 





I 



Test Method 

• Test conditions 

1) The device drive conditions in the following measurements should be adjusted to the 
typical values of the DC and clock voltage conditions. (See Fig. 9). 

2) In measurements mentioned below, blemishes should be excluded. Unless specified, the 
optical black level should be the reference for the signal output, and the value measured 
at Point B in Fig. 9 should be used. 

• Definition of standard imaging condition 

Standard imaging condition I : Use pattern box (brightness 706 nt, 3200° K Halogen source) 
at F5.6 with FUJINON lens H6X12.5D (F1.4). CM-500S (1.0 mmt) should be used as an 
IR cut filter. 

Standard imaging condition II : Uniformity of the light source within 2%. The light-source 
color temperature should be 3200° K, and CM-500S (1.0 mmt) should be used as an IR 
cut filter. The quantity of light should be adjusted to the average value of output voltage 
Vs shown in each item. 



- 155 - 



SONY® 



ICX018CK/ICX021CK 



1. Set to the Standard imaging condition I and measure output signals (Sr, Sg, and Sb) in the 
center of the screen for the R, G, and B channels. 

Rr = Sr/Sg Rb = Sb/Sg 

2. Set to the standard imaging condition II, adjust the intensity of light, check anti-blooming, 
then measure the minimum values of each color signal of the R, G, and B channels for the 
whole screen. 

3. After setting up standard imaging condition II, set the pattern box on the entire screen and 
measure the maximum and minimum output voltages of Channels G (Vgmax, Vgmin) adjusting 
Vs to 300 mV. 



_ Vgmax - Vgmin 
ovl — 

Vs 



X100 (%) 



4. In accordance with Method 5, measure non-uniformity of R and B channels in various parts 
of the screen using Channel G as a standard. In measurements adjust the output gain for 
Channels R and B to that for G in terms of the average signal. Measure the maximum and 
minimum values of the difference with G. 

/B 



t~A 




ASrg = (Vr-Vg) max- (Vr - Vg) min x ]QQ (%) 
Vs 

ASbg^ (Vb ~ V9) max J (Vb ~ V9) min X100 (o/o) 
Vs 

5. After setting up standard imaging condition II, set the pattern box on a vertical 1/10 screen. 
Measure the average signal voltage Vs of Channel G and maximum value Vsm of Channels 
R, G, and B of signal voltage during vertical blanking. (Vs = 300 mV, 1/10V method) 




V/10 




Black Level 



SM= -^-X100 (%) 
Vs 

6. Average dark signal at ambient temperature of 55 °C. 

7. Measure maximum and minimum dark signal (Vdmax, Vdmin). 
Blemishes should be excluded. The temperature should be 55 °C. 

A Vdt = (Vdmax - Vdmin) 

8. Measure the signal difference: A Vf between even field and odd field, after setting up 
standard imaging condition II. (Vs = 300 mV) 



F5 



AVf 
Vs 



x 100 (%) 



- 156 



SONY. 



ICX018CK/ICX021CK 




12K4 

levr 
. +1* 



47KJ 31 
* 1 0.47>jF 



CXB 
0026 



CXB 
0026 



iD— 03)— (13)— @ — ©— Qsh- @ — (!§)— V3r 
ICX018CK/ICX021CK 




-OVVH(=VVL+V0V) 



I 



Fig. 9. Test Circuit 
Note) XV1 denotes inverted level of VI. The others are the same. 

Typical Spectral Response (Light source characteristics are not included.) 



15 0.4 




400 



500 600 

Wave Length (nm) 



700 



157 



SONY® 



ICX018CK/ICX021CK 



loz 

591 

h 3 



o 
to 

H 

z 
o 

00 

r- 
O 

X 

u 



ra 
O 



?03 ; 

=01 j 

* I 

39 : 
]bi9 

2909 



L 


E 




: 929 
=029 






; 5 


- 


CM 






= 




^982 
H382 
=9Z2 
rOZ2 
=992 
^092 




2 


3 =C 


— 

c 


00 I 
(O . 
*r . 

CM 
01 










E SI 

Eoi 

— E 

— Z 

— I 

— sss 

HD29 


i c: 


- 


= : 




ro 

CM 
CTl 





>> >> 



Q ^ Q <-"CM ,-i CM CO *t o 

_l -J I C3CJ > > > > Q 

Ll- CO COCO O 

XX o 



158 



SONY® 



ICX018CK/ICX021CK 



cc 

O 
O 

o 

r» 
M 
O 
X 

o 



o 



log I 

,01 = 

Is I 

3 E c 

'005= 

3 c 



XI Q. >> >> 



5EE 

^sze 

llOZE 
EsiE 
= 0IE 



z 


Z $Z 




= 02 




E SI 




E 01 




-e 
-z 




z kz9 


J 


~ 


z 


E029 


- 


- 



W\ 



I 



Q ^ Q ^CM H (M CO *t 

_l _l I C3C3 > > > > 

U. CD CrtW) 

XX 



- 159 



SONY® ICX018CK/ICX021CK 



Handling 

1 . Electrostatic Protection 

It is crucial that static discharge be controlled and minimized. Handle most carefully. 

2. Soldering 

Make sure that the package temperature does not exceed 80°C. Solder dipping in a mounting 
furnace causes broken glass, filter delamination, and other defects. Use a grounded 30W 
soldering iron and solder in less than 2 seconds for each pin. Cool sufficiently when 
reworking or remounting. 

3. Glass surface dust 

Do not touch glass plates. Be careful not to have objects contact glass surface. Clean with 
a cotton bud when the glass surface is stained. Do not use an organic solvent other than 
ethyl alcohol. Store in a special container to prevent dust and dirt. To prevent dew 
condensation, preheat or precool when moving to a room in which temperature difference 
is great. 

4. ROM for blemish compensation and correlated double sampling. 

This device is shipped in a special container together with ROM. Be most careful about 
combination when remounting. 

5. Care must be taken to avoid exposure to strong light for a long time. 

6. Use CX20180 for V clock driver. 



- 160 



sony. IU018CK-AB/IU021CK-AB 



CCD Imaging Blocks for Color Camera 



Description 

IU018CK-AB and IU021CK-AB are solid state imaging blocks developed for color video cameras. They 
incorporate an image correction optical filter (Optical crystal low pass filter, infrared cut filter) indispensable 
for solid state imaging devices. 

These blocks can easily be attached to the rear of a lens or the mount of an interchangeable lens to provide 
a lightweight, compact imaging system. 



Pin Configuration (Top View) 



40.8 Ma * 




Vj<4 


© 


© 


NC 


V03 


© 


® 


NC 


V02 


© 


© 


H01 


SUB 


© 


© 


H02 


Vjrfl 


© 


© 


HOG 


SG 


© 


© 


PG 


OFD 


© 


© 


PD 


ED 


© 


© 


Vss 


Vdoi 


© 


© 


VGG 


VDD2 


© 


(ji 


Vout 



Fig. 1 



Pin Description 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V*4 


Vertical register transfer clock input 


11 


Vout 


Signal output 


2 


V*3 


Vertical register transfer clock input 


12 


Vgg 


Output amplifier gate bias 


3 


V*2 


Vertical register transfer clock input 


13 


Vss 


Output amplifier source bias 


4 


SUB 


Substrate 


14 


PD 


P recharge drain bias 


5 


V^i 


Vertical register transfer clock input 


15 


PG 


Output reset clock input 


6 


SG 


Sensor bias 


16 


HOG 


Horizontal register read out control 
bias 


7 


OFD 


Anti-blooming bias 


17 


H*2 


Horizontal register transfer clock 
input 


8 


ED 


Edge drain bias 


18 


H*l 


Horizontal register transfer clock 
input 


9 


Vddi 


Supply voltage 


19 


NC 




10 


VDD2 


Supply voltage 


20 


NC 





161 - 



SONY® 



IU018CK-AB/IU021CK-AB 



Package Outline (Unit: mm) 










[ 


- i , 






t ■■ 

<M 












. a 




=s»=^ 





Fig. 2 



- 162 



SONY® 



IU01 8CK-AB/IU021 CK-AB 



Configuration and Optical Characteristics 



Item 


Ratings 


Unit 


Remark 


Appearance, size, 
attachment 


See the Package 

Outline (Fig. 2) 






Optical axis 


Within the <£11.2 circle with 
the Ref. A center are the effec- 
tive elements. 


mm 


Fig. 2 

Standard location A 


Image rotation 


Within ±1 


deg 


(£2.1 spot 


Back focus 


1.74±0.3 


mm 


(In AIR) 

Fig. 2 Standard surface B 


Tilt 


60 


ixm 


Fig. 2 Standard surface B 


Optical thickness 


9.75 


mm 


BK-7 equivalent 

(including optical filter assembly and optical 

parts of CCD) 


Optical filter 


Four-layer laminated type 






Spectral sensitivity 
characteristics 


See Fig. 3 






Weight 


24 


g 





Note) See the specifications of ICX018CK and ICX021CK for Imaging Characteristics, Electrical Characteris- 
tics and Absolute Maximum Ratings. 

Spectral sensitivity characteristics example 



0.9 
0.8 
0.7 






G /\ 1 


















B 










0.6 
0.5 
0.4 
0.3 
0.2 
0.1 
0.0 






/ 


\ R 











































I 



Wave length (nm) 
(Fig. 3) 



Environmental Characteristics 



Item 


Condition 


Requirements 


Vibration 


7G, 10 to 30Hz, 300sec sweep, each 
15min for x, y, z directions 


The above structure satisfies optical 
characteristics. 


Impact 


80G, in 6 directions 


Low temperature durability 


-30°C, 240 hours 


High temperature durability 


80°C, 240 hours 


Heat cycle 


-30-C to25°Cto80°C ^ 
30min to 5min to 30min 


High temperature and 
high humidity durability 


60°C, 95%, 240 hours 



- 163- 



SONY. 



ICX022AK-3 



Interline-type CCD Solid Image Sensor 



Description 

ICX022AK-3 is an interline-type CCD solid imaging 
device designed for color video cameras. 
Effective pixels number 768 horizontally and 493 
vertically. 

Color filters incorporated Ye, G and Cy are vertical 
stripe filters of high resolution and high sensitivity. 

The device employs the field integration system to 
obtain a high resolution. 

Element Structure 

• Interline type CCD image sensor 

• Effective pixels: 768 (H) x 493 (V) 

• Image size: 2/3 inches (8.8 mm (H) x 6.6 mm (V)) 

• Color filters (on-chip): Ye, G, Cy vertical stripe 
filters 

• Field integration system 

• Electronic shutter function 

• Anti-blooming function 

• Chip size: 10.0 mm (H)x 8.2 mm (V) 

• Unit Cell size: 1 1 .0 urn (H) x 1 3.0 |xm (V) 

• Effective optical black 
Horizontal: Front 5pixels 

Back 45 pixels 

Vertical: Front 16 pixels 

Back 4pixels 

• Dummy bits: horizontal 22-bits, vertical 1-bit 
(even fields only) 



Package Outline 



Unit: mm 



20 pin DIP (Ceramic) 



2-0 2.5 



Q.3% , 



rr4 





\ 2.0*2,5 (»'oQ 
A i effective element* picture center 



ji 



— H 



493 



Pin 1 1 side -* 




Pin 1 side 



Fig. 1 Optical black configuration 



70609A-YA 



- 164- 



SONY® 



ICX022AK-3 



Pin Configuration and Description 
(Top View) 



o o 



v*« 


T 






@ GNO 


v*>» 


r) 






® N* 


V*l 


§ 






© ►*« 


sue 


JT 






© Vu 


GNO 


(fi. 






© PG 


V4.1 


® 






® TO 


Vl 


(t 






® GNO 


NC 


W 






@ Vtl 


NC 


(?) 






Qz) v«« 


VDO 


(s 


O 


o 


m) voui 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V<|>4 


Vertical register transfer clock 


11 


Vout 


Signal output 


2 


V(|>3 


Vertical register transfer clock 


12 


Vgg 


Output amplifier gate 


3 


V<(>2 


Vertical register transfer clock 


13 


Gss 


Output amplifier source 


4 


SUB 


Substrate (OFD) bias 


14 


GND 


GND 


5 


GND 


GND 


15 


PD 


Pre-charge drain bias 


6 


V<>1 


Vertical register transfer clock 


16 


PG 


Output reset clock 


7 


Vl 


Protection transistor bias 


17 


Vl 


Protection transistor bias 


8 


NC 




18 


H<|>2 


Horizontal register transfer clock 


9 


NC 




19 


H<J>1 


Horizontal register transfer clock 


10 


Vdd 


Output amplifier drain supply 


20 


GND 


GND 



I 



Imaging Device Function Block 




PD PG 



■O ® ® ®~ 

Vl H+2 H<H GND 



s)GND 



*Note) — I I : Photo Sensor 



- 165- 



SONY® 



ICX022AK-3 



Absolute Maximum Ratings 



Item 



SUB-GND 



Vdd, PD, Vout, Vss-GND 



Vdd, PD, Vout, Vss-SUB 



Horizontal and vertical transfer clock inputs - GND 



Horizontal and vertical transfer clock inputs - SUB 



Potential difference between vertical transfer clock inputs 



Potential difference between horizontal transfer clock inputs 



Hc>i, H(|)2 - V(t)4 



PG, Vgg - GND 



PG, Vgg - SUB 



Vl-SUB 



Pins other than GND, SUB and Vl-Vl 



Storage temperature 



Operation guarantee ambient temperature 



Ratings 



-0.3 to +55 



-0.3 to +20 



-55 to +10 



-15 to +20 



-65 to +10 



+15 



+17 



-17 to +17 



-10 to +15 



-55 to +10 



-65 to +0.3 



-0.3 to +27 



-30 to +80 



-10 to +55 



Unit 



°C 



Remarks 



Note 1 



Note 1 



Note 2 



Note 1 



Note) 1 . This imaging device consists of an N substrate P-Well structure where a protection transistor is 

connected to each pin accordingly. If a voltage exceeding 10 V is applied to pins other than Vl against 
the SUB pin, a punch through current will flow. Since a series resistance Rl is located between each 
pin and SUB, the device will withstand destruction through any rush voltage over 10 V. 
The series resistance Rl must be more than 1 kQ between Vp-p and SUB, more than 500 Q between 
Vout and SUB and more than 5kQ between Vss or PD and SUB. The series resistance between other 
pins (except Vl and GND) and SUB must be more than 5 kQ. 



© Vdd, PD, Vout and Vss pins 



Pins other than © (except Vl and GND) 




SUB » 



Every pin °- 
Vl 



GNDo- 



SUBo- 



1 



Fig. 2 Equivalent circuit 



2. In case of clock width <1 [is and clock duty factor <0.1 %, up to 27 V is guaranteed. 



- 166 



SONY® 



ICX022AK-3 



Bias Conditions 



Item 


Symbol 


Min. 


Typ. 


Max 


Unit 


Remarks 


Supply voltage of output circuit 


Vdd 


14.55 


15.0 


15.45 


V 




Vpd 


14.55 


15.0 


15.45 


V 


Notel 


Vgg 


1.6 


2.0 


2.4 


V 




Vss 


Ground with a 390 Q resistance 


±5% 


Substrate voltage adjustable range 


VSUB 


9 




19 


V 


Note 2 


Regulation range after substrate 
voltage adjustment 


VSUB 


-3 




3 


% 




Protection transistor bias 


Vl 


To be the vertical transfer clock low-level clamp bias 



DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output circuit current 


Idd 




5.0- 




mA 


Note 3 


Input current 


||N1 






1 


uA 


Note 4 


llN2 




. 


10 


HA 


Note 5 



Note) 1 . Vpd and Vdd must have the same voltage. 

2. Indication of the substrate voltage (Vsub) set value: 

The set value is indicated on the rear of the imaging device by a code. Adjust to obtain the indicated 

voltage at the SUB pin. 

□ □ 

Vsub code - Two digit indication 



t 



t 



I 



Integral part Decimal part 



The integral codes correspond to the following actual values 








Integral codes 


9 


A 


B 


C 


D 


E 


F 


G 


H 


I 


J 


Actual values 


9 


10 


11 


12 


13 


14 


15 


16 


17 


18 


19 



EX.) F5->15.5(V) 

3. Ground Vss with a 390Q resistance. 

4. 1) Current flowing to the ground when a voltage of 20 V is applied to Vdd, PD, Vout, Vss and SUB pins. 

Test ground all the pins other than those under test. 

2) Current flowing to the ground when a voltage of 25 V is applied to V<|>i, V<|>2, V<|>3, V<K H<|>1 and H<(>2 
pins in the order. Apply pin a voltage of 25 V to the SUB pin and ground pins other than those under 
test. 

3) Current flowing to the ground when a voltage of 1 5 V is applied to PG and Vgg pins in the order. 
Apply a voltage of 15 V to the SUB pin and ground pins other than those under test. 

4) Current flowing to the ground when Vl pin is grounded, GND and SUB pins are open and a voltage 
of 27 V is applied to other pins. 

5. Current flowing to the ground when a voltage of 55 V is applied to the SUB pin. In this case ground pins 
other than those under test. 



167- 



SONY® 



ICX022AK-3 



Clock Voltage Conditions 
Clock voltage 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Read clock voltage 


Vvt 


13.0 




15.0 


V 


Note 1 


Vertical transfer clock voltage 


VvHH 






1.3 


V 


Note 2 


VVH 


-0.5 




0.7 


V 


V»v 


8.0 






V 


VVLL 


-10.5 






V 


Horizontal transfer clock voltage 


Vhhh 






5.2 


V 


Note 3 


Vhl 


-3.0 




-1.7 


V 


V*H 


5.2 




8.0 


V 


Vhll 


-3.0 






V 


Output reset clock voltage 


Vpgl 









V 


Note 4 


V*PG 


7.0 




13.0 


V 


Substrate clock voltage 


V«SUB 


23.0 




27.0 


V 


Note 5 



Clock capacitance 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Vertical transfer clock - GND 


C*v 




5000 




PF 




Capacitance between vertical transfer 
clocks 


CfW 




1500 




pF 




Horizontal transfer clock - GND 


C*H 




180 




pF 




Capacitance between horizontal transfer 
clocks 


C*HH 




50 




pF 




Output reset clock - GND 


CifPG 




10 




PF 




Substrate clock - GND 


C«SUB 




500 




PF 





H+t- 



C+HH 

1 " 1 



-H+2 



mT mf 



C4h 



Fig. 4 Equivalent circuit of horizontal transfer clock capacitance 



- 168 



SONY® 



ICX022AK-3 



Note) 1 . Read clock voltage 

1 ) The symbol 'V expresses the voltage level while the read clock "Vt" of the vertical transfer clocks 
("V((>i" and "V<|)2") is set. The maximum value in the read clock waveform is expressed as "<|>h". 

2) The period in which the voltage level becomes (<|>h - <|>l)/2 is expressed as "tsr". The voltage levels 
at "tsr/2" are expressed as "Vn" (at V<|>i) and "Vt 3 " (at Vfa). The smaller of "Vn" and "Vre" is 
defined as the read clock voltage "Vvt". 



VT1.VT2 




♦ L=V+i,y»s LEVEL 



2. Vertical clock voltage (Refer to Fig. 6) 

T = 559 ns (with a horizontal driving frequency of 4 fsc) 

1 ) Definition of the vertical transfer clock amplitude 

Level 2T after the rising edge of "V^" is expressed as "VW. 
Level T after the falling edge of "V<)>r is expressed as "Vib". 
Level 2T after the rising edge of "VV is expressed as "W. 
Level T after the falling edge of "VV is expressed as "VW. 
Level 2T after the rising edge of "V<|)i" is expressed as "Via". 
Level T after the falling edge of "V<|)3" is expressed as "Vsb". 
Level 4T after the rising edge of "V<|>2" is expressed as "V2a". 
Level 3T after the falling edge of "V<t>4" is expressed as "V»b". 

V<(>2 level T after the falling edge of "V<|>i" is expressed as "V2c". 
V<j>3 level T after the falling edge of "V<|)2" is expressed as "Vac". 
V<|)4 level T after the falling edge of "V<j>3" is expressed as "Vtc". 
V<)>1 level 3T after the falling edge of "V<t>4" is expressed as "Vic". 

A31 =(V3A + V 2C )/2-VlB 

A42 = (Vaa + V 3 c) / 2 - V 2 B 
A13 = (Via + V4c)/2-V 3 b 
A24 = (V 2 a + Vic) / 2 - V4B 

The minimum value of these is defined as the vertical transfer clock amplitude "V<t>v". 

2) The maximum value from Via, V>a, V3a, and Via, is defined as the high level Vvh of the clock. 

3) The minimum level in a waveform which includes the vertical clock coupling is expressed as "Vvu." 
"Vvhh" expresses the maximum level except in the period where read clock Vt is applied (in V<|>1 
and Vc|>3only). 



I 



169 



SONY® 



ICX022AK-3 



|-T*1 




Fig. 6 Vertical transfer clock waveform 

T = 559ns (with a horizontal driving frequency of 4 fsc) 

3. Horizontal transfer clock voltage 

1 ) For the horizontal transfer clocks "H<|)i" and "H<|)2", the low-level period is expressed as "thl" and 
the high-level period is expressed as "thh". The symbol "tho" expresses the overlap period of "thl' 
and "thh". 

2) The low level at which "thl", "thh" and "tho" satisfy the following time duration is expressed as 
"Hib" and "H2b". 

And the high level is expressed as "Hia" and "H2A" 

thl > 10 ns, thh > 10 ns, tho > 5 ns 

A 21 = Hia - H 2B 
A12 = H 2 a-Hib 

The smaller of A21 and A12 is defined as the horizontal transfer clock amplitude "V<|>h". The low 
level at that point is expressed as "Vhl". 

3) The minimum level in the waveform which contains the coupling of the horizontal transfer clocks 
"H<t>i" and "Hfo" is expressed as "Vhll" and the minimum level is expressed as "Vhhh". 









\ / sH+2 






H2A , 












1 A - 


"\ / 






thh 


l / 


Ml 


J2I 




tho 


tho 




/ \ r •* 


1 


thl 


1 \ 


-H2B 


Vhll- 


\ 






\^- > ' v -H41 





Fig. 7 Horizontal transfer clock waveform 



170- 



SONY® 



ICX022AK-3 



4. Output reset clock voltage 

1 ) The low level of the output reset clock is to be the GND in the circuit. 

2) The amplitude of the output reset PG clock "V<|)pg" is defined as the maximum value of the 
amplitude which provides a high level period over 1 ns. 



More than 1 ns 



High level 



Low level 




V<|>PG 



* V<|>PGL 



Fig. 8 Waveform of PG clock 



5. Substrate clock voltage 

1 ) Substrate voltage is expressed as tyl, and the substrate clock waveform maximum value as <|>H. 

2) The period where voltage level turns to (<))H-(|)L)/2 is expressed as tsr. The difference between <|>L 
and voltage level at tsr/2 is defined as the substrate clock voltage V<t>SUB. 

Driving Clock Waveform Conditions 

1 . Definition of 4>h (1 00%) and <|>l (0%) 

1 ) For the horizontal transfer clocks (H<))1 , H(J>2), output reset clock (PG<t>) and vertical transfer clocks (V<j>i , 
V<|>2, V<|>3, V<|>4), the maximum value in the clock waveform which includes no coupling is expressed as 
"<|>h" and the minimum value is expressed as '>.". 

2) For the read clock (Vt), the maximum value in the clock waveform is expressed as "<|>h"."<|>l" expresses 
the voltage level while the read clock (Vt) of the vertical transfer clocks (V<>1, V<|>2) is applied. 

3) For the substrate clock (SUB<t>), the maximum value in the clock waveform is expressed as 'V and the 
substrate voltage (Vsub) as 'V'. 

2. Standard driving clock conditions (Typ.) 



I 



Horizontal drive frequency 


: 14.32 MHz 








Clock 
(Symbol) 


twh 


twl 


tr 


tf 


Unit 


Remarks 


HiJ»i 


18 


33.7 


10 


8 


ns 


Imaging period 


H<|>2 


18 


33.7 


10 


8 


H<t>i 


4.9 




0.01 


0.01 


\is 


Parallel-serial converting period 


H<|>2 




4.9 


0.01 


0.01 


<|>PG 


12 


53.7 


2 


2 


ns 




V>/V<t>2 


61.6 


1.6 


0.1 


0.1 


^s 


Imaging period 


V<|)3/V<|)4 


2.8 


60.45 


0.05 


0.1 


V4* 


2.4 




0.2 


0.1 


Reading period 


SUB<|) 


1.0 




0.08 


0.1 


^s 


Electron drained into substrate period 



- 171 



SONY® 



ICX022AK-3 



fL(0%) 




Fig. 9 Clock waveform 



Imaging Characteristics 














(See Fig. 10.) 
Ta=25°C 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Testing method 


Remarks 


Sensitivity G 


sg 


130 


170 




mV 


1 




Sensitivity ratio 


Ye 


Ry 


1.50 


1.70 


1.90 




1 




Cy 


Re 


1.28 


1.40 


1.60 




1 




Output saturation signal 


Vsat 


600 






mV 


2 • 


Note 


Blooming margin 




1000 






times 


3 




Smear 


Smr 




0.007 


0.015 


% 


4 


Note 


Video signal shading 


Svg 






25 


% 


5 




Uniformity in video signal 
channels 


ASrg 






10 


% 


6 




ASdg 






10 


% 


6 




Dark signal output 


Vdt 






2 


mV 


7 


Ta=55°C 


Dark signal shading 


AVdt 






1 


mV 


8 


Ta=55°C 


Flicker 


Ye 


Fy 






5 


% 


9 




G 


Fg 






5 


% 


9 




Cy 


Fc 






5 


% 


9 





Note) Saturation signal and blooming margin are guaranteed only when the substrate voltage has been set to 
the voltage indicated on the back of the imaging device. 



- 172- 



SQ1STY. . ICX022AK - 3 

Test Methods 

Conditions j ^ L ,_. 

(1) The conditions required to drive the device through the following tests are covered by the bias conditions 
and the clock voltage conditions. The test circuit shown in Fig. 1 1 is used for evaluating and testing the 
chdrdct6ristics> 

(2) Blemish are excluded from the following tests and the signal output is based on the optical black level 
unless otherwise specified test the value obtained at the output test point becomes the test value. 

Definition of the standard imaging conditions 

(1 ) Standard imaging condition I: Shoot the PTB-1 00 pattern box (luminance 706 Nit, Color temperature 
3200°K) with no pattern, using a FUJINON H6 x 12.5D (F1 .4) lens at F5.6. Use the CM-500S (1 .Ommt) 
filter to cut off infrared rays. 

(2) Standard imaging condition II: Shoot a light source (color temperature 3200°K) which provides a uniform 
brightness within 2% over the whole screen. 

For infrared cut-off filter, use the CM-500S (1 .Ommt) 

1 . Set to standard imaging condition I and test signal voltages (Sy, Sg, Sc) of Ye, G, Cy channels at the center 
of the screen. 

Ry = Sy/Sg Rg=Sc/sg 

2. Set to standard imaging condition II and adjust the light intensity applied to Ye channel to about ten times the 
intensity obtained at a signal voltage of 200 mV. Then obtain the minimum value of the signal voltages at 
channels Ye, G and Cy respectively over the whole screen. 

3. Set to standard imaging condition II and adjust the hight intensity applied to Ye channel to about 1 000 times 
the intensity obtained at a signal voltage of 200 mV. Check that neither blooming is generated nor the 
vertical register saturated. 

4. Set to standard imaging condition II and adjust the light intensity so that the signal voltage of G channel 
(Vsg) becomes 200 mV. Then, turn Vroff and obtain the maximum value of the signal voltage "Vsm" after 
stopping the horizontal resistor 50H at the effective pixels without depending Ye, G, Cy channels. 

Smr= x — x x 100(%) 

Vsg 50 10 

(Converted into 1/10V system) 

5. Set to standard imaging condition II and test the signal voltage of G channel to obtain maximum (Vg max) 
and minimum (Vg min) values. 

The light intensity is adjusted so that the average value of the signal voltage (Vg average) becomes about 
200 mV. 

Vg max-VG min 

Syg= — x100(%) 

Vg average 



- 173- 



SONTY® ICX022AK-3 

6. Following test 5, test the signal voltage of each channel. Calculate the output gains of the red and blue 
signals (Ar and Ab) from the mean values of the signal voltages of Ye, G and Cy channels ( W mean, 
Vcmean, Vcmean). Then arrange the mean value of the red and bule signal voltage (VRmean and VBmean) 
so that they become equal to "VGmean". Then measure the differences between the G channel signal 
voltage (VG) and the R channel as well as B channel signal voltage (VR as well as VB) to obtain the 
maximum and minimum values. 

VYmean - VGmean 
Ar = 



Ab = 



VGmean 
VCmean - VGmean 



VGmean 

VR = (VY - VG)/Ar VB = (VC - VG)/Ab 

(VR-VG)max (VR-VG)min 

ASrg= x100% 

y VGmean 

(VB-VG)max - (VB-VG)min 

ASbg = — x 100 % 

y VGmean 

7. Measure the mean voltage of the dark current signal based on the horizontal free-transfer level in a light- 
shaded condition with an ambient temperature of 55°C. 

8. Following measurement 7, test the dark current signal voltage to obtain the maximum (Vdmax) and 
minimum (Vdmin) values. Spot defects are ignored in this test. 

AVdt = (Vdmax - Vdmin) 

9. Set to standard imaging condition II and test the signal voltage difference "Vdr" between the fields of each 
channel. The light intensity is adjusted so that the average value of the G channel signal output (VG 
average) becomes about 200mV. 

The average values of Ye and Cy channels are expressed as "VY average" and "VC average", respectively. 

Vdri 

Fi= x1000(%) 

Vi average . = Q> Q 



174 



SONY® 



ICX022AK-3 



Electrical Characteristics Test Circuit 



Output test 
point 




I 



'OK < ^ZOATv 



XSUBjf 



SUB 
driver 



10(1 




1 



-ilVil 



PG 
driver 



H 
driver 



-Vpgh 

-XPG 

-Vpgl 
-Vhh 

(Vhl+VjZSh) 
-XH2 
-XH1 

-Vhl 



V 
driver 



-W-V0V 

-XV4 
-XV3 
-XSG1 



-VT 
-Vl 



10)1 

-)r±- 



V 
driver 



-W— V0V 

-XV2 
—XVI 
-XSG2 



i[?tf K>0K 



-VT 

-Vl 



Fig.10 



I 



Spectrum Sensitivity Characteristics (Typical example, excluding illuminant characteristics) 



9- -6 



































YeN. 






/Cy 


/ G 
































































\ 





















Wave length [nm] 



- 175 - 



SONY® 



ICX022AK-3 



L 



o 


















10 


^ 


fO 


<\l 


«- 




- 




- 



















w 



> > > > 



I > > > > 



» Q 



- 176- 



SONY® 



ICX022AK-3 



Sensor Read clock Timing Chart 



i r 



J L 



(ODD FIELD) 



Charge Drain Clock Timing Chart 



<EVEN FIELD) 



Unit: us 



I 



Unit: ^s 



177- 



SONY® 



ICX022AK-3 



Handling Instructions 

1 . On electric screening 

To prevent damage to the CCD image sensor by static electricity, handle as follows. 

a) Either handle the device with bare hands, or use antistatic gloves and clothes. Conductive shoes are 
also required. 

b) Use a ground lead when directly touching the device. 

c) Cover the floor and working table with a conductive mat or equivalent to avoid static electricity. 

d) Discharge using ionrzed air is recommended. 

e) To ship the mounted boards, use cartons with antistatic properties. 

2. On soldering 

a) Make sure the package temperature does not exceed 80°C. 

b) Solder-dipping of DIP in a mounting furnace may break glass. Use a grounded 30 W soldering iron a 
each pin for less than 2 seconds. When adjusting or removing soldered parts, let the CCD cool 
sufficiently. 

c) Do not use any solder-aspirating equipment to remove the imaging device. Should an electric solder- 
aspiration device be used, use only a device of the zero-cross type control system and be sure to 
ground the controller. 

3. On contamination 

a) Keep the operation room clean (Class 1 000 will be expected). 

b) Do not touch the glass surface avoid contact with foreign objects. Blow off any dust the surface with a 
blower. (Ionized air is recommended to blow off any object sticking through static electricity.) 

c) Wipe off grass spots with an applicator moistened with ethanol. Be careful not to scratch the surface. 

d) To eliminate contamination, store the device in an exclusive case. During transportation minimize the 
difference in temperatures between locations to avoid moisture condensation. 

e) When a protection tape has been affixed for shipment, remove it just before use after applying 
appropriate antistatic measures. Do not reuse the removed tape. 

4. Do not subject the device to light sources for extended periods. If a color element is subjected to strong 
light ray for an extended period, the color filter will be discolored. (Store the device in a dark place.) 

5. Usage or storage of the device in high temperature or high humidity may seriously affect the performance. 

6. The CCD image sensor is a high-precision optical part, that should not be subjected to mechanical shocks. 

7. System data write complete ROM (address for Blemish compensation included) 

A number of System data write complete ROM equal to the number of ICX022AK-3's is attached. ROM's 
with blemish compensation address written bear a serial No. sticker. Use in pair with ICX022AK-3 bearing 
the same serial No. 



- 178 



SONY. 



ICX024AK-3 



Interline-type CCD Image Sensor 



Description 

ICX024AK-3 is an interline-type CCD image 
sensor designed for color video cameras. 

Effective picture elements number 756 horizontally 
and 581 vertically. 

Complementary color filters Ye, G and Cy are 
vertical stripe filters of high resolution and high 
sensitivity. 

This chip features a field integration read out 
system and an electronic shutter with variable 
charge-storage time. 



Element Structure 

• Interline type CCD image sensor 

• Number of effective pixels: 756 (H) x 581 (V) 

• 2/3 inch optical format (Effective sensing area: 
diagonal 10.49 mm) 

• Color filters (on-chip): Ye.G.Cy vertical stripe 
filters 

• Field integration read out system 

• Electronic shutter function 

• Anti-blooming function 

• Chip size: 10.0 mm(H) x 8.2 mm(V) 

• Unit Cell size: 1 1 .0 mm(H) x 1 1 .0 mm(V) 

• Effective optical black 

Horizontal: Front 5 pixels 

Back 55 pixels 
Vertical: Front 1 9 pixels 

Back 6 pixels 

• Dummy bits: horizontal 22-bits, vertical 1-bit (even 
fields only) 

Pin 11 side 



Package Outline 



Unit: mm 



20 pins DIP (Ceramic) 



2-02.5 



0.35. 





itfvctiva «l«m«nttr picture canter 





Pin 1 side 



I 



Fig. 1 Optical black configuration 



80303A-YA 



179 



SONY® 



ICX024AK-3 



Pin Configuration and Description 
(Top View) 



o o 



«*« 


(t 






(20) GNO 


V»3 


(2) 






® "♦* 


V + 2 


(3) 






® H*2 


sue 


(*. 






® Vl " 


GND 


(fi) 






® PG 


V+l 


® 






@ PD 


Vl 


C 7 > 






(w) GNO 


NC 


w 






@ Vfl 


NC 


(9^ 






(3) Voo 


VOO 


® 


O 


O 


(n) Vou 



No. 



10 



Symbol 



V<)>4 



V(j>3 



V<)2 



SUB 



GND 



V«|»1 



Vl 



NC 



NC 



Vdd 



Description 



Vertical register transfer clock 



Vertical register transfer clock 



Vertical register transfer clock 



Substrate (OFD) bias 



GND 



Vertical register transfer clock 



Protective transistor bias 



Supply voltage 



No. 



11 



12 



13 



14 



15 



16 



17 



19 



20 



Symbol 



VOUT 



Vgg 



Vss 



GND 



PD 



PG 



Vl 



H^2 



H<t>l 



GND 



Description 



Signal output 



Output amplifier gate 



Output amplifier source 



GND 



Pre-charge drain bias 



Output reset clock 



Protective transistor bias 



Horizontal register transfer clock 



Horizontal register transfer clock 



GND 



Imaging Device Function Block 




*NoteH 



- 180 



SONY® 



ICX024AK-3 



Absolute Maximum Ratings 



Item 


Ratings 


Unit 


Remarks 


SUB - GND 


-0.3 to +55 


V 




Vdd, PD, Vout, Vss - GND 


-0.3 to +20 


V 




Vdd, PD, Vout, Vss - SUB 


-55 to +10 


V 


Note 1 


Horizontal and vertical transfer clock inputs - GND 


-15 to +20 


V 




Horizontal and vertical transfer clock inputs - SUB 


-65 to +10 


V 


Note 1 


Potential difference between vertical transfer clock inputs 


15 


V 


Note 2 


Potential difference between horizontal transfer clock inputs 


17 


V 




H<|)1, H<)2 - V<|)4 


-17 to +17 


V 




PG, Vgg -GND 


-10 to +15 


V 




PG, Vgg - SUB 


-55 to +10 


V 


Note 1 


Vl - SUB 


-65 to +0.3 


V 




Pins other than GND, SUB and Vl - Vl 


-0.3 to +27 


V 




Storage temperature 


-30 to +80 


°C 




Operation guarantee ambient temperature 


-10 to +55 


°C 





Note) 1 . This imaging device consists of an N substrate P-Well structure where a protection transistor 
is connected to each pin accordingly. If a voltage exceeding 10 V is applied to pins other 
than Vl against the SUB pin, a punch through current will flow. Since a series resistance Rl 
is located between each pin and SUB, the device will withstand destruction through any rush 
voltage over 10 V. The series resistance Rl must be more than 1 kft between Vp-p and 
SUB, more than 500 £2 between Vout and SUB and more than 5 k£2 between Vss or PD and 
SUB. The series resistance between other pins (except Vl and GND) and SUB must be 
more than 5 Q. 



I 



1 ) Vdd, PD, Vout and Vss pins 



2) Pins other than 1) (except Vl and GND) 



Every pin <> 
Vl 



^ 



GND o- 



SUB o- 



Every pin » 

Vl 
GND » 



r 



SUB o~ 



P 



"1 



Fig. 2 Equivalent circuit 



2. In case of clock width <10 lis and clock duty factor <0.1%, up to 27 V is guaranteed. 



181 



SONY® 



ICX024AK-3 



Electrical Characteristics 
Bias conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Supply voltage of output circuit 


Vdd 


14.55 


15.0 


15.45 


V 




Vpd 


14.55 


15.0 


15.45 


V 


Note 1 


Vgg 


1.6 


2.0 


2.4 


V 




Vss 


Ground with a 390 Q resistance 


±5% 


Substrate voltage adjustable range 


VsUB 


9 




19 


V 


Note 2 


Regulation range after substrate voltage 
adjustment 


VsUB 


-3 




3 


% 




Protection transistor bias 


Vl 


To be the vertical transfer clock low-level clamp bias 



DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output circuit current 


Idd 




5.0 




mA 


Note 3 


Input current 


llNl 






1 


liA 


Note 4 


Iin2 






10 


HA 


Note 5 



Note) 1. Vpd and Vdd must have the same voltage. 

2. Indication of the substrate voltage (Vsub) set value: 

The set value is indicated on the rear of the imaging device by a code. Adjust to obtain the 
indicated voltage at the SUB pin. 

Vsub code - Two digit indication □ □ 

t t 

Integral part Decimal part 

The integral code correspond to the following actual values: 



Integral codes 


9 


A 


B 


C 


D 


E 


F 


G 


H 


I 


J 


Numerical value 


9 


10 


11 


12 


13 


14 


15 


16 


17 


18 


19 



EX.) F5 -> 15.5 (V) 

3. Ground Vss with a 390 Q. resistance 

4. 1) Current flowing to the ground when a voltage of 20 V is applied to Vdd, PD, Vout, Vss 

and SUB pins. Test ground all the pins other than those under test. 

2) Current flowing to the ground when a voltage of 20 V is applied to V<j)i, V<(>2, V<|>3, VcK 
H<))1 and H«|»2 pins in the order. Apply pin a voltage of 20 V to the SUB pins and ground 
pins other than those under test. 

3) Current flowing to the ground when a voltage of 15 V is applied to PG and Vgg pins in 
the order. Apply a voltage of 15 V to the SUB pin and ground pins other than those 
under test. 

4) Current flowing to the ground when Vl pin is grounded, GND and SUB pins are open and 
a voltage of 27 V is applied to other pins. 

5. Current flowing to the ground when a voltage of 55 V is applied to the SUB pin. In this 
case ground pins other than those under test. 



182- 



SONY® 



ICX024AK-3 



Clock Voltage Conditions 
Clock voltage 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Read clock voltage 


VVT 


13.0 


5.0 


15.0 


V 


Note 1 


Vertical transfer clock voltage 


VvMM 






1.3 


V 


Note 2 


VVM 


-0.5 




0.7 


V 


V«v 


8.0 






V 


VVLL 


-10.5 






V 


Horizontal transfer clock voltage 


Vmmh 






5.2 


V 


Note 3 


Vhl 


-3.0 




-1.7 


V 


V*H 


5.2 




8.0 


V 


Vhll 


-3.0 






V 


Output reset clock voltage 


Vpgl 









V 


Note 4 


VoPG 


7.0 




13.0 


V 


Substrate clock voltage 


V4SUB 


23.0 




27.0 


V 


Note 5 



Clock capacitance 



Item 


Symbol 


Min. 


Typ. 


Max. | Unit 


Remarks 


Vertical transfer clock - GND 


CoV 




5000 




pF 




Capacitance between vertical transfer 
clocks 


CoVV 




1500 




pF 




Horizontal transfer clock - GND 


C(t>H 




180 




pF 




Capacitance between horizontal transfer 
clocks 


C<t>HH 




50 




PF 




Output reset clock - GND 


CfcPG 




10 




pF 




Substrate clock - GND 


CeSUB 




500 




pF 





H<|»1 



C0HH 

rz 1 — r 



1 



C(j)H 



H(|)2 



C(|)H 



Fig. 4 Equivalent circuit of horizontal transfer clock capacitance 



- 183 



SONY 9 ICX024AK-3 

Note) 1. Read clock voltage 

1) the symbol "<K" expresses the voltage level while the read clock "Vt" of the vertical 
transfer clocks ("V(|>i" and "v>2") is set. The maximum value in the read clock waveform 
is expressed as "<)>h". 

2) The period in which the voltage level becomes (<|>h - <|>l)/2 is expressed as "tsr". The 
voltage levels at "tsr/2" are expressed as "Vn" (at Vol) and "Vrs" (at Vo3). The smaller 
of "Vn" and "Vt 3 " is defined as the read clock voltage "VVr". 



VT!, VT2 




<j>H (0H - ((>l)/2 

<|>l = V<J>i, V<>3, Level 



Fig. 5 Read clock waveform 



2. Vertical clock voltage (Refer to Fig. 6) 

T = 564 ns (with a horizontal driving frequency of 1 4.19MHz) 

1) Definition of the vertical transfer clock amplitude 

Level 2T after the rising edge of "V<>3" is expressed as "VW. 
Level T after the falling edge of "V<|>r is expressed as "Vib". 
Level 2T after the rising edge of "V<)>4" is expressed as "V4a". 
Level T after the falling edge of "V<)>3" is expressed as "Vzb". 
Level 2T after the rising edge of "V<>i" is expressed as "Via". 
Level T after the falling edge of "V<|)3" is expressed as "Vsb". 
Level 4T after the rising edge of "V<t>2" is expressed as "Vza". 
Level 3T after the falling edge of "V^" is expressed as "V4b". 

V<|>2 Level T after the falling edge of "V<|>r is expressed as "Vjc". 

V<)>3 Level T after the falling edge of "V<|»2" is expressed as "Vac". 

V04 Level T after the falling edge of "V<t>3" is expressed as "V4c". 

V<(h Level 3T after the falling edge of "V<K' is expressed as "Vic". 

A31 = (Vsa + V 2 c) / 2 - Vib 

A42 = (V4A + Vac) / 2 - V 2B 

A13 = (Via + V4c) / 2 - Vsb 

A24 = (V 2 a + Vic) / 2 - V4B 

The minimum from these values is defined as the vertical transfer clock amplitude "V<|>v". 

2) The maximum value from Via, V2A, Vsa, and V4A, is defined as the high level Vvh of the 
clock. 

3) The minimum level in a waveform which includes the vertical clock coupling is expressed 
as "Vvll". 

"Vvhh" expresses the maximum level except. in the period where read clock Vr is protruding 
(in V<J)i and Vcjw only). 



- 184 



SONY® 



ICX024AK-3 




Fig. 6 Vertical transfer clock waveform 

T = 564ns (with a horizontal driving frequency of 1 4.1875MHz) 



3. Horizontal transfer clock voltage 

1) For the horizontal transfer clock s "H<|>r and "H<t>2", the low-level period is expressed as 
"thl" and the high-level period is expressed as "thh". The symbol "tho" expresses the 
overlap period of "thl" and "thh". 

2) The low level at which "thl", "thh" and "tho" satisfy the following time duration is 
expressed as "Hib" and "HW. 

And the high level is expressed as "Hia" and "H2A" 

thl > 10 ns, thh > 10 ns, tho > 5 ns 

A 21 = Hia - H 2B 
A 12 = H 2 a - Hie 

The smaller of A21 and A12 is defined as the horizontal transfer clock amplitude "V<t>H". 
The low level at that point is expressed as "Vhl". 

3) The minimum level in the waveform which contains the coupling of the horizontal transfer 
clocks "H<t>1" and "H<j> 2 " is expressed as "Vhll" and the minimum level is expressed as 

"Vhhh". 

Vhhh 

H2A-T 



I 



H1B-1 




1H2B 



Fig. 7 Horizontal transfer clock waveform 



- 185 



SONY® 



ICX024AK-3 



4. Output reset clock voltage 

1) The low level of the output reset clock is to be the GND in the circuit. 

2) The amplitude of the output reset PG clock "\A|)pg" is defined as the maximum value of 
the amplitude which provides a high level period over 10 ns. 



More than 1 ns 



High level 



Low level 




V^PG 



VPGL 



Fig. 8 Waveform of PG clock 

5. Basic clock voltage 

1) Basic voltage is expressed as <|>l and the maximum value of the basic clock waveform as 

<|)H. 

2) The period during which voltage level reaches (<)>h - <)>l) is expressed as tsr. The 
difference of voltage level with <j)L at tsr/2 is defined as basic clock voltage V<|> SUB. 




(4>H - <t>L)/2 
<J)L = Vsub 



Fig. 9 Basic clock waveform 
Driving Clock Waveform Conditions 

1) Definition of <|>h (100%) and <)>l (0%) 

(1) For the horizontal transfer clocks (H<t>i, H^), output reset clock (PG<t») and vertical transfer 
clocks (V<j)i, V<])2, V<|>3, V<|>4), the maximum value in the clock waveform which includes no 
coupling is expressed as "<|>h" and the minimum value is expressed as "<t»L". 

(2) For the read clock (Vr), the maximum value in the clock waveform is expressed as "<|>h"."<|>l" 
expresses the voltage level while the read clock (Vr) of the vertical transfer clocks (V<j>i, v>2) is 
protruding. 

(3) For the substrate clock (SUB<(>), the maximum value in the clock waveform is expressed as "(K 
and the substrate voltage (Vsub) as "<|>l". 



- 186 



SONY® 



ICX024AK-3 



2) Standard driving clock conditions (Typ. 
Horizontal drive frequency: 1 4.1875MHz 



Clock 
(Symbol) 


twh 


twl 


tr 


tt 


Unit 


Remarks 




H<>1 


18 


33.7 


10 


8 


ns 


Imaging period 


H<|>2 


18 


33.7 


10 


8 


H<(>1 


4.9 




0.01 


0.01 


US 


Parallel-serial converting period 


H«>2 




4.9 


0.01 


0.01 


<|)PG 


12 


53.7 


2 


2 


ns 




V<>1/V(|)2 


61.6 


1.6 


0.1 


0.1 


US 


Imaging period Reading period 


V<t>3/V<t>4 


2.8 


60.45 


0.05 


0.1 


V<»T 


2.4 




0.2 


0.1 


Reading period 


SUB<|) 


1.0 




0.08 


0.1 


[IS 


Electron sweep-off period 










tw 


h 






. <t>H(100%) 






90%- 






\ 


twl 






7 


r~ 


\ 


V 





10% 



<t>i_(o%; 



Fig. 10 Clock waveform 



Imaging Characteristics 



(For the testing circuit, see Fig. 10.) 
Ta=25°C 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Testing method 


Remarks 


Sensitivity G 


sg 


120 


160 




mV 


1 




Sensitivity ratio 


Ye 


Ry 


1.50 


1.70 


1.90 




1 




Cy 


Re 


1.28 


1.40 


1.60 




1 




Output saturation signal 


Vsat 


500 






mV 


2 


Note 


Blooming margin 




800 






times 


3 


Note 


Smear 


Smr 




0.07 


0.015 




4 




Video signal shading 


Svg 






25 


% 


5 




Uniformity in video 
signal channels 


ASrg 






10 


% 


6 




ASbg 






10 


% 


6 




Dark signal output 


Vdt 






2 


mV 


7 


Ta=55°C 


Dark signal shading 


AVdt 






1 


mV 


8 


Ta=55°C 


Flicker 


Ye 


Fy 






5 


% 


9 




G 


Fg 






5 


% 


9 




Gy 


Fc 






5 


% 


9 





I 



Note) Saturation signal and blooming margin are guaranteed only when the substrate voltage has 
been set to the voltage indicated on the back of the imaging device. 



187 



S ONYs ICX024AK-3 

Test Methods 

Conditions 

1) The conditions required to drive the device through the following tests are covered by the bias 
conditions and the clock voltage conditions. The test circuit shown in Fig. 11 is used for 
evaluating and testing the characteristics. 

2) Flaws are excluded from the following tests and the signal output is based on the optical back 
level unless otherwise specified. The value obtained at the output test point becomes the test 
value. 

Standard imaging conditions 

1) Shoot the PTB-100 pattern box (luminance 706 Nit, color temperature 3200°K) with no pattern, 
using a FUJINON H6 x 1 2.5D (F1 .4) lens at F5.6. Use the CM-500S (1 .0 mmt) filter to cut 
off infrared rays. 

2) Shoot a light source (color temperature 3200°K) which provides a uniform brightness within 2% 
over the whole screen. 

For infrared cut-off filter, use the CM-500S (1.0 mmt). 

1. Set to standard imaging condition 1) and test signal voltages (Sy, Sg, Sc) of Ye, G, Cy channels 
at the center of the screen. 

Ry = Sy / Sg 
Re = Sc / Sg 

2. Set to standard imaging condition 2) and adjust the light intensity applied to Ye channel to about 
eight times the intensity obtained at a signal voltage of 200 mV. Then obtain the minimum value 
of the signal voltage at channels Ye, G and Cy respectively over the whole screen. 

3. Set to imaging condition 2) and adjust the light intensity applied to channel Ye to about 800 times 
the intensity obtained at a signal voltage of 200 mV. At that time make sure there is no blooming 
and the vertical resistor is not saturated. 

4. Set to standard imaging condition 2) and adjust the light intensity so that the signal voltage of G 
channel (Vsg) becomes 200 mV. Then, turn Vr off and obtain the maximum value of the signal 
voltage "Vsm" after stopping the horizontal resistor 50 H at the effective picture element without 
depending Ye, G, Cy channels. 

Smr = -Ssr x -55" x TO" x 10 °( % > 

(Converted into 1/10 V system) 

5. Set to standard imaging condition 2) and test the signal voltage of G channel to obtain maximum 
(Vg max) and minimum (Vg min) values. 

The light intensity is adjusted so that the average value of the signal voltage (Vg average) 
becomes about 200 mV. 



SONY® 



ICX024AK-3 



6. Following test 5, test the signal voltage of each channel. Calculate the output gains of the red 
and blue signals (Ar and Ab) from the mean values of the signal voltages of Ye, G and Cy 
channels (VYmean, VGmean, VCmean). Then arrange the mean value of the red and blue signal 
voltage (VRmean and VBmean) so that they become equal to "VGmean". Then measure the 
differences between the G channel signal voltage (VG) and the R channel as well as B channel 
signal voltage (VR as well as VB) to obtain the maximum and minimum values. 

VYmean - VGmean 
VGmean 

VCmean - VGmean 



Ab = 



VGmean 

VR = (VY - VG)/Ar VB = (VC - VG)/Ab 

(VR - VG)max - (VR - VG)min 
ASr 9 = VGmearT X 100(%) 

(VB - VG)max - (VB - VG)min 
ASbg = VGmean x 100(%) 

7. Measure the mean voltage of the dark current signal based on the horizontal free-transfer level 
in light-shaded condition with an ambient temperature of 55°C. 

8. Following measurement 7, test the dark current signal voltage to obtain the maximum (V dmax) and 
minimum (V dmin) values. Spot defects are ignored in this test. 

AVdt = (Vdmax - Vdmin) 

9. Set to standard imaging condition 2) and test the signal voltage difference "Vdr" between the fields 
of each channel. The light intensity is adjusted so that the average value of the G channel signal 
output (VG average) becomes about 200 mV. 

The average values of Ye and Cy channels are expressed as "VY average" and "VC average", 
respectively. 



I 



Fi = tf^- x 1 00 (%) 

Vi average v ' 



i = Y, G, C 



189- 



SONY® 



ICX024AK-3 



Electrical Characteristics Test Circuit 




Fig. 11 



Spectrum Sensitivity Characteristics (Typical example, excluding illuminant characteristics) 



































Y<jNs v 






/Cy 


/ G 
































































V 












^ 


S 







Wave length [nm] 



190 



SONY, 



ICX024AK-3 




1-P^ 



I 



191 



SONY® 



ICX024AK-3 



Sensor Read clock Timing Chart 



< EVEN FIELD) 



i r 



Unit: |is 



Charge Drain Clock Timing Chart 



'•os Unit: \xs 



- 192 



SONY® ICX024AK-3 

Handling Instructions 

1. On electric screening 

To prevent damage to the CCD image sensor by static electricity, handle as follows. 

a) Either handle the device with bare hands, or use antistatic gloves and clothes. Conductive 
. shoes are also required. 

b) Use a ground lead when directly touching the device. 

c) Cover the floor and working table with a conductive mat or equivalent to avoid static electricity. 

d) Discharge using ionized air is recommended. 

e) To ship the mounted boards, use cartons with antistatic properties. 

2. On soldering 

a) Make sure the package temperature does not exceed 80°C. 

b) Solder-dipping in a mounting furnace may break glass. Use a grounded 30 W soldering iron a 
each pin for less than 2 seconds. When adjusting or removing soldered parts, let the CCD 
cool sufficiently. 

c) Do not use any solder-aspirating equipment to remove the imaging device. Should an electric 
solder-aspiration device be used, use only a device of the zero-cross type control system and 
be sure to ground the controller. 

3. On contamination 

a) Keep the operation room clean (Class 1000 will be expected). 

b) Do not touch the glass surface avoid contact with foreign objects. Blow off any dust the 
surface with a blower. (Ionized air is recommended to blow off any object sticking through 
static electricity.) 

c) Wipe off grass spots with an applicator moistened with ethanol. Be careful not to scratch the 
surface. 

d) To eliminate contamination, store the device in an exclusive case. During transportation 
minimize the difference in temperatures between locations to avoid moisture condensation. 

e) When a protection tape has been affixed for shipment, remove it just before use after applying 
appropriate antistatic measures. Do no reuse the removed tape. 

4. Do not subject the device to light sources for extended periods. If a color element is subjected to 
strong light ray for an extended period, the color filter will be discolored. (Store the device in a 
dark place.) 

5. Usage or storage of the device in high temperature or high humidity may seriously affect the 
performance. 

6. The CCD image sensor is a high-precision optical part, that should not be subjected to mechanical 
shocks. 

7. System data write complete ROM (with flow compensation address included) 
System data write complete ROM in equal quantity as ICX024AK-3 is attached. 
Analog those ROM with address for flow compensation have serial No. stuck on. 
Use in conjunction with ICX024AK-3 pairing the same serial No.. 



193- 



SONY. 



IU022AK-30A/40A 
IU024AK-30A/40A 



CCD Imaging Blocks for Color Camera 



Description 

IU022AK-30A/40A and IU024AK-30A/40A are solid state imaging blocks developed for color video 
cameras. They incorporate an image correction optical filter (Optical crystal low pass filter, infrared cut filter) 
indispensable for solid state imaging devices. 

These blocks can easily be attached to the rear of a lens or the mount of an interchangeable lens to provide 
a lightweight, compact imaging system. 

Pin Configuration (Top View) 





Fig. 1 



Pin Description 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V*4 


Vertical register transfer clock input 


11 


Vout 


Signal output 


2 


V*3 


Vertical register transfer clock input 


12 


Vgg 


Output amplifier gate bias 


3 


V*2 


Vertical register transfer clock input 


13 


Vss 


Output amplifier source bias 


4 


SUB 


Substrate 


14 


GND 


GND • 


5 


GND 


GND 


15 


PD 


P recharge drain bias 


6 


V*i 


Vertical register transfer clock input 


16 


PG 


Output reset clock input 


7 


VL 


Protected transistor bias 


17 


VL 


Protected transistor bias 


8 


NC 


Non connection 


18 


H4.2 


Horizontal register transfer clock 
input 


9 


NC 


Non connection 


19 


H*i 


Horizontal register transfer clock 
input 


10 


Vod 


Supply voltage 


20 


GND 


GND 



- 194 



SONY® 



IU022AK-30A/40A, IU024AK-30A/40A 



Package Outline (Unit: mm) 



6.6±° 3 




I 



2.54 



0.46 



35. 5* 02 




Fig. 2 



- 195 



SONY® 



IU022AK-30A/40A, IU024AK-30A/40A 



Configuration and Optical Characteristics 



Item 


Ratings 


Unit 


Remark 


Appearance, size, 
attachment. 


See the Package 

Outline (Fig. 2) 






Optical axis 


Within the #11.1 circle with 
the Ref. A center are the effec- 
tive elements. 


mm 


Fig. 2 

Standard location A 


Image rotation 


Within ±1 


deg 


#1.6 spot 


Back focus 


1.74±0.3 


mm 


(In AIR) 

Fig. 2 Standard surface B 


Tilt 


60 


//m 


Fig. 2 Standard surface B 


Optical thickness 


6.6 


mm 


BK-7 equivalent 

(including optical filter assembly and optical 

parts of CCD) 


Optical filter 


Four-layer laminated type 






Spectral sensitivity 
characteristics 


See Fig. 3 






Weight 


14 


g 





Note) See the specifications of ICX022AK-3/4 and ICX024K-3/4 for imaging characteristics, electrical 
characteristics and absolute maximum ratings. 



Spectral sensitivity characteristics example 



1.0 




























0.7 




/Cy 


A qN ^ 


Ye\ 
































0.4 


































\ 



































Wave length (nm) 
Fig. 3 



Environmental Characteristics 



Item 


Condition 


Requirements 


Vibration 


7G, 10 to 30Hz, 300sec sweep, each 
15min for x, y, z directions 




Impact 


80G, in 6directions 




Low temperature durability 


-30°C, 240 hours 


The above structure satisfies optical 


High temperature durability 


80°C, 240 hours 


characteristics. 


Heat cycle 


-30-C to25°Cto80°C ^ 
30min to 5mm to 30mm 




High temperature and 
high humidity durability 


60°C, 95%, 240hours 





- 196 



SONY® 



ICX022AN-3 



Interline-type CCD Solid Image Sensor 



Description 

ICX022AN-3 is an interline-type CCD solid imaging 
device designed for color video cameras. 
Effective pixels number 768 horizontally and 493 
vertically. 

HAD (Hole Accumulated Diode) sensors are 
employed as photosensor elements to ensure much 
reduced dark current. 

Color filters incorporated Ye, G, Mg and Cy are 
mosaic filters of high resolution and high sensitivity. 

The device employs the field integration system to 
obtain a high resolution. 

Electric charges are swept out of the substrate, so 
the sensor has electronic shutter capability with 
variable charge storage time. 

Features 

• Image size: 2/3 inches (8.8 mmH x 6.6 mmV) 

• Effective pixels: 768H x 493V 

• Effective optical black 



Package Outline 



Unit: mm 



Horizontal: 



Vertical: 



5 pixels 
45 pixels 
16 pixels 

4 pixels 



Front 

Back 

Front 

Back 
High resolution 
High sensitivity 
Low noise 
Low smear 
Low dark current 
Electronic shutter 
Low antiblooming 

No graphic distortion, no microphonic noise 
Y characteristics: 1 



20 pin DIP (Ceramic) 



2-0 25 



»— -'-- 



m 



0.3% 



7Z 



r-^A 




A I «irectiv« «l«m«nt* picture c«nt«r 



[254. 



493 



Pin 1 1 side -* 




Pin 1 side 



I 



Optical black configuration 



Device Structure 

• Interline type CCD image sensor 

• Chip size: 1 0.0 mmH x 8.2 mmV 

• Unit cell size: 1 1 .0 urn (H) x 1 3.0 \im (V) 

• Dummy bits: Horizontal 22-bits, vertical 1-bit 
(Even fields only) 

• HAD (Hole Accumulated Diode) sensor 

• High sensitivity output amplifier 

• Ye, Cy, Mg, G on chip type complementary color mosaic filter 

• N type substrate P-well structure 



E88238-YA 



- 197- 



SONY® 



ICX022AN-3 



Imaging Device Function Block 




"Note) — [ 



Pin Configuration and Description (Top View) 



o o 



V04 


(D 


® 


GNO 


V0J 


© 


@ 


H0> 


V02 


© 


@ 


H04 


SUB 


© 


© 


Vl 


GNO 


© 


® 


PG 


V0< 


© 


© 


PO 


Vi. 


© 


@ 


GND 


NC 


© 


@ 


Vss 


NC 


© 


© 


V» 


Vdo 


(yS) 


vO 


Vout 



o o 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V>4 


Vertical register transfer clock 


11 


Vout 


Signal output 


2 


V<|>3 


Vertical register transfer clock 


12 


Vgg 


Output amplifier gate 


3 


V>2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (OFD) bias 


14 


GND 


GND 


5 


GND 


GND 


15 


PD 


Pre-charge drain bias 


6 


V<|>1 


Vertical register transfer clock 


16 


PG 


Output reset clock 


7 


Vl 


Protection transistor bias 


17 


Vl 


Protection transistor bias 


8 


NC 




18 


H<|>2 


Horizontal register transfer clock 


9 


NC 




19 


H<|)i 


Horizontal register transfer clock 


10 


Vdd 


Output amplifier drain supply 


20 


GND 


GND 



198 



SONY® 



ICX022AN-3 



Absolute Maximum Ratings 



Item 


Ratings 


Unit 


Remarks 


SUB-GND 


-0.3 to +55 


V 




Vdd, PD, Vout, Vss-GND 


-0.3 to +20 


V 




Vdd, PD, Vout, Vss-SUB 


-55 to +10 


V 


Note 1 


Horizontal and vertical transfer clock inputs - GND 


-15 to +20 


V 




Horizontal and vertical transfer clock inputs - SUB 


-65 to +10 


V 


Note 1 


Potential difference between vertical transfer clock inputs 


+15 


V 


Note 2 


Potential difference between horizontal transfer clock inputs 


+17 


V 




H<|>1, H<>2 - V<|)4 


-17 to +17 


V 




PG, Vgg - GND 


-10 to +15 


V 




PG, Vgg - SUB 


-55 to +10 


V 


Note 1 


Vl - SUB 


-65 to +0.3 


V 




Pins other than GND, SUB and Vl-Vl 


-0.3 to +28 


V 




Storage temperature 


-30 to +80 


°C 




Operation guarantee ambient temperature 


-10 to +55 


°C 





Note) 1 . This imaging device consists of an N substrate P-Well structure where a protection transistor is 

connected to each pin accordingly. If a voltage exceeding 1 V is applied to pins other than Vl against 
the SUB pin, a punch through current will flow. Since a series resistance Rl is located between each 
pin and SUB, the device will withstand destruction through any rush voltage over 1 V. 
The series resistance Rl must be more than 1 kQ between Vp-p and SUB, more than 500 Q between 
Vout and SUB and more than 5kQ between Vss or PD and SUB. The series resistance between other 
pins (except Vl and GND) and SUB must be more than 5 kQ. 



® Vdd, PD, Vout and Vss pins 



Pins other than © (except Vl and GND) 



Every pin o- 



pin o •■ 

vlo — r 



GNDo- 



SUB o- 



Every pin o 



r 




SUB o 



Fig. 2 Equivalent circuit 



2. In case of clock width <10 us and clock duty factor <0.1%, up to 27 V is guaranteed. 



199- 



SONY® 



ICX022AN-3 



Bias Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Supply voltage of output circuit 


Vdd 


14.55 


15.0 


15.45 


V 




Vpd 


14.55 


15.0 


15.45 


V 


Notel 


Vgg 


1.6 


2.0 


2.4 


V 




Vss 


Ground with a 390 Q resistance 


±5% 


Substrate voltage adjustable range 


VSUB 


9 




19 


V 


Note 2 


Regulation range after substrate 
voltage adjustment 


VSUB 


-3 




3 


% 




Protection transistor bias 


Vl 


-12 


-11 


Note 6 


V 





DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output circuit current 


Idd 




5.0 




mA 


Note 3 


Input current 


||N1 






1 


\iA 


Note 4 


llN2 






10 


uA 


Note 5 



Note) 1 . Vpd and Vdd must have the same voltage. 

2. Indication of the substrate voltage (Vsub) set value: 

The set value is indicated on the rear of the imaging device by a code. Adjust to obtain the indicated 
voltage at the SUB pin. 

Vsub code - Two digit indication 



Integral part 



Decimal part 



The integral codes correspond to tr 


ie following actual values 








Integral codes 


9 


A 


B 


C 


D 


E 


F 


G 


H 


I 


J 


Actual values 


9 


10 


11 


12 


13 


14 


15 


16 


17 


18 


19 



EX.) F5^15.5(V) 

3. Ground Vss with a 390Q resistance. 

4. 1 ) Current flowing to the ground when a voltage of 20 V is applied to Vdd, PD, Vout, Vss and SUB 

pins. Test ground all the pins other than those under test. 

2) Current flowing to the ground when a voltage of 25 V is applied to V<>1, V(|>2, V4>3, V<)>4, H<)>1 and H<t>2 
pins in the order. Apply pin a voltage of 25 V to the SUB pin and ground pins other than those under 
test. 

3) Current flowing to the ground when a voltage of 1 5 V is applied to PG and Vgg pins in the order. 
Apply a voltage of 15 V to the SUB pin and ground pins other than those under test. 

4) Current flowing to the ground when Vl pin is grounded, GND and SUB pins are open and a voltage 
of 27 V is applied to other pins. 

5. Current flowing to the ground when a voltage of 55 V is applied to the SUB pin. In this case ground 
pins other than those under test. 

6. Vertical transfer clock low level clamp bias 



200 



SONY® 



ICX022AN-3 



Clock Voltage Conditions 
Clock voltage 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Read clock voltage 


VVT 


13.0 




15.0 


V 


Note 1 


Vertical transfer clock voltage 


VvHH 






1.3 


V 


Note 2 


VVH 


-0.3 




0.7 


V 


V*v 


8.0 






V 


VVLL 


-11.0 






V 


Horizontal transfer clock voltage 


Vhhh 






5.5 


V 


Note 3 


Vhl 


-3.0 




-1.7 


V 


V»H 


5.2 




8.0 


V 


Vhll 


-3.0 






V 


Output reset clock voltage 


Vpgl 









V 


Note 4 


VfPG 


7.0 




13.0 


V 


Substrate clock voltage 


V((iSUB 


23.0 




27.0 


V 


Note 5 



Clock capacitance 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Vertical transfer clock - GND 


C4.V 




5000 




pF 




Capacitance between vertical transfer 
clocks 


C»W 




1500 




PF 




Horizontal transfer clock - GND 


C*H 




180 




pF 




Capacitance between horizontal transfer 
clocks 


GtiHH 




50 




pF 




Output reset clock - GND 


CfPG 




10 




pF 




Substrate clock - GND 


C*SUB 




500 




PF 





I 



H0i- 



C0HH 

1 " 1 

r 



-H02 



I 



C0H 



Fig. 4 Equivalent circuit of horizontal transfer clock capacitance 



201 



SONY® ICX022AN - 3 

Note) 1. Read clock voltage 

1 ) The symbol "<|>l" expresses the voltage level while the read clock "Vt" of the vertical transfer clocks 
("V<|)i" and "V(|>2") is set. The maximum value in the read clock waveform is expressed as "<|>h". 

2) The period in which the voltage level becomes (<)>h - <|>l)/2 is expressed as "tsr". The voltage levels 
at "tsr/2" are expressed as "Vn" (at Vcj>i) and "V-ra" (at Vfa). The smaller of "Vn" and "Vt3" is 
defined as the read clock voltage "Vvt". 



VT1,VT2 




=V0i,V03 LEVEL 

Fig. 5 Read clock waveform 

2. Vertical clock voltage (Refer to Fig. 6) 

T = 559 ns (with a horizontal driving frequency of 14.32 MHz) 
1 ) Definition of the vertical transfer clock amplitude 

Level 2T after the rising edge of "VV is expressed as "Vm". 
Level T after the falling edge of "V<|>r is expressed as "Vm". 
Level 2T after the rising edge of "vV is expressed as "vV. 
Level T after the falling edge of "V<|>2" is expressed as "VW. 
Level 2T after the rising edge of "v>r is expressed as "Via". 
Level T after the falling edge of "V<|>3" is expressed as 'W. 
Level 4T after the rising edge of "V<|>2" is expressed as "V2A". 
Level 3T after the falling edge of "VcK is expressed as "V4b". 

V<|)2 level T after the falling edge of "V<t»i" is expressed as "V 2 c". 
V<j>3 level T after the falling edge of "Vtyi" is expressed as "V3c". 
V<|)4 level T after the falling edge of "V<|>3" is expressed as "Vac". 
V<|>1 level 3T after the falling edge of "W is expressed as "Vic". 

A31 = (V3A + V2C) / 2 - VlB 
A42 = (V4A + Vsc) / 2 - V2B 
A13 = (Via + V4c)/2-V 3 b 
A24 = (V 2 a + Vic) / 2 - V4B 

The minimum value of these is defined as the vertical transfer clock amplitude "V<K' 



2) The maximum value from Via, V>a, Vsa, and Via, is defined as the high level Vvh of the clock. 

3) The minimum level in a waveform which includes the vertical clock coupling is expressed as "Vvll" 
"Vvhh" expresses the maximum level except in the period where read clock Vt is applied (in V<)>1 
and V<))3 only). 



202- 



SONY® 



ICX022AN-3 




Fig. 6 Vertical transfer clock waveform 

T s 559ns (with a horizontal driving frequency of 4 fsc) 

3. Horizontal transfer clock voltage 

1 ) For the horizontal transfer clocks "H<|>r and "H<|>2", the low-level period is expressed as "thl" and 
the high-level period is expressed as "thh". The symbol "tho" expresses the overlap period of "thl" 
and "thh". 

2) The low level at which "thl", "thh" and "tho" satisfy the following time duration is expressed as 
"Hib" and "H2B". 

And the high level is expressed as "Hia" and "H2A" 



I 



thl > 10 ns, thh > 10 ns, tho > 5 ns 

A 21 = Hia - H 2B 
A12 = H 2 a-Hib 

The smaller of A21 and A12 is defined as the horizontal transfer clock amplitude "V<)>h". The low 
level at that point is expressed as "Vhl". 
3) The minimum level in the waveform which contains the coupling of the horizontal transfer clocks 
"H<|)i" and "H<|>2" is expressed as "Vhll" and the minimum level is expressed as "Vhhh". 




Fig. 7 Horizontal transfer clock waveform 



-203- 



SONY® 



ICX022AN-3 



4. Output reset clock voltage 

1 ) The low level of the output reset clock is to be the GND in the circuit. 

2) The amplitude of the output reset PG clock "V<)>pg" is defined as the maximum value of the 
amplitude which provides a high level period over 10 ns. 



More than 10 ns 



High level 



Low level 




V(|>PG 



V<|>PGL 



Fig. 8 Waveform of PG clock 



5. Substrate clock voltage 

1 ) Substrate voltage is expressed as <|)L, and the substrate clock waveform maximum value as <|>H. 

2) The period where voltage level turns to (<t>H-<|)L)/2 is expressed as tsr. The difference between <|>L 
and voltage level at tsr/2 is defined as the substrate clock voltage V<()SUB. 




Fig. 9 Substrate clock waveform 
Driving Clock Waveform Conditions 

1 . Definition of <|>h (1 00%) and <|>l (0%) 

1 ) For the horizontal transfer clocks (H^i, H<|)z), output reset clock (PG<])) and vertical transfer clocks (V<|>1, 
V^, V(|>3, V<|>4), the maximum value in the clock waveform which includes no coupling is expressed as 
"<)>h" and the minimum value is expressed as "<|>l". 

2) For the read clock (Vt), the maximum value in the clock waveform is expressed as "<|>H"."<t>L" expresses 
the voltage level while the read clock (Vt) of the vertical transfer clocks (V<|>1, V<t>2) is applied. 

3) For the substrate clock (SUB<|>), the maximum value in the clock waveform is expressed as "<|>h" and the 
substrate voltage (Vsub) as "<(>l". 



204 



SONY® 



ICX022AN-3 



2. Standard driving clock conditions (Typ.) 
Horizontal drive frequency: 14.32 MHz 



Clock 
(Symbol) 


twh 


twl 


tr 


tf 


Unit 


Remarks 


H4>1 


18 


33.7 


10 


8 


ns 


Imaging period 


H<|>2 


18 


33.7 


10 


8 


H4m 


4.9 




0.01 


0.01 


US 


Parallel-serial converting period 


H<|>2 




4.9 


0.01 


0.01 


(|)PG 


12 


53.7 


2 


2 


ns 




V<t>l/V<()2 


61.6 


1.6 


0.1 


0.1 


lis 


Imaging period 


V<t)3A/<()4 


2.8 


60.45 


0.05 


0.1 


V(()T 


2.4 




0.2 


0.1 


Reading period 


SUB<|> 


1.0 




0.08 


0.1 


[IS 


Electron drained into substrate period 



fM0%) 




I 



Fig. 10 Clock waveform 



205 



SONY® 










ICX022AN-3 


Imaging Characteristics 










(See Fig. 10.) 
Ta=25°C 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Testing method 


Remarks 


Sensitivity 


Sy 


150 


200 




mV 


1 




Output saturation signal 


Ysat 


600 






mV 


2 


Ta=55°C 


Smear 


SM 




0.007 


0.015 


% 


3 




Blooming margin 




1000 






times 


4 




Video signal shading 


SHy 






20 


% 


5 


Zone <|>, I 






25 


% 


5 


Zone <(> to II 


Uniformity between signal 
channels 


ASr 






10 


% 


6 




ASb 






10 


% 


6 




Dark signal 


Ydt 






2 


mV 


7 


Ta=55°C 


Dark signal shading 


AYdt 






1 


mV 


8 


Ta=55°C 


Flicker Y 


Fy 






2 


% 


9 




R-Y 


Fcr 






5 


% 


9 




B-Y 


Feb 






5 


% 


9 




Horizontal stripes R 


Lcr 






3.0 


% 


10 




G 


Leg 






3.0 


% 


10 




B 


Lcb 






3.0 


% 


10 




W 


Lew 






3.0 


% 


10 




Lag 


AYlag 






0.5 


% 


11 





Test Circuit 



CCD output signal ® 



I CCD I 1 1 CD. 



I 1 LPF1 J- 

JUUl 



-@ Y signal output ® 



ruuin 




lpf2 | — © Chroma signal output 



Note) Adjust AMP amplifier so that total gains between (A) and ® and between ® and © equal 1 . 



206- 



SONY® 



ICX022AN-3 



Test Method 
Test conditions 

1) Through the following tests the substrate voltage should set to the value displayed on the device, 
while the device drive conditions should be kept within the range of the bias and clock voltage 
conditions. 

2) Through the following tests defects are excluded and, unless otherwise specified the optical black 
level (Hence forth referred to as OPB) is set as the reference for the signal output which is 
taken as the Y signal output or the Chroma signal output of the testing system. 

Color coding of CFA (Color Filter Array) & Composition of luminance (Y) and chrominance (C) 
signals. 



CFA of this imager is shown in the Figure. This 
complementary CFA is used with a "field integration 
mode", where all of the photosites are read out 
during each video field. Signals from two vertically 
adjacent photosites, such as line A1 or A2 for field 
A, are summed when the image charge is 
transferred into the vertical storage columns. The 
readout line pairing is shifted down one line for 
field B. The sensor output signals through 
Horizontal register (H reg.) at line A1 are 

[G+Cy], [Mg+Ye], [G+Cy], [Mg+Ye]. 



Cy 


Ye 


Cy 


Ye 


G 


Mg 


G 


Mg 


Cy 


Ye 


Cy 


Ye 


Mg 


G 


Mg 


G 


^ 4^ 4' ^ 











A1 



A2 



Hreg 



Color Coding Diagram 



These signals are processed in order to compose Y and C signals. By adding the two adjacent 
signals at line A1, Y signal is formed as follows: 

Y = {(G+Cy) + (Mg+Ye)} x 1/2 
= 1/2 {2B+3G+2R} 

C signal is composed by subtracting the two adjacent signals at line A1. 

R - Y = {(Mg+Ye) - (G+Cy)} 
= {2R-G} 

Next, the signals through H reg. at line A2 are 

[Mg+Cy], [G+Ye], [Mg+Cy], [G+Ye] 

Similarly, Y and C signals are composed at line A2. 

Y = {(G+Ye) + (Mg+Cy)} x 1/2 
= 1/2 {2B+3G+2R} 

-(B-Y) = {(G+Ye) - (Mg+Cy)} 
= -{2B-G} 

Accordingly, Y signal is balanced in relation to the scanning lines, and C signal takes the form of R-Y 
and -(B-Y) on alternate lines. 
It is the same for B field. 



I 



-207- 



SONY® ICX022AN-3 

Definition of standard imaging conditions 

© Standard imaging condition I: (As imaging device) Use a pattern box (luminance 706 Nit, 3200°K 
Halogen source), at F5.6 with a typical test lens, and CM-500S (1.0 mmt) for IR cut filter. 

® Standard imaging condition II: Use a light source with uniformity within 2%, color temperature of 
3200°K and CM-500S (1.0 mmt) as IR cut filter. The light intensity is adjusted in accordance 
with the average value of Y signals (Ya) indicated in each item. 

1)Set to standard imaging condition I and measure Y signal (S) at the center of the screen. 

2) Set to imaging condition II. Adjust light intensity to 10 times when Y signal output average value 
YA=200mV. Then test Y signal Min. Value. 

3) Set to imaging condition II. Adjust light intensity to 500 times when Y signal output average value 
YA=200mV. Stop Read out clock. When the charge drain executed by the electronic shutter at the 
respective H blankings takes place, test the Max. value Ysm of Ysignal output. 

SM = (Ysm/Ya) x 7500 x V10 x 100 (%) (V10V) 

4) Set to imaging condition II. Adjust light intensity to 1 000 times when Y signal output average value 
Ya=200it)V. Then check that there is no blooming. 

5) Video signal shading SHy 

Set to standard imaging condition II. Test Y signal Max. (Y max.) and Min. (Y min.) values. 
Adjust light intensity to obtain a Y signal output average value (Ya) of about 150mV. 

SHy = (Ymax - Ymin)/YA x 100 (%) 

6) Set to standard imaging condition H. Adjust light intensity to obtain a Y signal output average value 
(Ya) of 200mA. Test the Max. (Cr max. and Cb max.) and Min. (Cr min. and Cb min.) values of 

C signals from R-Y and B-Y channels. 

ASr = | (Crmax - Crmin)/YA | x 100 (%) 
ASb = | (Cbmax - Cbmin)/YA | x 100 (%) 

7) Test the average Y signal voltage when the device ambient temperature is at 55°C and light is 
obstructed with horizontal idle transfer level as reference. 

8) Following 7, test Max. (Ydmax.) and Min. (Ydmin.) values of Y signal output. Only keep spot 
defects out of this range. 

AYdt = Ydmax - Ydmin 



-208- 



SONY® 



ICX022AN-3 



9) © Fy 

Set to standard imaging condition II. Adjust light intensity to obtain a Y signal output average 
value (Ya) of 200 mV. Test the Y signal difference (AYf) between even field and odd field. 

Fy = (AYf/YA) x 1 00 (%) 

® Fcr, Feb 

Set to standard imaging condition II. Insert R and B filter respectively, and test the C signal 
difference (ACr, ACb) between even field and odd field and the C signal output average value 
(CAr, CAb). At that time, adjust light intensity to obtain a Y signal output average value (Ya) of 
100 mV. 

Fci = (ACi/CAi) x 100 (%) (i = r, b) 

10) Set to standard imaging condition II. Insert W, R, G and B filters respectively, and test the 
signal difference (AYIw, AYIr, AYIg, AYIb) between Y signal lines of the same field. At that time, 
adjust light intensity to obtain a Y signal output average value (Ya) of 100 mV. 

Lei = (AYM/Ya) x 100 (%) (i = w, r, g, b) 



11) Light a stroboscopic tube with the following timing and test the residual image. 
AYlag = (Ylag/Ys) x 1 00 (%) 

AYIag = (Ylag/Ys)x100(%) 



FLD 



SGI 



I 



jl_j n n il 



SG2 



Strobe light timing. 



Output 



Ys 200mV Y lag (Residual image) 

ru_i.,_rL^-±_,— n n 
t 



_TL 



t 



209 



SONY® 



ICX022AN-3 



Drive Circuit 




210 



SONY® 



ICX022AN-3 



Spectral Sensitivity Characteristics (Excluding light source characteristics) 
Fujinon lens H6 x 12.5R 



a 



1.0- 


' " ' ' 





11 ■ y 


""V" ' 


,,ii 


III! 


.9 
.8 








Ye 






.7 
.6 




/ Cy 


If G 








.5 
.4 






/ 1 \ / 

— f • \ T 

/ ' \l 

T 1 — T 


r — - — i 




.3 
.2 

.1 


















Mg 




- - - 




.0 


, , , , 


/i , . 


. , i , 


i i . i 


, i i i 


1,11 



500 600 

Wave length [nm] 



Using read out clock timing chart 



I 




Unit: \xs 



211 - 



SONY® 



ICX022AN-3 



;s : 



u 





1 




_ J 


_ 








_ 




— — 


— 








_ 




— — 


— 




■jT 




_ 




— — 


— 


— 


rt 


















_ 




— — 


— 








_ 




— — 


— 








- 




- - 


— 








- 







- 








_ 




_ _ 


- 








i - 




z z 


— 








I 




g-c 


c 






pi 


-_ 




Z Z 


E 


«a 


1i 




_l — 


~~ 


~ — 


_ 








- 


- 


- — 


— 








_ 


_ 


z z 


z 








_ 






_ 








l— 






— 






c 
g 

a> 
a 
o 


- 


Z 


z : 


z 


v_ 


1 


a> 


~ . 


"~ 


5«^ 








3 


— 


Z 


"" ~ 


_ 






ectronic s 


J I 


^ 


z z 




Ǥ 


!' 


c 


2 


2 


- - 








3 

Q 


- 


- 


- - 









212 



SONY® 



ICX022AN-3 



Handling Instructions 

1) Static charge prevention 

CCD image sensor are easily damaged by static discharge. Before handling be sure to take the 
following protective measures. 

a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use 
conductive shoes. 

b) When handling directly use an earth band. 

c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. 

d) Ionized air is recommended for discharge when handling CCD image sensor. 

e) For the shipment of mounted substrates use boxes treated for the prevention of static charges. 

2) Soldering 

a) Make sure the package temperature does not exceed 80°C. 

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 
grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and 
remount cool sufficiently. 

c) To dismount an imaging device do not use a solder pult. When using an electric desoldering 
tool use a thermal controller of the zero cross On/Off type and connect to ground. 

3) Dust and dirt protection 

a) Operate in clean environments (around class 1000 will be appropriate). 

b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. 
Should dirt stick to a glass surface blow it off with an air blow. (For dirt stuck through static 
electricity ionized air is recommended) 

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not 
to scratch the glass. 

d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool 
when moving to a room with great temperature differences. 

e) When a protective tape is applied before shipping, just before use remove the tape applied for 
electrostatic protection. Do not reuse the tape. 

4) Do not expose to strong light (sun rays) for long periods, color filters are discolored. 

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage 
or usage in such conditions. 

6) CCD image sensor are precise optical equipment that should not be subject to mechanical shocks. 

7) Defect compensation ROM 

This is shipped in its own case in pair with the CCD image sensor. Pair with the CCD image 
sensor bearing the same serial number during mounting. When the CCD image sensor has no 
defect there is no ROM or serial number. 



I 



213- 



Interline-type CCD Solid Image Sensor 



Description 

ICX024AN-3 is an interline-type CCD solid imaging 
device designed for color video cameras. 
Effective pixels number 756 horizontally and 581 
vertically. 

HAD (Hole Accumulated Diode) sensors are 
employed as photosensor elements to ensure much 
reduced dark current. 

Color filters incorporated Ye, G, Mg and Cy are 
mosaic filters of high resolution and high sensitivity. 

The device employs the field integration system to 
obtain a high resolution. 

Electric charges are swept out of the substrate, so 
the sensor has electronic shutter capability with 
variable charge storage time. 

Features 

• Image size: 2/3 inches (8.8 mmH x 6.6 mmV) 

• Effective pixels: 756H x 581 V 

• Effective optical black 
Horizontal: Front 5 pixels 

Back 55 pixels 

Vertical: Front 19 pixels 

Back 6 pixels 

• High resolution 

• High sensitivity 

• Low noise 

• Low smear 

• Low dark current 

• Electronic shutter 

• Low antiblooming 

• No graphic distortion, no microphonic noise 

• y characteristics: 1 



Package Outline 



Unit: mm 



20 pin DIP (Ceramic) 

31.0w 



J2 



0.3^ 



¥ 



\ 2.0*2.5 (»■<>') 




p«tuf« c«nt«r 



- I?.54 



Pin 1 1 side-* 




Pin 1 side 



Device Structure 

• Interline type CCD image sensor 

• Chip size: 1 0.0 mmH x 8.2 mmV 

• Unit cell size: 1 1 .0 urn (H) x 1 1 .0 urn (V) 

• Dummy bits: Horizontal 22-bits, vertical 1 -bit 
(Even fields only) 

• HAD (Hole Accumulated Diode) sensor 

• High sensitivity output amplifier 

• Ye, Cy, Mg, G on chip type complementary color mosaic filter 

• N type substrate P-well structure 



Fig. 1 Optical black configuration 



E89143-YA 



214 



SONY® 



ICX024AN-3 



Imaging Device Function Block 




•Note) — L 



Photo Sensor 



Pin Configuration and Description (Top View) 



o o 



V04 


© 


@ 


GNO 


V0J 


© 


® 


H0i 


V02 


© 


@ 


H0a 


SUB 


© 


© 


Vl 


SNO 


© 


© 


PG 


V0< 


© 


© 


PO 


Vl 


m 


® 


GND 


NC 


© 


© 


Vis 


NC 
VOO 


© 
fa) 


@ 


Vol 
VOUT 



o o 



I 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V(|>4 


Vertical register transfer clock 


11 


Vout 


Signal output 


2 


V<|>3 


Vertical register transfer clock 


12 


Vgg 


Output amplifier gate 


3 


V<|>2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (OFD) bias 


14 


GND 


GND 


5 


GND 


GND 


15 


PD 


Pre-charge drain bias 


6 


V<|>1 


Vertical register transfer clock 


16 


PG 


Output reset clock 


7 


Vl 


Protection transistor bias 


17 


Vl 


Protection transistor bias 


8 


NC 




18 


H<))2 


Horizontal register transfer clock 


9 


NC 




19 


H<|>1 


Horizontal register transfer clock 


10 


Vdd 


Output amplifier drain supply 


20 


GND 


GND 



215 



SONY® 



ICX024AN-3 



Absolute Maximum Ratings 



Item 


Ratings 


Unit 


Remarks 


SUB-GND 


-0.3 to +55 


V 




Vdd, PD, Vout, Vss-GND 


-0.3 to +20 


V 




Vdd, PD, Vout, Vss-SUB 


-55 to +10 


V 


Note 1 


Horizontal and vertical transfer clock inputs - GND 


-15 to +20 


V 




Horizontal and vertical transfer clock inputs - SUB 


-65 to +10 


V 


Note 1 


Potential difference between vertical transfer clock inputs 


+15 


V 


Note 2 


Potential difference between horizontal transfer clock inputs 


+17 


V 




H<(>1 , H<|)2 - V(()4 


-17 to +17 


V 




PG, Vgg - GND 


-10 to +15 


V 




PG, Vgg - SUB 


-55 to +10 


V 


Note 1 


Vl-SUB 


-65 to +0.3 


V 




Pins other than GND, SUB and Vl-Vl 


-0.3 to +28 


V 




Storage temperature 


-30 to +80 


°C 




Operation guarantee ambient temperature 


-10 to +55 


°C 





Note) 1 . This imaging device consists of an N substrate P-Well structure where a protection transistor is 

connected to each pin accordingly. If a voltage exceeding 10 V is applied to pins other than Vl against 
the SUB pin, a punch through current will flow. Since a series resistance Rl is located between each 
pin and SUB, the device will withstand destruction through any rush voltage over 1 V. 
The series resistance Rl must be more than 1 kQ between Vp-p and SUB, more than 500 Q between 
Vout and SUB and more than 5k£2 between Vss or PD and SUB. The series resistance between other 
pins (except Vl and GND) and SUB must be more than 5 kQ. 



© Vdd, PD, Vout and Vss pins 



Every pin o- 



pin o * 

Vl o T 



GND o- 



SUB o- 



© Pins other than © (except Vl and GND) 
Every pin o- 



r 




SUB o- 



Fig. 2 Equivalent circuit 



2. In case of clock width <10 (is and clock duty factor <0.1%, up to 27 V is guaranteed. 



216 



SONY® 



ICX024AN-3 



Bias Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Supply voltage of output circuit 


Vdd 


14.55 


15.0 


15.45. 


V 




Vpd 


14.55 


15.0 


15.45 


V 


Notel 


Vgg 


1.6 


2.0 


2.4 


V 




Vss 


Ground with a 390 Q resistance 


±5% 


Substrate voltage adjustable range 


VSUB 


9 




19 


V 


Note 2 


Regulation range after substrate 
voltage adjustment 


VSUB 


-3 




3 


% 




Protection transistor bias 


Vl 


-12 


-11 


Note 6 


V 





DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output circuit current 


Idd 




5.0 




mA 


Note 3 


Input current 


||N1 






1 


RA 


Note 4 


llN2 






10 


uA 


Note 5 



Note) 1 . Vpd and Vdd must have the same voltage. 

2. Indication of the substrate voltage (Vsub) set value: 

The set value is indicated on the rear of the imaging device by a code. Adjust to obtain the indicated 
voltage at the SUB pin. 

Vsub code - Two digit indication [ j ^ 



I 



Integral part 



Decimal part 



The integral codes correspond to the following actual values: 



Integral codes 


9 


A 


B 


C 


D 


E 


F 


G 


H 


I 


J 


Actual values 


9 


10 


11 


12 


13 


14 


15 


16 


17 


18 


19 



EX.) F5->15.5(V) 

3. Ground Vss with a 390Q resistance. 

4. 1 ) Current flowing to the ground when a voltage of 20 V is applied to Vdd, PD, Vout, Vss and SUB 

pins. Test ground all the pins other than those under test. 

2) Current flowing to the ground when a voltage of 25 V is applied to V<|>1, V<t>2, V<)>3, V<)>4, H01 and H<t>2 
pins in the order. Apply pin a voltage of 25 V to the SUB pin and ground pins other than those under 
test. 

3) Current flowing to the ground when a voltage of 1 5 V is applied to PG and Vgg pins in the order. 
Apply a voltage of 1 5 V to the SUB pin and ground pins other than those under test. 

4) Current flowing to the ground when Vl pin is grounded, GND and SUB pins are open and a voltage 
of 27 V is applied to other pins. 

5. Current flowing to the ground when a voltage of 55 V is applied to the SUB pin. In this case ground 
pins other than those under test. 

6. Vertical transfer clock low level clamp bias 



-217- 



SONY® 



ICX024AN-3 



Clock Voltage Conditions 
Clock voltage 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Read clock voltage 


VVT 


13.0 




15.0 


V 


Note 1 


Vertical transfer clock voltage 


VvHH 






1.3 


V 


Note 2 


VVH 


-0.3 




0.7 


V 


V»v 


8.0 






V 


VVLL 


-11.0 






V 


Horizontal transfer clock voltage 


Vhhh 






5.5 


V 


Note 3 


Vhl 


-3.0 




-1.7 


V 


V»H 


5.2 




8.0 


V 


Vhll 


-3.0 






V 


Output reset clock voltage 


Vpgl 









V 


Note 4 


V»PG 


7.0 




13.0 


V 


Substrate clock voltage 


V»SUB 


23.0 




27.0 


V 


Note 5 



Clock capacitance 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Vertical transfer clock - GND 


C«v 




5000 




pF 




Capacitance between vertical transfer 
clocks 


C«>w 




1500 




PF 




Horizontal transfer clock - GND 


C«H 




180 




PF 




Capacitance between horizontal transfer 
clocks 


C*HH 




50 




PF 




Output reset clock - GND 


C*PG 




10 




PF 




Substrate clock - GND 


C*SUB 




500 




PF 





HfJi- 



C0HH 

HI— 



CflSH 



-H02 



C<6h 



Fig. 4 Equivalent circuit of horizontal transfer clock capacitance 



218 



SONY® 



ICX024AN-3 



Note) 1 . Read clock voltage 

1 ) The symbol "<|>l" expresses the voltage level while the read clock "Vt" of the vertical transfer clocks 
("V<|)i" and "VV) is set. The maximum value in the read clock waveform is expressed as 'V. 

2) The period in which the voltage level becomes (<)>h - <>l)/2 is expressed as "tsr". The voltage levels 
at "tsr/2" are expressed as "Vn" (at v>i) and "Vn" (at V<|)3). The smaller of "Vn" and "Vra" is 
defined as the read clock voltage "Wr". 



VT1.VT2 




<*l=V«S!,V<m LEVEL 



Fig. 5 Read clock waveform 

2. Vertical clock voltage (Refer to Fig. 6) 

T = 564 ns (with a horizontal driving frequency of 14.19 MHz) 
1 ) Definition of the vertical transfer clock amplitude 



Level 2T after the rising edge of "vV 
Level T after the falling edge of "vV 
Level 2T after the rising edge of "Vty* 
Level T after the falling edge of "V<t>2" 
Level 2T after the rising edge of "V<t>r 
Level T after the falling edge of "V<t>3" 
Level 4T after the rising edge of "V<|>2' 
Level 3T after the falling edge of "V<|>4 



is expressed as "V3a". 
is expressed as "Vib". 

is expressed as "W. 
is expressed as "VW. 
' is expressed as "Via". 
is expressed as "Vsb". 
' is expressed as "V2a" 
" is expressed as "V4b" 



I 



V<))2 level T after the falling edge of "V<n" is expressed as "V2c". 
V<|>3 level T after the falling edge of "Vijte" is expressed as "V3c". 
V<|>4 level T after the falling edge of "V<|)3" is expressed as "V»c". 
V<|>1 level 3T after the falling edge of "V<|>4" is expressed as "Vic". 

A31 = (Vsa + V 2 c) / 2 - Vib 
A42 = (V4A + Vsc) / 2 - V2B 

A13 = (Via + V4c)/2-V 3 b 
A24 = (V 2 a + Vic) / 2 - V4B 

The minimum value of these is defined as the vertical transfer clock amplitude "V<t>v" 



2) The maximum value from Via, V2A, Vsa, and V4A, is defined as the high level Vvh of the clock. 

3) The minimum level in a waveform which includes the vertical clock coupling is expressed as "Vvll" 
"Vvhh" expresses the maximum level except in the period where read clock Vt is applied (in V<f>i 
and V<|>3 only). 



-219- 



SONY® 



ICX024AN-3 




V04 



Fig. 6 Vertical transfer clock waveform 

T = 564ns (with a horizontal driving frequency of 14.19 MHz) 

3. Horizontal transfer clock voltage 

1 ) For the horizontal transfer clocks "H<t>r and "H<j)2", the low-level period is expressed as "thl" and 
the high-level period is expressed as "thh". The symbol "tho" expresses the overlap period of "thl" 
and "thh". 

2) The low level at which "thl", "thh" and "tho" satisfy the following time duration is expressed as 
"Hib" and "H2b". 

And the high level is expressed as "Hia" and "H2a" 

thl > 10 ns, thh > 10 ns, tho > 5 ns 

A 21 =Hia-H 2 b 
A12 = H 2 a-Hib 

The smaller of A21 and A12 is defined as the horizontal transfer clock amplitude "V<|)h". The low 
level at that point is expressed as "W. 

3) The minimum level in the waveform which contains the coupling of the horizontal transfer clocks 
"H(|)i" and "H<()2" is expressed as "VW and the minimum level is expressed as "Vhhh". 



H2A , 


-*s / 








thh 




\ I "tho" 




/ \ r tiTi 


HtB -J 


J \ 





-H(42 



•H0| 



*H2B 



Fig. 7 Horizontal transfer clock waveform 



220 



SONY® 



ICX024AN-3 



4. Output reset clock voltage 

1 ) The low level of the output reset clock is to be the GND in the circuit. 

2) The amplitude of the output reset PG clock "V<t>PG" is defined as the maximum value of the 
amplitude which provides a high level period over 10 ns. 



More than 10 ns 



High level 



Low level 




V<|)PG 



V<|>PGL 



Fig. 8 Waveform of PG clock 



5. Substrate clock voltage 

1 ) Substrate voltage is expressed as <)>L, and the substrate clock waveform maximum value as <(>H. 

2) The period where voltage level turns to (<|)H-<|>L)/2 is expressed as tsr. The difference between <|>L 
and voltage level at tsr/2 is defined as the substrate clock voltage V<|)SUB. 




I 



Fig. 9 Substrate clock waveform 
Driving Clock Waveform Conditions 

1 . Definition of <|>h (1 00%) and <|>l (0%) 

1 ) For the horizontal transfer clocks (H<>1, H^), output reset clock (PG<)>) and vertical transfer clocks (V<|>1, 
V<|)2, V<|>3, V<|)4), the maximum value in the clock waveform which includes no coupling is expressed as 
"V and the minimum value is expressed as "<|>l". 

2) For the read clock (Vt), the maximum value in the clock waveform is expressed as "<|>h"."<|)l" expresses 
the voltage level while the read clock (Vt) of the vertical transfer clocks (V<)>1, V<t>z) is applied. 

3) For the substrate clock (SUB<|)), the maximum value in the clock waveform is expressed as "<|>h" and the 
substrate voltage (Vsub) as "<|>l". 



-221 - 



SONY® 



ICX024AN-3 



2. Standard driving clock conditions (Typ.) 
Horizontal drive frequency: 14.19 MHz 



Clock 
(Symbol) 


twh 


twl 


tr 


tf 


Unit 


Remarks 


H<>1 


18 


33.7 


10 


8 


ns 


Imaging period 


H<{>2 


18 


33.7 


10 


8 


H<))1 


4.9 




0.01 


0.01 


US 


Parallel-serial converting period 


H<|)2 




4.9 


0.01 


0.01 


<|)PG 


12 


53.7 


2 


2 


ns 




v<kv<|>2 


61.6 


1.6 


0.1 


0.1 


US 


Imaging period 


V(|)3/V<t)4 


2.8 


60.45 


0.05 


0.1 


V<j>T 


2.4 




0.2 


0.1 


Reading period 


SUB4> 


1.0 




0.08 


0.1 


Electron drained into substrate period 



f L ( %l 




Fig. 10 Clock waveform 



222- 



SONY® 










ICX024AN-3 


Imaging Characteristics 










(See Fig. 10.) 
Ta=25°C 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Testing method 


Remarks 


Sensitivity 


Sy 


150 


200 




mV 


1 




Output saturation signal 


Ysat 


500 






mV 


2 


Ta=55°C 


Smear 


SM 




0.007 


0.015 


% 


3 




Blooming margin 




1000 






times 


4 




Video signal shading 


SHy 






20 


/o 


5 


Zone 0, 1 






25 


% 


5 


Zone ct> to II' 


Uniformity between signal 
channels 


ASr 






10 


% 


6 




ASb 






10 


% 


6 




Dark signal 


Ydt 






2 


mV 


7 


Ta=55°C 


Dark signal shading 


AYdt 






1 


mV 


8 


Ta=55°C 


Flicker Y 


Fy 






2 


% 


9 




R-Y 


Fcr 






5 


% 


9 




B-Y 


Feb 






5 


% 


9 




Horizontal stripes R 


Lcr 






3.0 


% 


10 




G 


Leg 






3.0 


% 


10 




B 


Lcb 






3.0 


% 


10 




W 


Lew 






3.0 


% 


10 




Lag 


AYlag 






0.5 


% 


11 





I 



Test Circuit 



CCD output signal ® 



C.D.S I— AMP 



JUKI 



ruuui 



-@ Y signal output ® 




iPFg | — © Chroma signal output 



Note) Adjust AMP amplifier so that total gains between (A) and ® and between (§) and (C) equal 1 . 



-223 



SONY* 



ICX024AN-3 



Test Method 
Test conditions 

1) Through the following tests the substrate voltage should set to the value displayed on the device, 
while the device drive conditions should be kept within the range of the bias and clock voltage 
conditions. 

2) Through the following tests defects are excluded and, unless otherwise specified the optical black 
level (Hence forth referred to as OPB) is set as the reference for the signal output which is 
taken as the Y signal output or the Chroma signal output of the testing system. 

Color coding of CFA (Color Filter Array) & Composition of luminance (Y) and chrominance (C) 
signals. 



CFA of this imager is shown in the Figure. This 
complementary CFA is used with a "field integration 
mode", where all of the photosites are read out 
during each video field. Signals from two vertically 
adjacent photosites, such as line A1 or A2 for field 
A, are summed when the image charge is 
transferred into the vertical storage columns. The 
readout line pairing is shifted down one line for 
field B. The sensor output signals through 
Horizontal register (H reg.) at line A1 are 

[G+Cy], [Mg+Ye], [G+Cy], [Mg+Ye]. 



Cy 


Ye 


Cy 


Ye 


G 


Mg 


G 


Mg 


Cy 


Ye 


Cy 


Ye 


Mg 


G 


Mg 


G 


•4^ 4^ -V 4^ 











A1 



A2 



Hreg 



Color Coding Diagram 



These signals are processed in order to compose Y and C signals. By adding the two adjacent 
signals at line A1, Y signal is formed as follows: 

Y = {(G+Cy) + (Mg+Ye)} x 1/2 
= 1/2 {2B+3G+2R} 

C signal is composed by subtracting the two adjacent signals at line A1. 

R - Y = {(Mg+Ye) - (G+Cy)} 
= {2R-G} 

Next, the signals through H reg. at line A2 are 

[Mg+Cy], [G+Ye], [Mg+Cy], [G+Ye] 

Similarly, Y and C signals are composed at line A2. 

Y = {(G+Ye) + (Mg+Cy)} x 1/2 
= 1/2 {2B+3G+2R} 

-(B-Y) = {(G+Ye) - (Mg+Cy)} 
= -{2B-G} 

Accordingly, Y signal is balanced in relation to the scanning lines, and C signal takes the form of R-Y 
and -(B-Y) on alternate lines. 
It is the same for B field. 



224- 



SONYe ICX024AN-3 

Definition of standard imaging conditions 

© Standard imaging condition I: (As imaging device) Use a pattern box (luminance 706 Nit, 3200°K 
Halogen. source), at F5.6 with a typical test lens, and CM-500S (1.0 mmt) for IR cut filter. 

© Standard imaging condition II: Use a light source with uniformity within 2%, color temperature of 
3200°K and CM-500S (1.0 mmt) as IR cut filter. The light intensity is adjusted in accordance 
with the average value of Y signals (Ya) indicated in each item. 

1) Set to standard imaging condition I and measure Y signal (S) at the center of the screen. 

2) Set to imaging condition II. Adjust light intensity to 10 times when Y signal output average value 
YA=200mV. Then test Y signal Min. Value. 

3) Set to imaging condition II. Adjust light intensity to 500 times when Y signal output average value 
YA=200mV. Stop Read out clock. When the charge drain executed by the electronic shutter at the 
respective H blankings takes place, test the Max. value Ysm of Ysignal output. 

SM = (Ysm/Ya) x V500 x 710 x 100 (%) (V10V) 

4) Set to imaging condition II. Adjust light intensity to 1000 times when Y signal output average value 
Ya=200itiV. Then check that there is no blooming. 

5) Video signal shading SHy 

Set to standard imaging condition II. Test Y signal Max. (Y max.) and Min. (Y min.) values. 
Adjust light intensity to obtain a Y signal output average value (Ya) of about 150mV. 

SHy = (Ymax - Ymin)/YA x 100 (%) 

6) Set to standard imaging condition II. Adjust light intensity to obtain a Y signal output average value 
(Ya) of 200mA. Test the Max. (Cr max. and Cb max.) and Min. (Cr min. and Cb min.) values of 

C signals from R-Y and B-Y channels. 

ASr = | (Crmax - Crmin)/YA | x 100 (%) 
ASb = | (Cbmax - Cbmin)/Y A | x 100 (%) 

7) Test the average Y signal voltage when the device ambient temperature is at 55°C and light is 
obstructed with horizontal idle transfer level as reference. 

8) Following 7, test Max. (Ydmax.) and Min. (Ydmin.) values of Y signal output. Only keep spot 
defects out of this range. 

AYdt= Ydmax - Ydmin 



I 



225- 



SONY® 



ICX024AN-3 



9) © Fy 

Set to standard imaging condition II. Adjust light intensity to obtain a Y signal output average 
value (Ya) of 200 mV. Test the Y signal difference (AYf) between even field and odd field. 

Fy = (AYf/YA) x 100 (%) 

© Fcr, Feb 

Set to standard imaging condition II. Insert R and B filter respectively, and test the C signal 
difference (ACr, ACb) between even field and odd field and the C signal output average value 
(CAr, CAb). At that time, adjust light intensity to obtain a Y signal output average value (Ya) of 
100 mV. 

Fci = (ACi/CAi) x 100 (%) (i = r, b) 

10) Set to standard imaging condition II. Insert W, R, G and B filters respectively, and test the C 
Signal difference (AYIw, AYIr, AYIg, AYIb) between Y signal lines of the same field. At that time, 
adjust light intensity to obtain a Y signal output average value (Ya) of 100 mV. 

Lei = (AYM/Ya) x 100 (%) (i = w, r, g, b) 



1 1 ) Light a stroboscopic tube with the following timing and test the residual image. 
AYlag = (Ylag/Ys)x 100 (%) 



AYIag = (Ylag/Ys)x100(%) 



FLD 



SGI 



n n n fl 



SG2 



Jl 



Strobe light timing 



Output 



Ys 200mV Ylag (Residual image) 

ru.i._ru.i_n ru 



_n 




-226 



SONY® 



ICX024AN-3 



Drive Circuit 




I 



227 



SONY® 



ICX024AN-3 



Spectral Sensitivity Characteristics (Excluding light source characteristics) 
Fujinon lens H6 x 12.5R 



1.0- 







■ ' ' y 


fV ' ' 


..I, 


i i i i 


.9 
.8 








Ye 






.7 
.6 




/ Cy 


V G * 


. 






5 
.4 
.3 




~ > V— 




\ / 
\ / 
\ / 

Y — 







.2 






Mg 
















i i i i 






.Oh 


i i i i 


i i i i — |. 



500 600 

Wave length [nm] 



Using read out clock timing chart 



J~\ 



<EVEN FIEI_0> 



Unit: |iS 



228 



SONY® 



ICX024AN-3 



O 




r 



I 



229 



SONY® 



ICX024AN-3 



Handling Instructions 

1 ) Static charge prevention 

CCD image sensor are easily damaged by static discharge. Before handling be sure to take the 
following protective measures. 

a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use 
conductive shoes. 

b) When handling directly use an earth band. 

c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. 

d) Ionized air is recommended for discharge when handling CCD image sensor. 

e) For the shipment of mounted substrates use boxes treated for the prevention of static charges. 

2) Soldering 

a) Make sure the package temperature does not exceed 80°C. 

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 
grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and 
remount cool sufficiently. 

c) To dismount an imaging device do not use a solder pult. When using an electric desoldering 
tool use a thermal controller of the zero cross On/Off type and connect to ground. 

3) Dust and dirt protection 

a) Operate in clean environments (around class 1000 will be appropriate). 

b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. 
Should dirt stick to a glass surface blow it off with an air blow. (For dirt stuck through static 
electricity ionized air is recommended) 

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not 
to scratch the glass. 

d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool 
when moving to a room with great temperature differences. 

e) When a protective tape is applied before shipping, just before use remove the tape applied for 
electrostatic protection. Do not reuse the tape. 

4) Do not expose to strong light (sun rays) for long periods, color filters are discolored. 

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage 
or usage in such conditions. 

6) CCD image sensor are precise optical equipment that should not be subject to mechanical shocks. 

7) Defect compensation ROM 

This is shipped in its own case in pair with the CCD image sensor. Pair with the CCD image 
sensor bearing the same serial number during mounting. When the CCD image sensor has no 
defect there is no ROM or serial number. 



230- 



SONY® 



ICX026BK 



Solid-State Image Sensor for Color Camera 



Description 

ICX026BK is an interline transfer CCD solid-state 
imager suitable for NTSC 1/2 inch color video 
cameras. High sensitiveness is achieved through the 
adoption of Ye, Cy, Mg and G complementary color 
mosaic filters and HAD (Hole Accumulated Diode) 
sensors. 

This chip features a field integration read out 
system and an electronic shutter with variable 
charge-storage time. 

Features 

• High sensitivity (+6 dB compare with ICX026AK) 

• Optical size 1/2 inch format 

• Field integration read out system 

• Low dark current 

• Ye, Cy, Mg, G on chip type complementary color 
mosaic filter. 

• Horizontal register 5V drive 

• High antiblooming 

• Low smear 

• Variable speed electronic shutter 

Device Structure 

• Number of effective pixels 51 (H) x 492 (V) 

• Number of total pixels 537 (H) x 505 (V) 

• Interline transfer CCD image sensor 

• Chip size 7.84 mm (H) x 6.40 mm (V) 

• Unit cell size 1 2.7 ^m (H) x 9.8 urn (V) 

• Optical black 

Horizontal (H) direction 
Vertical (V) direction 

• Number of dummy bits 

Horizontal 16 

Vertical 1 (even field only) 

• Substrate material silicon 



Package Outline 



Unit: mm 



20 pins DIP (Ceramic) 



18.0»°3 




s Effective picture elements center 



Front 2 pixels Rear 25 pixels 
Front 1 2 pixels Rear 1 pixels 





I 



(pin 11) 2 25 

Optical black position (Top View) 



Block Diagram 




Note) -□ : Photo sensor 



Vl H01 H02 GND 



E89405-YA 



-231 - 



SONY® 



ICX026BK 



Pin Configuration (Top View) 



(20)GND 

©H02 

©H01 

@PG 

®VL 

©PD 

©GND 

©Vss 

©VGG 

60 V OUT 



Pin Description 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V<|)4 


Vertical register transfer clock 


11 


Vout 


Signal output 


2 


V<)>3 


Vertical register transfer clock 


12 


Vgg 


Output amplifier gate bias 


3 


V<|)2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (Overflow drain) 


14 


GND 


GND 


5 


GND 


GND 


15 


PD 


Precharge drain bias 


6 


V<|>1 


Vertical register transfer clock 


16 


Vl 


Protective transistor bias 


7 


Vl 


Protective transistor bias 


17 


PG 


Precharge gate clock 


8 


GND 


GND 


18 


H<|>1 


Horizontal register transfer clock 


9 


Vddi 


Output amplifier drain supply 


19 


H<)>2 


Horizontal register transfer clock 


10 


Vdd2 


Output amplifier drain supply 


20 


GND 


GND 



Absolute Maximum Ratings 

• Substrate voltage SUB - GND 

• Supply voltage 



• Clock input voltage 



Vddi, Vdd2, PD, Vout, Vss, - GND 
Vddi, Vdd2, PD, Vout, Vss, - SUB 
V<)>1, V<|>2, V<)>3, V(|>4, H<|>1, H<>2 - GND 
V<)>1, V<|)2, V<)3, V<H, H<|>1, H<>2 - SUB 

• Voltage difference between vertical clock input pins 

• Voltage difference between horizontal clock input pins 

• H<t)i, H<|>2, - V<(>4, 

• PG, Vgg - GND 

• PG, Vgg - SUB 

• Vl - SUB 

• Beside GND, SUB, Vl - Vl 

• Storage temperature 

• Operating temperature 

♦Note) +27 V (Max.) when clock width < 1 us, duty factor < 0. 1 %. 



-0.3 to +55 V 




-0.3 to +18 V 




-55 to +10 V 




-15 to +20 V 




-65 to +10 V 




+15 V*(Max.) 


+17 V 


(Max.) 


-17 to +17 V 




-10 to +15 V 




-55 to +10 V 




-65 to +0.3 V 




-0.3 to +30 V 




-30 to +80 °C 




-10 to +55 °C 





-232 



SONY® 



ICX026BK 



Bias Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain voltage 


VDD1, VDD2 


14.55 


15.0 


15.45 


V 


VDD1 = VDD2 


Precharge drain voltage 


Vpd 


14.55 


15.0 


15.45 


V 


Vpd = Vddi = Vdd2 


Output amplifier gate voltage 


Vgg 


1.75 


2.0 


2.25 


V 




Output amplifier source 


Vss 


Ground through 680 Q resistor 


±5% 


Substrate voltage adjustment 
range 


VSUB 


7 




19 


V 


*1 


Fluctuation range after 
substrate voltage adjustment 


N/SUB 


-3 




+3 


% 




Protective transistor bias 


Vl 


*2 





DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain current 


Idd 




2.5 




mA 


Idd = Iddi + Idd2 


Input current 


llM 






1 


HA 


*3 


Input current 


llN2 






10 


^A 


*4 



Note) *1. Substrate voltage (Vsub) setting value display. 

Substrate voltage setting value is displayed at the back of the device through a code 
address. Adjust so as to obtain the displayed voltage at SUB pin. 

Vsub code address - two digits display 



D 


□ 


t 


t 


Integral part . 


Decimal part 



I 



The relation between code address of integral part and actual numerical values. 



Code address of 
integral part 


7 


8 


9 


A 


B 


C 


D 


E 


F 


G 


H 


I 


J 


Numerical value 


7 


8 


9 


10 


11 


12 


13 


14 


15 


16 


17 


18 


19 



<Example> F5 -> 15.5 (V) 
*2. Vl setting is Vvl of the vertical transfer clock waveform. 

*3. 1) Current to earth when 18V is applied to pins Vddi, Vdd2, Vout, Vss and SUB pin. 
However, pins that are not tested are grounded. 

2) Current to earth when 20V is sequentially applied to pins V<|>1, V<|>2, V<|>3, V<K H<|)1, and 
H(|>2. However, 20V is applied to SUB while pins that are not tested are grounded. 

3) Current to earth when 15V is sequentially applied to pins PG and Vgg. However, 15V 
is applied to SUB while pins that are not tested are grounded. 

*4. 1) Current to earth when 55V is applied to SUB pin. Pins that are not tested are 
grounded. 
2) Current to earth when Vl is grounded, GND and SUB are open and 30V is applied to 
other pins. 



233- 



SONY® 



ICX026BK 



Clock Voltage Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


No. 


Remarks 


Read out clock voltage 


Vvt 


14.3 


15.0 


15.7 


V 


2,6 


*1 


Vertical transfer clock voltage *2 


VVH1 , VVH2,VVH3, VVH4 


-0.2 





0.2 


V 


1,2,3,6 


VvH=(VvH1+VvH2)/2 




VVU ,VVL2,VVL3,VVL4 


-9.6 


-9.0 


-8.3 


V 


1,2,3,6 


VVL=(VvL3+VvL4)/2 




V<|)V 


8.1 


9.0 


9.8 


V 


1,2,3,6 


Vi|)v=VvHn-VvLn (n=1 to 4) 




| VVH1 - VVH2 | 






0.2 


V 


3,6 






VVH3 - VVH 


-0.4 




0.1 


V 


2,3,6 






VVH4 - VVH 


-0.4 




0.1 


V 


1,3,6 






VVHH 






0.8 


V 


1,2,3,6 


High level coupling 




VVHL 






1.0 


V 


1,2,3,6 


High level coupling 




VVLH 






0.8 


V 


1,2,3,6 


Low level coupling 




VVLL 






0.8 


V 


1,2,3,6 


Low level coupling 


Horizontal transfer clock voltage 


V(|)H 


4.7 


5.0 


5.3 


V 


18,19 


*3 




Vhl 


-0.05 





0.05 


V 


18,19 




Precharge gate clock voltage 


V<(>PG 


8.0 




11.5 


V 


17 


*4 




Vpgl 


-0.1 





0.1 


V 


17 




Substrate clock voltage 


V())SUB 


23.0 




34.0 


V 


4 


*5 



Note) *1. See Fig. 1. 

*2. See Fig. 2. 

*3. See Fig. 3. 

*4. See Fig. 3. 

*5. See Fig. 4. 

Clock Equivalent Circuit Constant 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Capacitance between vertical transfer clock and GND 


C<|>vi, C<t>v3 




1000 




pF 




Capacitance between vertical transfer clock and GND 


C<|>V2, C<|>V4 




1200 




pF 




Capacitance between vertical transfer clocks 


C<|>V12, C<|>V34 




1200 




pF 




Capacitance between vertical transfer clocks 


C<|>V23, C((>V41 




750 




PF 




Capacitance between horizontal transfer clock and GND 


C<|>H1, C<|>H2 




70 




pF 




Capacitance between horizontal transfer clocks 


C<|>HH 




50 




PF 




Capacitance between precharge gate clock and GND 


C<|>PG 




8 




pF 




Capacitance between substrate clock and GND 


C<|>SUB 




400 




pF 




Vertical transfer clock serial resistor 


Ri,R2,R3,R4 




33 




Q 




Vertical transfer clock ground resistor 


Rgnd 




15 




a 




Horizontal transfer clock serial resistor 


R<)>H 




10 




a 





Wh 



OV4I t- 



V«*2 




V*4 V*3 

Vertical transfer clock equivalent circuit 



H*i o — *M — r 



CVm -r 



—II- 

C*HH 



R*>H 
-WV ° H*2 



T OH2 



Horizontal transfer clock equivalent circuit 



234 



SONY® 



ICX026BK 



Drive Clock Waveform Conditions 

1. Read out clock waveform 

100% 

90% 




tWh 



OV 



Fig.1 



2. Vertical transfer clock waveform 



V<|)1 



"fe 



VVHH wuyy 

._ VVH VVHH 




V(|)2 




V<))3 




I 



V<))4 



VVHH VVHH 



_ V £_J____l 




Fig.2 



-235 



SONY® 



ICX026BK 



3. Horizontal transfer clock waveform/Precharge gate clock waveform 



Vhl.Vpgl- 




4. Substrate clock waveform 



Fig. 3 



VsuB 




Fig. 4 



Item 


Symbol 


twh 


twl 


tr 


tf 


Unit 


Remarks 


Min. 


Typ. 


Max 


Min. 


Typ. 


Max 


Min. 


Typ. 


Max 


Min. 


Typ. 


Max 


Read out clock 


Vt 


1.5 


1.85 














0.5 






0.5 


MS 


During read out 


Vertical transfer clock 


V(>1 ,V<(»2,V<t>3, V<))4 


















0.45 


0.015 




0.25 


US 


* 


Horizontal transfer clock 


H«|» 


37 


41 




38 


42 






12 


15 




10 


15 


ns 


During imaging 


Horizontal transfer clock 


H«|»1 




5.6 












0.012 






0.01 




US 


During parallel serial 
conversion. 


Horizontal transfer clock 


H<|>2 










5.6 






0.012 






0.01 




|iS 


During parallel serial 
conversion. 


Precharge gate clock 


<|)PG 


15 


17 




75 


81 






4 






3 




ns 




Substrate clock 


0SUB 


1.5 


2.1 














0.5 






0.5 


US 


During charge drain. 



"Note) When vertical transfer clock driver CXD1250 is in use. 



236- 



SONY® 








ICX026BK 


Operating Characteristics 








Ta = 25°C 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test 
method 


Remarks 


Sensitivity 


S 


260 


340 




mV 


1 


Ta=55°C 


Saturation signal 


Ysat 


500 






mV 


2 




Smear 


SM 




0.005 


0.015 


% 


3 




Blooming margin 




1000 






times 


4 




Video signal shading 


SHy 






20 


% 


5 


ZoneO, I 






25 


% 


5 


ZoneO to II' 


Uniformity between signal 
channels 


ASr 






10 


% 


6 




ASb 






10 


% 


6 




Dark signal 


Ydt 






2 


mV 


7 


Ta=55°C 


Dark signal shading 


AYdt 






1 


mV 


8 


Ta=55°C 


Flicker Y 


Fy 






2 


% 


g 




Flicker R-Y 


Fcr 






5 


% 


9 




Flicker B-Y 


Feb 






5 


% 


9 




Horizontal stripes R 


Lcr 






4 


% 


10 




Horizontal stripes G 


Leg 






4 


% 


10 




Horizontal stripes B 


Lcb 






4 


% 


10 




Horizontal stripes W 


Lew 






4 


% 


10 




Lag 


AYlag 






0.5 


% 


11 





Zone chart of Video signal shading 







t 9 . 






67 


J 151 








65 


10 




ZONE 0,1 




ive picture 


j )52 ZONE 


nX 


snts 




10* ^Z0 


nf m 



I 



Testing System 



® 

®CCD output signal 



CCD 



C.D.S. 



■^H 



JL 



© 

-© Y signal output 



© 
.PF2|— ® Chroma signal output 



Note) Adjust AMP amplifier so that total gains between (A) and ® and between ® and (5) equal 1 . 



-237- 



SONY® 



ICX026BK 



Test Method 
Test conditions 

1 ) Through the following tests the substrate voltage should set to the value displayed on the device, 
while the device drive conditions should be kept within the range of the bias and clock voltage 
conditions. 

2) Through the following tests defects are excluded and, unless otherwise specified the optical black 
level (Hence forth referred to as OPB) is set as the reference for the signal output which is 
taken as the Y signal output or the Chroma signal output of the testing system. 

Color coding of CFA (Color Filter Array) & Composition of luminance (Y) and chrominance (C) 
signals. 



CFA of this imager is shown in the Figure. This 
complementary CFA is used with a "field integration 
mode", where all of the photosites are read out 
during each video field. Signals from two vertically 
adjacent photosites, such as line A1 or A2 for field 
A, are summed when the image charge is 
transferred into the vertical storage columns. The 
readout line pairing is shifted down one line for 
field B. The sensor output signals through the 
horizontal register (H reg.) at line A1 are 

[G+Cy], [Mg+Ye], [G+Cy], [Mg+Ye]. 



Cy 


Ye 


Cy 


Ye 


G 


Mg 


G 


Mg 


Cy 


Ye 


Cy 


Ye 


Mg 


G 


Mg 


G 


■A- 4* -*' 4" 











A1 



A2 



Hreg 



Color Coating Diagram 



These signals are processed in order to compose Y and C signals. By adding the two adjacent 
signals at line A1, Y signal is formed as follows: 

Y = {(G+Cy) + (Mg+Ye)} x 1/2 
= 1/2 {2B+3G+2R} 

C signal is composed by subtracting the two adjacent signals at line A1. 

R - Y = {(Mg+Ye) - (G+Cy)} 
= {2R-G} 

Next, the signals through H reg. at line A2 are 

[Mg+Cy], [G+Ye], [Mg+Cy], [G+Ye] 

Similarly, Y and C signals are composed at line A2. 

Y = {(G+Ye) + (Mg+Cy)} x 1/2 
= 1/2 {2B+3G+2R} 

-(B-Y) = {(G+Ye) - (Mg+Cy)} 
= -{2B-G} 

Accordingly, Y signal is balanced in relation to the scanning lines, and C signal takes the form of R-Y 
and -(B-Y) on alternate lines. 
It is the same for B field. 



238 



SONY® ICX026BK 

Definition of standard imaging conditions 

© Standard imaging condition I: (As imaging device) Use a pattern box (luminance 706 Nit, 3200°K 
Halogen source), at F5.6 with a typical test lens, and CM-500S (1.0 mmt) for IR cut filter. 

@ Standard imaging condition II: Use a light source with uniformity within 2%, color temperature of 
3200°K and CM-500S (1.0 mmt) as IR cut filter. The light intensity is adjusted in accordance 
with the average value of Y signals (Ya) indicated in each item. 

1 ) Set to standard imaging condition I and measure Y signal (S) at the center of the screen. 

2) Set to imaging condition II. Adjust light intensity to 10 times when Y signal output average value 
YA=150mV. Then test Y signal Min. Value. 

3) Set to imaging condition II. Adjust light intensity to 500 times when Y signal output average value 
YA=150mV. Stop Read out clock. When the charge drain executed by the electronic shutter at the 
respective H blankings takes place, test the Max. value Ysm of Ysignal output. 

SM = (Ysm/Ya) x V500 x V10 x 100 (%) (V10V) 

4) Set to imaging condition II. Adjust light intensity to 1 000 times when Y signal output average value 
YA=150mV. Then check that there is no blooming. 

5) Video signal shading SHy 

Set to standard imaging condition II. Test Y signal Max. (Y max.) and Min. (Y min.) values. 
Adjust light intensity to obtain a Y signal output average value (Ya) of about 150mV. 

SHy = (Ymax- Ymin)/YA x 100 (%) 

6) Set to standard imaging condition II. Adjust light intensity to obtain a Y signal output average value 
(Ya) of 150mV. Test the Max. (Cr max. and Cb max.) and Min. (Cr min. and Cb min.) values of 

C signals from R-Y and B-Y channels. 

ASr = | (Crmax - Crmin)/YA | x 100 (%) 
ASb = | (Cbmax - Cbmin)/YA | x 100 (%) 

7) Test the average Y signal voltage when the device ambient temperature is at 55°C and light is 
obstructed with horizontal idle transfer level as reference. 

8) Following 7, test Max. (Yd max.) and Min. (Yd min.) values of Y signal output. Only keep spot 
defects out of this range. 

AYdt= Ydmax - Ydmin 



I 



239- 



SONY® 



ICX026BK 



9) © Fy 

Set to standard imaging condition II. Adjust light intensity to obtain a Y signal output average 
value (Ya) of 150 mV. Test the Y signal difference (AYf) between even field and odd field. 

Fy = (AYf/YA) x 100 (%) 

® Fcr, Feb 

Set to standard imaging condition II. Insert R and B filter respectively, and test the C signal 
difference (ACr, ACb) between even field and odd field and the C signal output average value 
(CAr, CAb). At that time, adjust light intensity to obtain a Y signal output average value (Ya) of 
100 mV. 

Fci = (ACi/CAi) x 100 (%) (i = r, b) 

10) Set to standard imaging condition II. Insert W, R, G and B filters respectively, and test the signal 
difference (AYIw, AYIr, AYIg, AYIb) between Y signal lines of the same field. At that time, adjust 
light intensity to obtain a Y signal output average value (Ya) of 100 mV. 

Lei = (AYM/Ya) x 100 (%) (i = w, r, g, b) 

1 1 ) Light a stroboscopic tube with the following timing and test the residual image. 
AYlag = (Ylag/Ys)x 100 (%) 



FLD 



SG1 



_Il 



JI L 



SG2 



_J H 



Strobe light timing 



Output 




Y lag (Residual image) 

^ n n 

t 



240- 



SONY® 



ICX026BK 




I 



-241 - 



SONY® 



ICX026BK 



Spectral Sensitivity Characteristics 

(Excluding light source characteristics, including lens characteristics) 




400 



Using read out clock timing chart 



500 600 

Wave Length [nm] 



700 



Odd Field < 



HD 



V1 
V2 



V3 
V4 



V1 
V2 



Even Field •< 



V3 
V4 



J L 



Unites 



-242 



SONY® 



ICX026BK 



S 

£ 
' Z 

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S2S 















(0 in 


* 


to 


PJ 


- 



0) 0) 



:j 



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cvj 










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«— 


(VI 


ro 


■<t 


U 3 


<rt 


</) 


> 


> 


> 


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OO 



243 



SONY® 



ICX026BK 



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-244 



SONY® ICX026BK 

Handling Instructions 

1 ) Static charge prevention 

CCD image sensor are easily damaged by static discharge. Before handling be sure to take the 
following protective measures. 

a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use 
conductive shoes. 

b) When handling directly use an earth band. 

c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. 

d) Ionized air is recommended for discharge when handling CCD image sensor. 

e) For the shipment of mounted substrates use boxes treated for the prevention of static charges. 

2) Soldering 

a) Make sure the package temperature does not exceed 80°C. 

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 
grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and 
remount cool sufficiently. 

c) To dismount an imaging device do not use a solder pult. When using an electric desoldering 
tool use a thermal controller of the zero cross On/Off type and connect to ground. 

3) Dust and dirt protection 

a) Operate in clean environments (around class 1 000 will be appropriate). 

b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. 
Should dirt stick to a glass surface blow it off with an air blow. (For dirt stuck through static 
electricity ionized air is recommended) 

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not 
to scratch the glass. 

d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool 
when moving to a room with great temperature differences. 

e) When a protective tape is applied before shipping, just before use remove the tape applied for 
electrostatic protection. Do not reuse the tape. 

4) Do not expose to strong light (sun rays) for long periods, color filters are discolored. 

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage 
or usage in such conditions. 

6) CCD image sensor are precise optical equipment that should not be subject to mechanical shocks. 



-245- 



SONY® 



ICX027BK 



Solid-State Image Sensor for Color Camera 



Description 

ICX027BK is an interline transfer CCD solid-state 
imager suitable for PAL 1/2 inch color video cameras. 
High sensitiveness is achieved through the adoption 
of Ye, Cy, Mg and G complementary color mosaic 
filters and HAD (Hole Accumulated Diode) sensors. 

This chip features a field integration read out 
system and an electronic shutter with variable 
charge-storage time. 

Features 

• High sensitivity (+6 dB compare with ICX027AK) 
•.Optical size 1/2 inch format 

• Field integration read out system 

• Low dark current 

• Ye, Cy, Mg, G on chip type complementary color 
mosaic filter. 

• Horizontal register 5V drive 

• High antiblooming 

• Low smear 

• Variable speed electronic shutter 



Package Outline 



Unit: mm 



20pin DIP (Ceramic) 



18.0">3 




Effective picture 
elements center 




J0.46 



Device Structure 

• Number of effective pixels 500 (H) x 582 (V) 

• Number of total pixels 537 (H) x 597 (V) 

• Interline transfer CCD image sensor 

• Chip size 7.84 mm (H) x 6.40 mm (V) 

• Unit cell size 1 2.7 urn (H) x 8.3 urn (V) 

• Optical black 

Horizontal (H) direction Front 7 pixels Rear 30 pixels 
Vertical (V) direction Front 14 pixels Rear 1 pixels 

• Number of dummy bits 

Horizontal 1 6 

Vertical 1 (even field only) 

• Substrate material silicon 

Block Diagram 



(pin 1) 




(pin 11) 7 H 30 
Optical black position (Top View) 




*Note)— □ : Photo sensor 



E89406-YA 



-246- 



SONY® 



ICX027BK 



Pin Configuration (Top View) 



V04M) . n 


@)GND 


V03© 


@)H02 


V02Qp 


©H01 


SUB® 


(j7)PG 


GND® 


©VL 


V01 


©PD 


Vl ® 


©GND 


GND® 


@vss 


Vddi© 


©VGG 


VDD2(io) ~, 


(jpVOUT 



Pin Description 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V<|>4 


Vertical register transfer clock 


11 


Vout 


Signal output 


2 


V(|>3 


Vertical register transfer clock 


12 


Vgg 


Output amplifier gate bias 


3 


V<>2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (Overflow drain) 


14 


GND 


GND 


5 


GND 


GND 


15 


PD 


Precharge drain bias 


6 


V<>1 


Vertical register transfer clock 


16 


Vl 


Protective transistor bias 


7 


Vl 


Protective transistor bias 


17 


PG 


Precharge gate clock 


8 


GND 


GND 


18 


H<t>i 


Horizontal register transfer clock 


9 


Vddi 


Output amplifier drain supply 


19 


H<|>2 


Horizontal register transfer clock 


10 


VDD2 


Output amplifier drain supply 


20 


GND 


GND 



I 



Absolute Maximum Ratings 



Substrate voltage 
Supply voltage 

Clock input voltage 



SUB- GND 

Vddi, Vdd2, PD, Vout, Vss, - GND 
Vddi, Vdd2, PD, Vout, Vss, - SUB 
V01, V<)>2, V<t)3, V<M, H<>1 , H<)2 - GND 
V<(»1 , V<))2, V<t>3, V<|>4, H(>1 , H<>2 - SUB 

• Voltage difference between vertical clock input pins 

• Voltage difference between horizontal clock input pins 

• H<)>1, H<|)2, - V(|>4, 

• PG, Vgg - GND 

• PG, Vgg - SUB 

• Vl - SUB 

• Beside GND, SUB, Vl - Vl 

• Storage temperature 

• Operating temperature 

♦Note) +27 V (Max.) when clock width < 1 us, duty factor < 0.1%. 



-0.3 to +55 V 




-0.3 to +18 V 




-55 to +10 V 




-15 to +20 V 




-65 to +10 V 




15 V* 


(Max. 


17 V 


(Max. 


-17 to +17 V 




-10 to +15 V 




-55 to +10 V 




-65 to +0.3 V 




-0.3 to +30 V 




-30 to +80°C 





-10 to +55°C 



-247- 



SONY® 



ICX027BK 



Bias Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain voltage 


VDD1, VDD2 


14.55 


15.0 


15.45 


V 


Vddi = VDD2 


Precharge drain voltage 


Vpd 


14.55 


15.0 


15.45 


V 


Vpd = Vddi = Vdd2 


Output amplifier gate voltage 


Vgg 


1.75 


2.0 


2.25 


V 




Output amplifier source 


Vss 


Ground through 680 fi resistor 


±5% 


Substrate voltage adjustment 
range 


VSUB 


7 




19 


V 


*1 


Fluctuation range after 
substrate voltage adjustment 


VSUB 


-3 




+3 


% 




Protective transistor bias 


Vl 


*2 





DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain current 


Idd 




2.5 




mA 


Idd = Iddi + Idd2 


Input current 


Iini 






1 


HA 


*3 


Input current 


llN2 






10 


RA 


*4 



Note) *1. Substrate voltage (Vsub) setting value display. 

Substrate voltage setting value is displayed at the back of the device through a code 
address. Adjust so as to obtain the displayed voltage at SUB pin. 



Vsub code address - two digits display 



□ 


D 


t 


t 


Integral part 


Decimal part 



The relation between code address of integral part and actual numerical values. 



Code address of 
integral part 


7 


8 


9 


A 


B 


C 


D 


E 


F 


G 


H 


I 


J 


Numerical Value 


7 


8 


9 


10 


11 


12 


13 


14 


15 


16 


17 


18 


19 



<Example> F5 -> 15.5 (V) 
*2. Vl setting is Vvl of the vertical transfer clock waveform. 

*3. 1) Current to earth when 18V is applied to pins Vddi, Vdd2, Vout, Vss and SUB pin. 
However, pins that are not tested are grounded. 

2) Current to earth when 20V is sequentially applied to pins V<>1, V<j>2, V<|)3, V<|>4, H<>1, and 
H<|>2. However, 20V is applied to SUB while pins that are not tested are grounded. 

3) Current to earth when 15V is sequentially applied to pins PG and Vgg. However, 15V 
is applied to SUB while pins that are not tested are grounded. 

*4. 1) Current to earth when 55V is applied to SUB pin. Pins that are not tested are 
grounded. 
2) Current to earth when Vl is grounded, GND and SUB are open and 30V is applied to 
other pins. 



-248 



SONY® 














ICX027BK 


Clock Voltage Conditions 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


No. 


Remarks 


Read out clock voltage 


Vvt 


14.3 


15.0 


15.7 


V 


2,6 


*1 


Vertical transfer clock voltage *2 


VVH1 ,VVH2,VVH3,VVH4 


-0.2 





0.2 


V 


1 ,2,3,6 


VvH=(VvH1+VvH2)/2 




VvU ,VVL2,VVL3, VVL4 


-9.6 


-9.0 


-8.3 


V 


1,2,3,6 


VvL=(VvL3+VvL4)/2 




V(()V 


8.1 


9.0 


9.8 


V 


1,2,3,6 


V<t>v=VvHn-VvLn (n=1 


to 4) 




| VVH1 - VVH2 | 






0.2 


V 


3,6 






VVH3 - VVH 


-0.4 




0.1 


V 


2,3,6 






WH4 - VVH 


-0.4 




0.1 


V 


1,3,6 






VVHH 






0.8 


V 


1,2,3,6 


High level coupling 




VVHL 






1.0 


V 


1,2,3,6 


High level coupling 




VVLH 






0.8 


V 


1,2,3,6 


Low level coupling 




VVLL 






0.8 


V 


1 ,2,3,6 


Low level coupling 


Horizontal transfer clock voltage 


V<|>H 


4.7 


5.0 


5.3 


V 


18,19 


*3 




Vhl 


-0.05 





0.05 


V 


18,19 




Precharge gate clock voltage 


V(>PG 


8.0 




11.5 


V 


17 


*4 




Vpgl 


-0.1 





0.1 


V 


17 




Substrate clock voltage 


V(|>SUB 


23.0 




34.0 


V 


4 


*5 



Note) *1. See Fig. 1. 

*2. See Fig. 2. 

*3. See Fig. 3. 

*4. See Fig. 3. 

*5. See Fig. 4. 

Clock Equivalent Circuit Constant 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Capacitance between vertical transfer clock and GND 


C<t>vi, C<|>v3 




1000 




PF 




Capacitance between vertical transfer clock and GND 


C0V2, C<(>V4 




1200 




PF 




Capacitance between vertical transfer clocks 


C0V12, C<|>V34 




1400 




PF 




Capacitance between vertical transfer clocks 


C<|>V23, C<|>V41 




900 




PF 




Capacitance between horizontal transfer clock and GND 


C<tJH1, C<|>H2 




70 




PF 




Capacitance between horizontal transfer clocks 


C<)>HH 




50 




PF 




Capacitance between precharge gate clock and GND 


C<|>PG 




8 




PF 




Capacitance between substrate clock and GND 


C(|>SUB 




400 




PF 




Vertical transfer clock serial resistor 


Ri,R2,R3,R4 




33 




n 




Vertical transfer clock ground resistor 


Rgnd 




15 




a. 




Horizontal transfer clock serial resistor 


R<|>H 




10 




Q. 





I 



V«M 



V«*2 




C^v« ^ 



h*i o — Wf — r 



C*>m =f 



W-4 V*3 

Vertical transfer clock equivalent circuit 



-HI- 

C*>HH 



R*»H 

-AM ° H*2 



-r Oh2 



Horizontal transfer clock equivalent circuit 



249- 



SONY® 



ICX027BK 



Drive Clock Waveform Conditions 



1. Read out clock waveform 




2. Vertical transfer clock waveform 



Fig.1 



ov 




V<t>3 




V<|>2 



V04 




VVMH VVHM 




Fig.2 



250 



SONY® 



ICX027BK 



3. Horizontal transfer clock waveform/Precharge gate clock waveform 



Vhl.Vpgl 



4. Substrate clock waveform 




Fig. 3 




. iov. 

VsoB — »- •/« 



I 



Fig. 4 



Item 


Symbol 


twh 


twl 


tr 


tf 


Unit 


Remarks 


Min. 


Typ. 


Max 


Min. 


Typ. 


Max 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max 


Read out clock 


Vt 


1.5 


1.85 














0.5 






0.5 


MS 


During read out 


Vertical transfer clock 


V<t>1 ,V<|>2,V<|>3,V<t>4 


















0.45 


0.015 




0.25 


US 


* 


Horizontal transfer clock 


H0 


38 


42 




38 


42 






12 


15 




10 


15 


ns 


During imaging 


Horizontal transfer clock 


H<|>1 




5.6 












0.012 






0.01 




MS 


During parallel serial 
conversion. 


Horizontal transfer clock 


H(|>2 










5.6 






0.012 






0.01 




US 


During parallel serial 
conversion. 


Precharge gate clock 


())PG 


15 


17 




76 


82 






4 






3 




ns 




Substrate clock 


(J>SUB 


1.5 


2.1 














0.5 






0.5 


J1S 


During charge drain. 



*Note) When vertical transfer clock driver CXD1250 is in use. 



251 



SONY® ICX027BK 


Operating Characteristics Ta = 25°C 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test 
method 


Remarks 


Sensitivity 


S 


240 


320 




mV 


1 




Saturation signal 


Ysat 


450 






mV 


2 


Ta=55°C 


Smear 


SM 




0.005 


0.015 


% 


3 




Blooming margin 




1000 






times 


4 




Video signal shading 


SHy 






20 


% 


5 


ZonO, I 






25 


% 


5 


ZoneO to II' 


Uniformity between signal 
channels 


ASr 






10 


% 


6 




ASb 






10 


% 


6 




Dark signal 


Ydt 






2 


mV 


7 


Ta=55°C 


Dark signal shading 


AYdt 






1 


mV 


8 


Ta=55°C 


Flicker Y 


Fy 






2 


% 


9 




Flicker R-Y 


Fcr 






5 


% 


9 




Flicker B-Y 


Feb 






5 


% 


9 




Horizontal stripes R 


Lcr 






4 


% 


10 




Horizontal stripes G 


Leg 






4 


% 


10 




Horizontal stripes B 


Lcb 






4 


% 


10 




Horizontal stripes W 


Lew 






4 


% 


10 




Lag 


AYlag 






0.5 


% 


11 





Zone chart of Video signal shading 



Effective picture 
elements 



ZONE 0,1 

ZONEHJ' 



Testing System 



® 

©CCD output signal 



CCD 



C.D.S. — Hamp. 



LPFi 



-S^H 



JL 



© 

-® Y signal output 



© 



LPF2|— @ Chroma signal output 



Note) Adjust AMP amplifier so that total gains between (§) and ® and between (§) and © equal 1 . 



252- 



SONY® 



ICX027BK 



Test Method 
Test conditions 

1 ) Through the following tests the substrate voltage should set to the value displayed on the device, 
while the device drive conditions should be kept within the range of the bias and clock voltage 
conditions. 

2) Through the following tests defects are excluded and, unless otherwise specified, the optical black 
level (Hence forth referred to as OPB) is set as the reference for the signal output which is 
taken as the Y signal output or the Chroma signal output of the testing system. 

Color coding of CFA (Color Filter Array) & Composition of luminance (Y) and chrominance (C) 
signals. 



CFA of this imager is shown in the Figure. This 
complementary CFA is used with a "field integration 
mode", where all of the photosites are read out 
during each video field. Signals from two vertically 
adjacent photosites, such a% line A1 or A2 for field 
A, are summed when the image charge is 
transferred into the vertical storage columns. The 
readout line pairing is shifted down one line for 
field B. The sensor output signals through the 
horizontal register (H reg.) at line A1 are 

[G+Cy], [Mg+Ye], [G+Cy], [Mg+Ye]. 



9l 


Ye 


Cy 


Ye 


~g1 


Mg 


G 


Mg 


% 


Ye 


Cy 


Ye 


Mg 


G 


Mg 


G 


-v 4' 4- 4- 











A1 



A2 



Hreg 



Color Coating Diagram 



These signals are processed in order to compose Y and C signals. By adding the two adjacent 
signals at line A1, Y signal is formed as follows: 

Y = {(G+Cy) + (Mg+Ye)} x 1/2 
= 1/2 {2B+3G+2R} 

C signal is composed by subtracting the two adjacent signals at line A1. 

R - Y = {(Mg+Ye) - (G+Cy)} 
= {2R-G} 

Next, the signals through H reg. at line A2 are 

[Mg+Cy], [G+Ye], [Mg+Cy], [G+Ye] 

Similarly, Y and C signals are composed at line A2. 

Y = {(G+Ye) + (Mg+Cy)} x 1/2 
= 1/2 {2B+3G+2R} 

-(B-Y) = {(G+Ye) - (Mg+Cy)} 
= -{2B-G} 

Accordingly, Y signal is balanced in relation to the scanning lines, and C signal takes the form of R-Y 
and -(B-Y) on alternate lines. 
It is the same for B field. 



I 



253- 



SONY® ; 'CX027BK 

Definition of Standard Imaging Conditions 

© Standard imaging condition I: (As imaging device) Use a pattern box (luminance 706 Nit, 3200°K 
Halogen source), at F5.6 with a typical test lens, and CM-500S (1.0 mmt) for IR cut filter. 

© Standard imaging condition II: Use a light source with uniformity within 2%, color temperature of 
3200°K and CM-500S (1.0 mmt) as IR cut filter. The light intensity is adjusted in accordance 
with the average value of Y signals (Ya) indicated in each item. 

1) Set to standard imaging condition I and measure Y signal (S) at the center of the screen. 

2) Set to imaging condition II. Adjust light intensity to 10 times when Y signal output average value 
YA=150mV. Then test Y signal Min. Value. 

3) Set to imaging condition II. Adjust light intensity to 500 times when Y signal output average value 
YA=150mV. Stop Read out clock. When the charge drain executed by the electronic shutter at the 
respective H blankings takes place, test the Max. value Ysm of Ysignal output. 

SM = (Ysm/Ya) x V500 x 1 /10 x 100 (%) (VioV) m 

4) Set to imaging condition II. Adjust light intensity to 1000 times when Y signal output average value 
YA=150mV. Then check that there is no blooming. 

5) Video signal shading SHy 

Set to standard imaging condition II. Test Y signal Max. (Y max.) and Min. (Y min.) values. 
Adjust light intensity to obtain a Y signal output average value (Ya) of about 150mV. 

SHy = (Ymax - Ymin)/YA x 100 (%) 

6) Set to standard imaging condition II. Adjust light intensity to obtain a Y signal output average value 
(Ya) of 150mV. Test the Max. (Cr max. and Cb max.) and Min. (Cr min. and Cb min.) values of 

C signals from R-Y and B-Y channels. 

ASr = | (Crmax - Crmin)/YA | x 100 (%) 
ASb = | (Cbmax - Cbmin)/YA | x 100 (%) 

7) Test the average Y signal voltage when the device ambient temperature is at 55°C and light is 
obstructed with horizontal idle transfer level as reference. 

8) Following 7, test Max. (Yd max) and Min. (Yd min) values of Y signal output. Only keep spot 
defects out of this range. 

AYdt= Ydmax - Ydmin 



-254- 



SONY® 



ICX027BK 



9) © Fy 

Set to standard imaging condition II. Adjust light intensity to obtain a Y signal output average 
value (Ya) of 150 mV. Test the Y signal difference (AYf) between even field and odd field. 

Fy = (AYf/YA) x 1 00 (%) 

® Fcr, Feb 

Set to standard imaging condition II. Insert R and B filter respectively, and test the C signal 
difference (ACr, ACb) between even field and odd field and the C signal output average value 
(CAr, CAb). At that time, adjust light intensity to obtain a Y signal output average value (Ya) of 
100 mV. 

Fci = (ACi/CAi) x 100 (%) (i = r, b) 

10) Set to standard imaging condition II. Insert W,R,G and B filters respectively and test the signal 
difference (AYIw, AYIr, AYIg, AYIb) between Y signal lines of the same field. At that time, adjust 
light intensity to obtain a Y signal output average value (Ya) of 100 mV. 

Lei = (AYIi/YA) x 100 (%) (i = w, r, g, b) 



11) Light a stroboscopic tube with the following timing and test the residual image. 
AYlag = (Ylag/Ys) x 100 (%) 



FLD 



SG1 



I 



ji n n o i 



SG2 



Strobe light timing 

Output — I L 



Ys 200mV 

ruJL 



Y lag (Residual image) 

t 



-255- 



SONY® 



ICX027BK 



L^Wk— 




\f 



-ff< fe 

-r« 



h 



f» 



-VW — fe 



tH<- 



4? 



-JWV — k 



*IV* 



*tf 




[L 



^J*- 



x B 



-)Rs 



®°a 



t-T*-#— fe 



00? 



55- — f-VW 



I fe 



A A A A AAA 



-^WV— fe 



^-Wr^U-VW fe 



e? 




256- 



SONY® 



ICX027BK 



Spectral Sensitivity Characteristics 

(Excluding light source characteristics, including lens characteristics) 




400 



Using read out clock timing chart 



500 
Wave Length [nm] 



600 



700 



I 



Odd Field < 



Even Field s 



V1 
V2 



V3 
V4 



V1 
V2 



V3 
V4 



J L 



Unites 



- 257 



SONY® 



ICX027BK 



r=JU 



So 
in m 



— (M 

8 a 



— w to * 
> > > > 



83 



-258- 



SONY® 



ICX027BK 



I = 



I 





X 








Q. 


o 








Q. 


m 


o 


_l 


▼• 


CM 


e> 


X 


X 


^ 


CM 


to *■ 


_l 


-> 


z 


CD 


X 


X 


Ol 


CO 


CO 


> 


> 


> > 


o 


CO 



259- 



SONY. ^mt 

Handling Instructions 

1 ) Static charge prevention 

CCD image sensor are easily damaged by static discharge. Before handling be sure to take the 
following protective measures. 

a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use 
conductive shoes. 

b) When handling directly use an earth band. 

c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. 

d) Ionized air is recommended for discharge when handling CCD image sensor. 

e) For the shipment of mounted substrates use boxes treated for the prevention of static charges. 

2) Soldering 

a) Make sure the package temperature does not exceed 80°C. 

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 
grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and 
remount cool sufficiently. 

c) To dismount an imaging device do not use a solder pult. When using an electric desoldering 
tool use a thermal controller of the zero cross On/Off type and connect to ground. 

3) Dust and dirt protection 

a) Operate in clean environments (around class 1000 will be appropriate). 

b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. 
Should dirt stick to a glass surface blow it off with an air blow. (For dirt stuck through static 
electricity ionized air is recommended) 

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not 
to scratch the glass. 

d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool 
when moving to a room with great temperature differences. 

e) When a protective tape is applied before shipping, just before use remove the tape applied for 
electrostatic protection. Do not reuse the tape. 



4) Do not expose to strong light (sun rays) for long periods, color filters are discolored. 

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage 
or usage in such conditions. 

6) CCD image sensor are precise optical equipment that should not be subject to mechanical shocks. 



-260 



SONY. 



ICX038AK 



Solid-State Image Sensor for Color Camera 



Description 

ICX038AK is an interline transfer CCD solid- 
state imager suitable for NTSC 1/2 inch color 
video cameras. High sensitiveness is achieved 
through the adoption of Ye, Cy, Mg and G 
complementary color mosaic filters and HAD 
(Hole-Accumulation Diode) sensors. 

This chip features a field integration read out 
system and an electronic shutter with variable 
charge-storage time. 

Features 

• High image, high sensitivity and low dark 
current 

• Consecutive various speed shutter 

1 /60sec. (Ty p.) , 1/1 OOsec. to 1 / 1 0OOOsec. 

• Low smear 

• High antiblooming 

• Ye, Cy, Mg, G on chip type complementary 
color mosaic filter. 

• Horizontal register 5V drive 

• Reset gate 5V drive 

Device Structure 

• Optical size 1/2 inch format 

• Number of effective pixels 

768 (H) X494 (V) 

• Number of total pixels 

811 (H) X508 (V) 

• Interline transfer CCD image sensor 

• Chip size 7.95mm (H) x 6.45mm (V) 

• Unit cell size 8.4 urn (H) x 9.8 urn (V) 

• Optical black Horizontal (H) direction 

Vertical (V) direction 

• Number of dummy bits Horizontal 

Vertical 

• Substrate material silicon 



Pakage Outline 



Unit : mm 



20 pin DIP (Ceramic) 



18.0> 



sJ 




ElKcliv* EUnwnlV Picture C«nl«f 




£""<*! 



( Unit ; mm ) 



Approx. 380k pixels 
Approx. 410k pixels 




Optical black position (Top View) 



Front 3 pixels Rear 40 pixels 
Front 12 pixels Rear 2 pixels 

22 

1 (even field only) 



E89442 - ST 



-261 - 



SONY® 



ICX038AK 



Block Diagram 



Pin Configuration 

(Top View) 




LH#I N9I H°)2 
Noto) - J 1 : Photo Hour 



Pin Description 



V04 


A 




@) H02 


V03 


(b 




(j9) H01 


V02 


® 




(j8) LH01 


SUB 


w 




© RG 


6N0 


(5) 




U© RD 


V01 


© 


TOP VIEW 


(g) GND 


Vl 







@ GND 


GND 


® 




(j|) Vss 


VDD 


© 




02) NC 


VOUT 


(§) 


/~*\ 


(jj) Vgg 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V4m 


Vertical register transfer clock 


11 


Vgg 


Output amplifier gate bias 


2 


Vd>3 


Vertical register transfer clock 


12 


NC 




3 


V<|>2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (Overflow drain) 


14 


GND 


GND 


5 


GND 


GND 


15 


GND 


GND 


6 


V<t»i 


Vertical register transfer clock 


16 


RD 


Reset drain bias 


7 


Vl 


Protective transistor bias 


17 


RG 


Reset gate clock 


8 


GND 


GND 


18 


LH 4> 1 


Horizontal register final stage transfer clock 


9 


Vdd 


Output amplifier drain supply 


19 


H 4> 1 


Horizontal register transfer clock 


10 


VOUT 


Signal output 


20 


H4> 2 


Horizontal register transfer clock 



Absolute Maximum 


Ratings 








Item 


Ratings 


Unit 


Remarks 


Substrate voltage SUB-GND 


-0.3 to +55 


V 




Supply voltage 


Vdd, Vrd, Vout, Vss - GND 


- 0.3 to +18 


V 




Vdd. Vrd, Vout, Vss - SUB 


- 55 to +10 


V 




Clock input voltage 


V <|> 1, V<J>2, V(J)3, V<J>4- GND 


- 1 5 to +20 


V 




V <|> 1, V(J>2, V0 3, V<J>4- SUB 


to + 10 


V 




Voltage difference between vertical clock input pins 


to+ 15 


V 


* (Max.) 


Voltage difference between horizontal clock input pins 


to +17 


V 




H <t> 1. H(t>2-V04 


- 1 7 to +17 


V 




LH<1m, RG, Vgg -GND 


- 1 to +15 


V 




LH(|> 1, RG, Vgg -SUB 


- 55 to +10 


V 




Vl - SUB 


-65 to +0.3 


V 




Beside GND, SUB-Vl 


-0.3 to +30 


V 




Storage temperature 


-30 to +80 


^C 




Operating temperature 


- 1 to +60 


°C 





* Note) +27V (Max.) when clock width < 10 us, duty factor < 0.1 %. 



262- 



SONY® 



ICX038AK 



Bias Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain voltage 


Vdd • 


14.55 


15.0 


15.45 


V 




Reset drain voltage 


Vrd 


14.55 


15.0 


15.45 


V 


Vrd = Vdd 


Output amplifier gate voltage 


Vgg 


1.75 


2.0 


2.25 


V 




Output amplifier source 


Vss 


Ground through 
390 Q resistor 




±5% 


Substrate voltage adjustment range 


VSUB 


9.0 




18.5 


V 


*2 


Fluctuation range after substrate voltage 
adjustment 


A Vsub 


-3 




+ 3 


% 




Reset gate clock voltage adjustment 
range 


Vrgl 


0.5 




5.0 


V 


*2 *6 


Fluctuation range after reset gate clock 
voltage adjustment 


A Vrgl 


-3 




+ 3 


% 




Protective transistor bias 


Vl 


*3 







DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain current 


Idd 




5 




mA 




Input current 


llN1 






1 


HA 


*4 


Input current 


llN2 






10 


HA 


*5 



* 2) Substrate voltage (Vsub) • reset gate clock voltage (Vrgl) setting value display. 

Setting values of substrate voltage and reset gate clock voltage are displayed at the back 
of the device through a code address. Adjust substrate voltage (Vsub) and reset gate clock 
voltage (Vrgl) to the displayed voltage. Fluctuation range after adjustment is ±3%. 



I 



Vsub code address — 1 digit display n D 

Vrgl code address - 1 digit display J L-vsub address code 

' Vrgl address code 

Code addresses and actual numerical values correspond to each other as follows. 



Vrgl address code 





1 


2 


3 


4 


5 


6 


7 


8 


9 




Numerical value 


0.5 


1.0 


1.5 


2.0 


2.5 


3.0 


3.5 


4.0 


4.5 


5.0 










Vsub 

address 

code 


E 


f 


G 


h 


J 


K 


L 


m 


N 


P~ 


Q 


R^ 


~T 


"-T^ 


! u 


V 


W 


X 


Y 


Z 


Numerical 
value 


9.0 


9.5 


10.0 


10.5 


11.0 


11.5 


12.0 


12.5 


13.0 


13.5 


14.0 


14.5 


15.0 


15.5 


16.0 


16.5 


17.0 


17.5 


18.0 


18.5 



< Example > "5L" -► Vrgl = 3.0V 
Vsub= 12.0V 

* 3) Vl setting is the Vvl voltage of the vertical transfer clock waveform. 



-263 



SONY® 



* 4) 1. Current to each pin when 18V is applied to Vdd, Vout, Vss and SUB pins, while pins 

that are not tested are grounded. 

2. Current to each pins when 20V is applied sequentially to V$ 1, V<j> 2, V(J>3, V<1> 4, H $ 1 
and H <t> 2, while pins that are not tested are grounded. However, 20V is applied to SUB. 

3. Current to each pins when 15V is applied sequentially to pins RG, LH (J) 1 and Vgg, 
while pins that are not tested are grounded. However, 15V is applied to SUB. 

4. Current to Vl pin when it is grounded, while 30V is applied to all pins except pins 
that are not tested. However, GND and SUB pins are kept open. 

* 5) Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are 

grounded. 

Clock Voltage Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Waveform 
diagram 


Remarks 


Read out clock 
voltage 


Vvt 


14.55 


15.0 


15.45 


V 


1 




Vertical transfer 
clock voltage 


VVH1, VVH2 


-0.05 





0.05 


V 


2 


Vvh = (Vvhi+Vvh2)/2 


VVH3, VVH4 


-0.2 





0.05 


V 


2 




VVL1, VVL2, 
VVL3, VVL4 


-9.6 


-9.0 


-8.5 


V 


2 


VvL = (VvL3 + VvL4)/2 


V<J>V 


8.3 


9.0 


9.65 


V 


2 


V <|> v = VvHn — Vvi_n 
(n = 1 to 4) 


I VVH1 — VVH2 I 






0.1 


V 


2 




VVH3 — VVH 


-0.25 




0.1 


V 


2 




VVH4 — VVH 


-0.25 




0.1 


V 


2 




VvHH 






0.5 


V 


2 


High level coupling 


VVHL 






0.5 


V 


2 


High level coupling 


VvLH 






0.5 


V 


2 


Low level coupling 


VVLL 






0.5 


V 


2 


Low level coupling 


Horizontal 
transfer clock 
voltage 


V$ H 


4.75 


5.0 


5.25 


V 


3 




Vhl 


-0.05 





0.05 


V 


3 




Horizontal final 
stage transfer 
clock voltage 


Vlhh 


4.45 


5.0 


5.55 


V 


4 




Vlhl 


-4.7 


-4.0 


-3.5 


V 


4 




V<|>LH 


8.0 


9.0 


10.0 


V 


4 




Reset gate clock, 
voltage 


V <j> RG 


4.5 


5.0 


5.5 


V 


5 


* 6 


Vrglh — Vrgll 






0.8 


V 


5 


Low level coupling 


Substrate clock 
voltage 


V 4> sub 


23.0 


24.0 


25.0 


V 


6 





-264- 



SONY® 



ICX038AK 



* 6) No adjustment of reset gate clock voltage is necessary when reset gate clock is driven 
as indicated below. In this case, reset gate clock voltage set point displayed on back of 
image sensor has no meaning. 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Waveform 
diagram 


Remarks 


Reset gate clock 
voltage 


Vrgl 


-0.2 





0.2 


V 


5 




V <t> RG 


8.5 


9.0 


9.5 


V 


5 





Clock Equivalent Circuit Constant 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Capacitance between vertical transfer 
clock and GND 


-C $ V1 , C V3 




1800 




PF 




C <(> V2, C <t> V4 




2200 




PF 




Capacitance between vertical transfer 
clocks 


C <J> V12, C <J> V34 




450 




PF 




C <j> V23, C <t> V41 




270 




PF 




Capacitance between horizontal transfer 
clock and GND 


C (J> H1, C <J> H2 




62 




PF 




Capacitance between horizontal transfer 
clocks 


C HH 




47 




PF 




Capacitance between horizontal final 
stage transfer clock and GND 


C $ LH 




8 




PF 




Capacitance between reset gate clock 
and GND 


C<t> RG 




8 




PF 




Capacitance between substrate clock 
and GND 


C <t> SUB 




400 




PF 




Vertical transfer clock serial resistor 


Ri, R2, R3, R4 




68 




Q 




Vertical transfer clock ground resistor 


Rgnd 




15 




Q 






V04 



H01 O- 



COH1 Z= 



Ttr 



C<?HH 



^- C0H2 



Ttr 



-O H<*>2 



V03 



Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent 

circuit 



-265 



SONY® 



ICX038AK 



Drive Clock Waveform Conditions 



(1) Read out clock waveform 




OV 



(2) Vertical transfer clock waveform 



V<t>1 



VVH1 VVHH 




V«>3 



VVHL 




VVL 



V4>2 



VVHH VVHH 



VVH2 »VHL 




VVL 



V*>4 




-266- 



SONY® 



ICX038AK 



(3) Horizontal transfer clock waveform diagram 



90 V. 



iov. 



Vhl— ► 




V<t>H 





(4) Horizontal final stage transfer clock waveform diagram 



VLHH 



Vlhl 




(5) Reset gate clock waveform diagram 



RG waveform 

Vrglh-^- - 
Vrgll-* 

LH1 waveform 

ov -► 



tr . . twh tf 




VRGH 



VRGL+ 0.5V 
VRGL 



Vrglh is the maximum value and Vrgll the minimum value of the coupling waveform in the 
period from Point A in the diagram above to RG rise. 
Vrgl is the mean value for Vrglh and Vrgll. 

Vrgl= (Vrglh + Vrgll) /2 
Vrgh is the minimum value for twh period. 
V $ rg = Vrgh — Vrgl 



267 



SONY® 



ICX038AK 



(6) Substrate clock waveform 




Clock switching characteristics 



Item 


Symbol 


twh 


twl 


tr 


tf 


Unit 


Remarks 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Read out clock 


Vt 


2.3 


2.5 












0.5 






0.5 




MS 


During read 
out 


Vertical transfer 
clock 


V 4> i. V 4> 2, 

V 4> a, V 4> 4 




















0.015 




0.25 


MS 


*7 


Horizontal transfer 
clock 


H4> 




20 






20 






15 


19 


*8 


15 


19 


ns 


During 
imaging 


Horizontal final 
stage clock 


LH4> 




24 




22 


27 






10 






9 




ns 


During 
imaging 


Horizontal transfer 
/horizontal final 
stage clock 


H 4» i. LH 4> 




5.38 












0.01 






0.01 




MS 


During 
parallel 
serial 
conversion. 


Horizontal transfer 
clock 


H4>2 










5.38 






0.01 






0.01 




MS 


Reset gate clock 


4> RG 


11 


13 






51 






3 






3 




ns 




Substrate clock 


4> SUB 


1.5 


1.8 














0.5 






0.5 


MS 


During 
charge drain. 



* 7) When vertical transfer clock driver CXD1250 is in use. 

* 8) tf £ tr - 2 ns 



Item 


Symbol 


two 


Unit 


Remarks 


Min. 


Typ. 


Max. 


Horizontal transfer clock 


H<J> 


16 


20 




ns 


*9 


Horizontal transfer/ 
horizontal final stage clock 


H 4> 2, LH <J> 


15 


20 




ns 


*10 



* 9) "two" is the overlap period of horizontal transfer clocks H 4> 1 and H 4> 2's twh and twl. 
*10) "two" is the overlap period of horizontal transfer clock H <J> 2's twl and horizontal final 
stage transfer clock LH<t>'s twh' 



268 



SONY® 



ICX038AK 



Operating Characteristics 












(Ta = 25°C) 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test method 


Remarks 


Sensitivity 


S 


180 


220 




mV 


1 




Saturation signal 


Ysat 


500 






mV 


2 


Ta = 60lC 


Smear 


Sm 




0.009 


0.015 


% 


3 




Video signal shading 


SHy 






20 


% 


4 


Zone 0, 1 






25 


% 


4 


Zone to II' 


Uniformity between 
signal channels 


ASr 






10 


% 


5 




ASb 






10 


% 


5 




Dark signal 


Ydt 






2 


mV 


6 


Ta = 60t 


Dark signal shading 


AYdt 






1 


mV 


7 


Ta = 60°C 


Flicker Y 


Fy 






2 


% 


8 




Flicker R-Y 


Fcr 






5 


% 


8 




Flicker B-Y 


Feb 






5 


% 


8 




Horizontal stripes R 


Lcr 






3 


% 


9 




Horizontal stripes G 


Leg 






3 


% 


9 




Horizontal stripes B 


Lcb 






3 


% 


9 




Horizontal stripes W 


Lew 






3 


% 


9 




Lag 


Lag 






0.5 


% 


10 





Zone chart of Video signal shading 

768 (H) 




V 
TO 

Testing System 



Ignoring region 

Effective picture elements 



® 



CCD 



CCD output signal 



C.D.S 



LPF1 



® 
-® Y signal output 



(3dB down 6.3MHz) 
A 



S/H 



S/H 

T~ 

JL 



> 



LPF2 



© 
-® Chroma signal output 



(3dB down 1MHz) 



I 



Note) Adjust AMP amplifier so that total gains between ® and ® and between ® and © equal 1. 



269- 



SONY® 



ICX038AK 



Image Sensor Characteristics Test Method 

©Test conditions 

(D Through the following tests the substrate voltage and reset gate clock voltage are set to 
the value displayed on the device, while the device drive conditions are at the typical value 
of the bias and clock voltage conditions. 

(5) Through the following tests defects are excluded and, unless otherwise specified, the optical 
black level (Hence forth referred to as OB) is set as the reference for the signal output which 
is taken as the Y signal output or the chroma signal output of the testing system. 

© Color coding of CFA (Color Filter Array) & Composition of luminance (Y) and 
chrominance (C) signals 



< 



Cy 


Ye 


Cy 


Ye 


G 


Mg 


G 


Mg 


Cy 


Ye 


Cy 


Ye 


Mg 


G 


Mg 


G 


] 


1 


1 


i 











> 
> 



A1 



A2 



Hreg 



Color Coding Diagram 



CFA of this image sensor is shown in the 
Figure. This complementary CFA is used with 
a "field integration mode", where all of the 
photosites are read out during each video 
field. Signals from two vertically adjacent 
photosites, such as line A1 or A2 for field 
A, are summed when the image charge is 
transferred into the vertical storage columns. 
The read out line pairing is shifted down one 
line for field B. The sensor output signals 
through the horizontal register (H reg.) at line 
A1 are [G + Cy], [Mg + Ye], [G + Cy], [Mg 
+ Ye]. 



These signals are processed in order to compose Y and C signals. By adding the two adjacent 
signals at line A1, Y signal is formed as follows : 
Y = {(G + Cy) + (Mg + Ye)} x 1/2 
= 1/2 {2B + 3G + 2R} 
C signal is composed by subtracting the two adjacent signals at line A1. 
R - Y= {(Mg + Ye) - (G + Cy)} 
= {2R-G} 
Next, the signals through H reg. at line A2 are 
[Mg + Cy], [G + Ye], [Mg + Cy], [G + Ye] 
Similarly, Y and C signals are composed at line A2. 
Y={(G + Ye) + (Mg + Cy)} x 1/2 

= 1/2 {2B + 3G + 2R} 
-(B-Y) = {(G + Ye) - (Mg + Cy)} 
= - {2B - G} 
Accordingly, Y signal is balanced in relation to the scanning lines, and C signal takes the form 
of R-Y and - (B-Y) on alternate lines. 
It is the same for B field. 



270 



SONY® ICX038AK 



©Definition of standard imaging conditions 

© Standard imaging condition I : (As imaging device) Use a pattern box (luminance 706 Nit, color 
temperature 3200k Halogen source) as a subject. (Pattern for evaluation is not applicable.) 
Use a testing standard lens with CM500S O.Ommt) as IR cut filter and image at F5.6. At 
this time, light intensity to sensor receiving surface is defined as standard sensitivity testing 
light intensity. Y signal output average value in this condition is called Ya. 

(D Standard imaging condition II : Image a light source (color temperature of 3200k) which 
uniformity of brightness is within 2% at all angles. Use a testing standard lens with CM500S 
O.Ommt) as IR cut filter. The light intensity is adjusted to the value indicated in each testing 
item by lens diaphragm. 

1 . Sensitivity 

Set to standard imaging condition I and measure Y signal (S) at the center of the screen. 

2. Saturation signal 

Set to standard imaging condition II. Adjust light intensity to 10 times that of Y signal 
output average value (Ya), then test Y signal minimum value. 

3. Smear 

Set to standard imaging condition II. Adjust light intensity to 500 times that of Y signal 
output average value (Ya). Stop read out clock. When the charge drain executed by the 
electric shutter at the respective H blankings takes place, test the maximum value Ysm of 
Y signal output. 

Sm =^ Lx 550 >< tV X,00(%)<1/10V) 

4. Video signal shading 

Set to standard imaging condition II. Adjust light intensity to Y signal output average value 
(Ya) with lens diaphragm at F5.6 to F8. Then test maximum (Ymax) and minimum (Ymin) 
values of Y signal. 

SHy= (Ymax- Ymin)/Y A X 100 (%) 

5. Video signal between channels uniformity 

Set to standard imaging condition II. Adjust light intensity to Y signal output average value 
(Ya). Then test maximum (Crmax, Cbmax) and minimum (Crmin, Cbmin) values of chroma 
signals from R — Y and B - Y channels. 

A Sr = | (Crmax - Crmin)/Y A | x 1 00 (%) 
A Sb = | (Cbmax - Cbmin)/Y A I x 1 00 (%) 

6. Dark signal 

Test Y signal output average value Ydt when the device ambient temperature is at 60 C C 
and light is obstructed with horizontal idle transfer level as reference. 



I 



-271 - 



SONY® 



7. Dark signal shading 

Following 6, test maximum (Ydmax) and minimum (Ydmin) values of dark signal output. 

A Ydt = Ydmax - Ydmin 

8. Flicker 
© Fy 

Set to standard imaging condition II. Adjust light intensity to Y signal output average value 
(Ya). Then test the Y signal difference (AYf) between even field and odd field. 

Fy= (AYf/YA) x 100 (%) 

(D Fcr, Feb 

Set to standard imaging condition II. Adjust light intensity to Y signal output average value 
(Ya). Then insert R or B filter, and test the C signal difference (ACr, ACb) between even 
field and odd field and the C signal output average value (CAr, CAb). 

Fci= (ACi/CAi) x 100 (%) (i = r, b) 

9. Lateral stripe 

Set to standard imaging condition II. Adjust light intensity to Y signal output average value 
(Ya). Then insert R, G and B filters respectively, and test the signal difference (AYIw, AYIr, 
AYIg, AYIb) between Y signal lines of the same field. 

Lci= (AYN/Ya) x 100 (%) (i=w, r, g, b) 

10. Residual image 

Adjust Y signal output value (Ys) by strobe light to 200mV. Then light a stroboscopic tube 
with the following timing and test the residual image (Ylag). 



Lag= (Ylag/Ys) x 100 (%) 



FLD 



SG1 



Strobe light timing 



Output 



Y lag (Residual image) 




n_ 



-272 



SONY* 



ICX038AK 



3 
O 

o 


> 




I 



-273- 



SONY® 



ICX038AK 



Spectral Sensitivity Characteristics 

(Excluding light source characteristics, including lens characteristics) 



1.0 
.9 

.8 
.7 
.6 
.5 
.4 
.3 
.2 









\ 












Y.\ 






cy 




WG) 




























































N^ Mg 




















V 












^ 









400 



500 600 

WAVE LENGTH Cnml 



700 



Using read out clock timing chart 



ODD FIELD < 



EVEN FIELD < 



HD 

VI 
V2 

V3 
V4 



VI 
V2 

V3 
V4 



40.6 



'2.51 



JT 



I I 



J f -6 



2.5 2.5 



J-L 



i r 

— L_ 



Unit : ms 



-274- 



SONY® 



ICX038AK 





> 



.C 

o 



I 



uo 



-275 - 



SONY® 



ICX038AK 



C 

o 

o 

X 



(0 



276- 



SONY® ,CX038AK 



Handling Instructions 

1) Static charge prevention 

CCD image sensors are easily damaged by static discharge. Before handling be sure to take 
the following protective measures. 

a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use 
conductive shoes. 

b) When handling directly use an earth band. 

c) Install a conductive mat on the floor or working table to prevent the generation of static 
electricity. 

d) Ionized air is recommended for discharge when handling CCD image sensor. 

e) For the shipment of mounted substrates use boxes treated for the prevention of static 
charges. 

2) Soldering 

a) Make sure the package temperature does not exceed 80 °C. 

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. 
Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For 
repairs and remount, cool sufficiently. 

c) To dismount an imaging device do not use a solder suction equipment. When using an 
electric desoldering tool use a thermal controller of the zero cross On/Off type and 
connect to ground. 

3) Dust and dirt protection 

a) Operate in clean environments (around class 1000 will be appropriate). 

b) Do not either touch glass plates by hand or have any object come in contact with glass 
surfaces. Should dirt stick to a glass surface blow it off with an air blow. (For dirt 
stuck through static electricity ionized air is recommended) 

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be 
careful not to scratch the glass. 

d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or 
precool when moving to a room with great temperature differences. 

e) When a protective tape is applied before shipping, just before use remove the tape 
applied for electrostatic protection. Do not reuse the tape. 

4) Do not expose to strong light (sun rays) for long periods, color filters are discolored. 

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid 
storage or usage in such conditions. 

6) CCD image sensor are precise optical equipment that should not be subject to mechanical 
shocks. 

7) Defect compensation ROM 

This is shipped in its own case in pair with the CCD image sensor. 

Pair with the CCD image sensor bearing the same serial number during mounting. When 

the CCD image sensor has no defect, there is no ROM or serial number. 



I 



-277- 



SONY. 



ICX039AK 



Solid-State Image Sensor for Color Camera 



Description 

ICX039AK is an interline transfer CCD solid- 
state imager suitable for PAL 1/2 inch color 
video cameras. High sensitiveness is achieved 
through the adoption of Ye, Cy, Mg and G 
complementary color mosaic filters and HAD 
(Hole-Accumulation Diode) sensors. 

This chip features a field integration read out 
system and an electronic shutter with variable 
charge-storage time. 

Features 

• High image, high sensitivity and low dark 
current 

• Consecutive various speed shutter 

1/50sec.(Typ.), 1/100sec. to 1/10000sec. 

• Low smear 

• High antiblooming 

• Ye, Cy, Mg, G on chip type complementary 
color mosaic filter. 

• Horizontal register 5V drive 

• Reset gate 5V drive 

Device Structure 

• Optical size 1 /2 inch format 

• Number of effective pixels 

752 (H) X582 (V) 

• Number of total pixels 

795 (H) X596 (V) 

• Interline transfer CCD image sensor 

• Chip size 7.95mm (H) X 6.45mm (V) 

• Unit cell size 8.6 urn (H) x 8.3 urn (V) 

• Optical black Horizontal (H) direction 

Vertical (V) direction 

• Number of dummy bits Horizontal 

Vertical 

• Substrate material silicon 



Pakage Outline 



Unit : mm 



20 pin DIP (Ceramic) 




□ I 


1 N 








it 






I I 1 - 778 


0.46 



( Unit ; mm ) 



Approx. 440k pixels 
Approx. 470k pixels 




Optical black position (Top View) 



Front 3 pixels Rear 40 pixels 
Front 12 pixels Rear 2 pixels 

22 

1 (even field only) 



E89445 - ST 



-278 



SONY® 



ICX039AK 



Block Diagram 




J) — • 








H^Tl 




NOW 

4ia 




i-E3 


l 


HZ3 




3 






-m 




-s 




-LaJ 


* 


-isi 


(n) . 


s 






-H3 




-oa 




-sa 


n 


-Gt 


@ 


I 






-G51 




-{E 


1 


-s 


1 


-L»J 




6 




L r 


V 




V V 








Horiionta 

1 




3 






Js) i— 






1 













Pin Configuration 

(Top View) 



LH9> H»1 H02 



Pin 



Not.) -O : P"*" ! 

Description 



V04 


V 




@) H02 


V03 


Q) 




© H01 


V02 


(X) 




(l8) LH01 


SUB 


& 




@ RG 


GND 


(5) 




(l6) RD 


V01 


© 


TOP VIEW 


@ GND 


Vl 


(5 




(K) GND 


GND 


® 




© Vss 


VDD 


© 




(J2) NC 


VOUT 


(id) 


/~\ 


(H) Vgg 



No. 


Symbol 


Description 


No. 


Symbol 


Description 


1 


V<t>4 


Vertical register transfer clock 


11 


Vgg 


Output amplifier gate bias 


2 


V(f>3 


Vertical register transfer clock 


12 


NC 




3 


Vd> 2 


Vertical register transfer clock 


13 


Vss 


Output amplifier source 


4 


SUB 


Substrate (Overflow drain) 


14 


GND 


GND 


5 


GND 


GND 


15 


GND 


GND 


6 


V 4> 1 


Vertical register transfer clock 


16 


RD 


Reset drain bias 


7 


Vl 


Protective transistor bias 


17 


RG 


Reset gate clock 


8 


GND 


GND 


18 


LH 4> 1 


Horizontal register final stage transfer clock 


9 


Vdd 


Output amplifier drain supply 


19 


H 4> 1 


Horizontal register transfer clock 


10 


VoUT 


Signal output 


20 


H4>2 


Horizontal register transfer clock 



I 



Absolute Maximum 


Ratings 








Item 


Ratings 


Unit 


Remarks 


Substrate voltage SUB-GND 


-0.3 to +55 


V 




Supply voltage 


Vdd, Vrd, Vout, Vss - GND 


- 0.3 to +18 


V 




Vdd, Vrd, Vout, Vss - SUB 


- 55 to +10 


V 




Clock input voltage 


V$1, V<(>2, V<t>3, V04- GND 


- 1 5 to +20 


V 




V (J> 1, V 2, V 3, V<M- SUB 


to + 10 


V 




Voltage difference between vertical clock input pins 


to+ 15 


V 


* (Max.) 


Voltage difference between horizontal clock input pins 


to+ 17 


V 




H<M, H<t>2-V<M 


- 1 7 to +17 


V 




LH 1, RG, Vgg -GND 


- 1 to +15 


V 




LH<|> 1, RG, Vgg-SUB 


- 55 to +10 


V 




Vl - SUB 


-65 to +0.3 


V 




Beside GND, SUB-Vl 


-0.3 to +30 


V 




Storage temperature 


-30 to +80 


°C 




Operating temperature 


- 1 to +60 


°C 





* Note) + 27V (Max.) when clock width < 10 us, duty factor < 0.1 %. 



279 



SONY® 



Bias Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain voltage 


Vdd 


14.55 


15.0 


15.45 


V 




Reset drain voltage 


Vrd 


14.55 


15.0 


15.45 


V 


Vrd = Vdd 


Output amplifier gate voltage 


Vgg 


1.75 


2.0 


2.25 


V 




Output amplifier source 


Vss 


Ground through 
390 resistor 




±5% 


Substrate voltage adjustment range 


VSUB 


9.0 




18.5 


V 


* 2 


Fluctuation range after substrate voltage 
adjustment 


A Vsub 


-3 




+ 3 


% 




Reset gate clock voltage adjustment 
range 


Vrgl 


0.5 




5.0 


V 


*2 *6 


Fluctuation range after reset gate clock 
voltage adjustment 


A Vrgl 


-3 




+ 3 


% 




Protective transistor bias 


v l 


*3 







DC characteristics 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Output amplifier drain current 


Idd 




5 




mA 




Input current 


Iiimi 






1 


uA 


*4 


Input current 


llN2 






10 




uA 


*5 



* 2) Substrate voltage (Vsub) • reset gate clock voltage (Vrgl) setting value display. 

Setting values of substrate voltage and reset gate clock voltage are displayed at the back 
of the device through a code address. Adjust substrate voltage (Vsub) and reset gate clock 
voltage (Vrgl) to the displayed voltage. Fluctuation range after adjustment is ±3%. 



•—Vsub address code 
' Vrgl address code 

Code addresses and actual numerical values correspond to each other as follows. 



Vsub code address - 1 digit display 
Vrgl code address - 1 digit display 



Vrgl address code 





1 


2 


3 


4 


5 


6 


7 


8 


9 




Numerical value 


0.5 


1.0 


1.5 


2.0 


2.5 


3.0 


3.5 


4.0 


4.5 


5.0 




Vsub 

address 

code 


E 


f 


G 


h 


J 


K 


L 


m 


N 


P 


Q 


R 


S 


T 


U 


V 


W 


X 


Y 


Z 


Numerical 
value 


9.0 


9.5 


10.0 


10.5 


11.0 


11.5 


12.0 


12.5 


13.0 


13.5 


14.0 


14.5 


15.0 


15.5 


16.0 


16.5 


17.0 


17.5 


18.0 


18.5 



< Example > "5I_" 



Vrgl = 3.0V 
Vsub = 1 2.0V 



* 3) Vl setting is the Vvl voltage of the vertical transfer clock waveform. 



-280 



SONY® 



ICX039AK 



*4) 1. Current to each pin when 18V is applied to Vdd, Vout. Vss and SUB pins, while pins 
that are not tested are grounded. 

2. Current to each pins when 20V is applied sequentially to V<t» 1, V<|)2, V<|)3, V<J>4, H<|> 1 
and H <t> 2, while pins that are not tested are grounded. However, 20V is applied to SUB. 

3. Current to each pins when 15V is applied sequentially to pins RG, LH $ 1 and Vgg, 
while pins that are not tested are grounded. However, 15V is applied to SUB. 

4. Current to Vl pin when it is grounded, while 30V is applied to all pins except pins 
that are not tested. However, GND and SUB pins are kept open. 

* 5) Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are 
grounded. 



Clock Voltage Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Waveform 
diagram 


Remarks 


Read out clock 
voltage 


Vvt 


14.55 


15.0 


15.45 


V 


1 




Vertical transfer 
clock voltage 


VvH1, VvH2 


-0.05 





0.05 


V 


2 


Vvh = (Vvm+Vvh2)/2 


VVH3, VVH4 


-0.2 





0.05 


V 


2 




VvL1, VVL2, 
VVL3, VVL4 


-9.6 


-9.0 


-8.5 


V 


2 


VvL = (VvL3 + VvL4)/2 


V<t>v 


8.3 


9.0 


9.65 


V 


2 


V <t> v = VvHn - Vvi_n 
(n = 1 to 4) 


I VVH1 — VVH2 I 






0.1 


V 


2 




VVH3 — VVH 


-0.25 




0.1 


V 


2 




VVH4 — VVH 


-0.25 




0.1 


V 


2 




VVHH 






0.5 


V 


2 


High level coupling 


VVHL 






0.5 


V 


2 


High level coupling 


VvLH 






0.5 


V 


2 


Low level coupling 


VVLL 






0.5 


V 


2 


Low level coupling 


Horizontal 
transfer clock 
voltage 


V<|>H 


4.75 


5.0 


5.25 


V 


3 




Vhl 


-0.05 





0.05 


V 


3 




Horizontal final 
stage transfer 
clock voltage 


Vlhh 


4.45 


5.0 


5.55 


V 


4 




Vlhl 


-4.7 


-4.0 


-3.5 


V 


4 




V<|)LH 


8.0 


9.0 


10.0 


V 


4 




Reset gate clock 
voltage 


V $ RG 


4.5 


5.0 


5.5 


V 


5 


* 6 


Vrglh — Vrgll 






0.8 


V 


5 


Low level coupling 


Substrate clock 
voltage 


V <|> SUB 


23.0 


24.0 


25.0 


V 


6 





I 



-281 



SONY® 



ICX039AK 



* 6) No adjustment of reset gate clock voltage is necessary when reset gate clock is driven 
as indicated below. In this case, reset gate clock voltage set point displayed on back of 
image sensor has no meaning. 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Waveform 
diagram 


Remarks 


Reset gate clock 
voltage 


Vrgl 


-0.2 





0.2 


V 


5 




V RG 


8.5 


9.0 


9.5 


V 


5 





Clock Equivalent Circuit Constant 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Capacitance between vertical transfer 
clock and GND 


C <J> V1, C V3 




1800 




pF 




C V2, C V4 




2200 




pF 




Capacitance between vertical transfer 
clocks 


C V12, C V34 




450 




pF 




C V23, C V41 




270 




PF 




Capacitance between horizontal transfer 
clock and GND 


C H1, C H2 




62 




PF 




Capacitance between horizontal transfer 
clocks 


C HH 




47 




PF 




Capacitance between horizontal final 
stage transfer clock and GND 


C LH 




8 




PF 




Capacitance between reset gate clock 
and GND 


C0RG 




8 




PF 




Capacitance between substrate clock 
and GND 


C SUB 




400 




PF 




Vertical transfer clock serial resistor 


Ri, R2, R3, R4 




68 




Q 




Vertical transfer clock ground resistor 


Rgnd 




15 




Q 






V02 



C0V41 zp xat>v2zz, C0V23 



V<M 



V03 



H0I O- 



C0H1 ZZ 



in 



C0HH 



ZZ C0H2 



7fr 



-O H02 



Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent 

circuit 



282 



SONY® 



ICX039AK 



Drive Clock Waveform Conditions 



(1) Read out clock waveform 



00% — 

90% — 


-^! 


-=-ri 






A—- 1 - ^ 


-HI— o\ 


<f>M 


H % — 


/ | Vvt 1 \ <>M 

4+MV. 


1 ■ 


1 




i tr I twh i tf ' 
»■« M< »|« M 







ov 



(2) Vertical transfer clock waveform 



v <t> 1 



WHi vvhh VVH Vvhh 

Vvhl£ 




A VVLL I 

VVL - 1 



V<t>3 




V42 



Vvhh Vvhh 




Vvl 



V<k4 



Vvhh Vvhh 




-283 



SONY® 



ICX039AK 



(3) Horizontal transfer clock waveform diagram 



90 V. 



10 V. 



VHL-*- 




V$H 




(4) Horizontal final stage transfer clock waveform diagram 

tr twh tf 



VLHH 



VLHL 





«* 


+■ 


-4 


1 ► 


* 


— * 












i 


\ 




4- 3.5V -- 








V <t>LH 






twl 




10V. -V 






1 


L 








'[ 










twh' 













(5) Reset gate clock waveform diagram 



RG waveform 

Vrglh h 
Vrgll h 



LH1 waveform 

ov -► 



tr . twh tf 




VRGH 



VRGL+0.5V 
VRGL 



Vrglh is the maximum value and Vrgll the minimum value of the coupling waveform in the 
period from Point A in the diagram above to RG rise. 
Vrgl is the mean value for Vrglh and Vrgll. 

Vrgl = (Vrglh + Vrgll) /2 
Vrgh is the minimum value for twh period. 

V <t> rg = Vrgh — Vrgl 



284 



SONY® 



ICX039AK 



(6) Substrate clock waveform 



100 V. 
90 V. 



10 V. 
Vsue — ► V. 



— - 


_ *=rn__ . _ ^ 

^r 1 1 




I ! v ^ 


SUB 1 \ <>M 
1 \ 2 


<J>M 




"71 r'w T"?v — ,.„ 




' tr I twh i tf ' 
W M* »|« — M 







Clock switching characteristics 



Item 


Symbol 


twh 


twl 


tr 


tf 


Unit 


Remarks 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Read out clock 


Vt 


2.3 


2.5 












0.5 






0.5 




MS 


During read 
out 


Vertical transfer 
clock 


V 4» i. V 4> 2. 

V (J) 3, V 4> 4 




















0.015 




0.25 


MS 


*7 


Horizontal transfer 
clock 


H4> 




20 






20 






15 


19 


*8 


15 


19 


ns 


During 
imaging 


Horizontal final 
stage clock 


LH4> 




24 




22 


21 






10 






9 




ns 


During 
imaging 


Horizontal transfer 
/horizontal final 
stage clock 


H 4> i. LH <t> 




5.38 












0.01 






0.01 




MS 


During 
parallel 
serial 
conversion. 


Horizontal transfer 
clock 


H4>2 










5.38 






0.01 






0.01 




MS 


Reset gate clock 


4> RG 


11 


13 






51 






3 






3 




ns 




Substrate clock 


4> SUB 


1.5 


1.8 














0.5 






0.5 


MS 


During 
charge drain. 



I 



* 7) When vertical transfer clock driver CXD1250 is in use. 
*8) tf^tr-2 ns 



Item 


Symbol 


two 


Unit 


Remarks 


Min. 


Typ. 


Max. 


Horizontal transfer clock 


H 


16 


20 




ns 


*9 


Horizontal transfer/ 
horizontal final stage clock 


H <|> 2, LH <t> 


15 


20 




ns 


*10 



* 9) "two" is the overlap period of horizontal transfer clocks H <J> 1 and H 4> 2's twh and twl. 

* 10) "two" is the overlap period of horizontal transfer clock H <t> 2's twl and horizontal final 

stage transfer clock LH<t>'s twh' 



-285 - 



SONY® 










ICX039AK 


Operating Characteristics 








(Ta = 25t) 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test method 


Remarks 


Sensitivity 


S 


160 


200 




mV 


1 




Saturation signal 


Ysat 


450 






mV 


2 


Ta = 60 < £ 


Smear 


Sm 




0.009 


0.015 


% 


3 




Video signal shading 


SHy 






20 


% 


4 


Zone 0, I 






25 


% 


4 


Zone to II' 


Uniformity between 
signal channels 


ASr 






' 10 


% 


5 




ASb 






10 


% 


5 




Dark signal 


Ydt 






2 


mV 


6 


Ta = 60^C 


Dark signal shading 


AYdt 






1 


mV 


7 


Ta = 60t> 


Flicker Y 


Fy 






2 


% 


8 




Flicker R-Y 


Fcr 






5 


% 


8 




Flicker B-Y 


Feb 






5 


% 


8 




Horizontal stripes R 


Lcr 






3 


% 


9 




Horizontal stripes G 


Leg 






3 


% 


9 




Horizontal stripes B 


Lcb 






3 


% 


9 




Horizontal stripes W 


Lew 






3 


% 


9 




Lag 


Lag 






0.5 


% 


10 





Zone chart of Video signal shading 



* 

r- 


752 (H) — 

2 


12-H 


^±-r 


H 
8 


M 






T 

8 
582 

6 


/ 
V 

TO 


0. I 


H 

s 


=^ z£ =N=v 


n. 


n' 



TO 

Testing System 

® 



-Ignoring region 
-Effective picture elements 



CCD 



@ CCD output signal 
C.D.S | — | amp: 



LPF1 



® 
-@ Y signal output 



(3dB down 6.3MHz) 

i. 



S/H 



S/H 

T 

A 



LPF2 



Chroma signal output 



(3dB down 1MHz) 



Note) Adjust AMP amplifier so that total gains between ® and ® and between ® and © equal 1. 



-286 



SONY® 



ICX039AK 



Image Sensor Characteristics Test Method 

©Test conditions 

© Through the following tests the substrate voltage and reset gate clock voltage are set to 
the value displayed on the device, while the device drive conditions are at the typical value 
of the bias and clock voltage conditions. 

(D Through the following tests defects are excluded and, unless otherwise specified, the optical 
black level (Hence forth referred to as OB) is set as the reference for the signal output which 
is taken as the Y signal output or the chroma signal output of the testing system. 

® Color coding of CFA (Color Filter Array) & Composition of luminance (Y) and 
chrominance (C) signals 



< 



Cy 


Ye 


Cy 


Ye 


G 


Mg 


G 


Mg 


Cy 


Ye 


Cy 


Ye 


Mg 


G 


Mg 


G 


1 


1 


1 


I 











> 
> 



A1 



A2 



Hreg 



Color Coding Diagram 



CFA of this image sensor is shown in the 
Figure. This complementary CFA is used with 
a "field integration mode", where all of the 
photosites are read out during each video 
field. Signals from two vertically adjacent 
photosites, such as line A1 or A2 for field 
A, are summed when the image charge is 
transferred into the vertical storage columns. 
The read out line pairing is shifted down one 
line for field B. The sensor output signals 
through the horizontal register (H reg.) at line 
A1 are [G + Cy], [Mg + Ye], [G + Cy], [Mg 
+ Ye]. 



These signals are processed in order to compose Y and C signals. By adding the two adjacent 
signals at line A1, Y signal is formed as follows: 
Y = {(G + Cy) + (Mg + Ye)} x 1/2 
= 1 /2 {2B + 3G + 2R} 
C signal is composed by subtracting the two adjacent signals at line A1. 
R - Y= {(Mg + Ye) - (G + Cy)} 
= {2R-G} 
Next, the signals through H reg. at line A2 are 
[Mg + Cy], [G + Ye], [Mg + Cy], [G + Ye] 
Similarly, Y and C signals are composed at line A2. 
Y= {(G + Ye) + (Mg + Cy)} x 1/2 

= 1 /2 {2B + 3G + 2R} 
-(B-Y) = {(G + Ye) - (Mg + Cy)} 
= - {2B - G} 
Accordingly, Y signal is balanced in relation to the scanning lines, and C signal takes the form 
of R - Y and — (B — Y) on alternate lines. 
It is the same for B field. 



-287- 



SONY® 



©Definition of standard imaging conditions 



© Standard imaging condition I : (As imaging device) Use a pattern box (luminance 706 Nit, color 
temperature 3200k Halogen source) as a subject. (Pattern for evaluation is not applicable.) 
Use a testing standard lens with CM500S (1.0mmt) as IR cut filter and image at F5.6. At 
this time, light intensity to sensor receiving surface is defined as standard sensitivity testing 
light intensity. Y signal output average value in this condition is called Ya. 

(D Standard imaging condition II : Image a light source (color temperature of 3200k) which 
uniformity of brightness is within 2% at all angles. Use a testing standard lens with CM500S 
(1.0mmt) as IR cut filter. The light intensity is adjusted to the value indicated in each testing 
item by lens diaphragm. 

1 . Sensitivity 

Set to standard imaging condition I and measure Y signal (S) at the center of the screen. 

2. Saturation signal 

Set to standard imaging condition II. Adjust light intensity to 10 times that of Y signal 
output average value (Ya), then test Y signal minimum value. 

3. Smear 

Set to standard imaging condition II. Adjust light intensity to 500 times that of Y signal 
output average value (Ya). Stop read out clock. When the charge drain executed by the 
electric shutter at the respective H blankings takes place, test the maximum value Ysm of 
Y signal output. 

s "=^*5k> >< w ><,00W)<1/10V) 

4. Video signal shading 

Set to standard imaging condition II. Adjust light intensity to Y signal output average value 
(Ya) with lens diaphragm at F5.6 to F8. Then test maximum (Ymax) and minimum (Ymin) 
values of Y signal. 

SHy= (Ymax- Ymin)/Y A x 100 (%) 

5. Video signal between channels uniformity 

Set to standard imaging condition II. Adjust light intensity to Y signal output average value 
(Ya). Then test maximum (Crmax, Cbmax) and minimum (Crmin, Cbmin) values of chroma 
signals from R-Y and B-Y channels. 

A Sr = | (Crmax - Crmin)/Y A I X 1 00 (%) 
A Sb = | (Cbmax - Cbmin)/Y A I x 1 00 (%) 

6. Dark signal 

Test Y signal output average value Ydt when the device ambient temperature is at 60 °C 
and light is obstructed with horizontal idle transfer level as reference. 



288- 



SONY® 



ICX039AK 



7. Dark signal shading 

Following 6, test maximum (Ydmax) and minimum (Ydmin) values of dark signal output. 

A Ydt = Ydmax - Ydmin 

8. Flicker 
© Fy 

Set to standard imaging condition II. Adjust light intensity to Y signal output average value 
(Ya). Then test the Y signal difference (AYf) between even field and odd field. 

Fy= (AYf/Y A ) x 100 (%) 

<D Fcr, Feb 

Set to standard imaging condition II. Adjust light intensity to Y signal output average value 
(Ya). Then insert R or B filter, and test the C signal difference (ACr, ACb) between even 
field and odd field and the C signal output average value (CAr, CAb). 

Fci= (ACi/CAi) x 100 (%) (i = r, b) 



9. Lateral stripe 

Set to standard imaging condition II. Adjust light intensity to Y signal output average value 
(Ya). Then insert R, G and B filters respectively, and test the signal difference (AYIw, AYIr, 
AYIg, AYIb) between Y signal lines of the same field. 

Lci= (AYH/Ya) x 100 (%) (i=w, r, g, b) 

10. Residual image 

Adjust Y signal output value (Ys) by strobe light to 200mV. Then light a stroboscopic tube 
with the following timing and test the residual image (Ylag). 



I 



Lag= (Ylag/Ys) x 100 (90 



FLD 



SG1 



Strobe light timing 



Output 



_n 



Y lag (Residual image) 




-289- 



SONY® 



ICX039AK 




o 



290 



SONY® 



ICX039AK 



Spectral Sensitivity Characteristics 

(Excluding light source characteristics, including lens characteristics) 



w 
w 

z 
o 

0. 
V) 
Ul 

oc 

UJ 

> 









N 












T.S 






cy 




J/gi 




























































\^ M 9 









































400 



500 600 

WAVE LENGTH tnm] 



700 



I 



Using read out clock timing chart 



ODD FIELD < 



EVEN FIELD < 



HD 

VI 
V2 

V3 
V4 



VI 
V2 

V3 
V4 



41.8 



'2.51 
i i 



I. i 
I I 



!l.5 I 2.6 



,J2.5 






25 



Unit : ms 



-291 



SONY® 



ICX039AK 



fl> 

> 



.C 

o 



Q Q iC Q 

-I > -I I 



Qh 
U 3 
OO 



292 



SONY® 



ICX039AK 



L 



c 
o 

o 

X 



.c 
O 

c 
E 

> 



I 



293 



SONY® ICX039AK 



Handling Instructions 

1) Static charge prevention 

CCD image sensors are easily damaged by static discharge. Before handling be sure to take 
the following protective measures. 

a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use 
conductive shoes. 

b) When handling directly use an earth band. 

c) Install a conductive mat on the floor or working table to prevent the generation of static 
electricity. 

d) Ionized air is recommended for discharge when handling CCD image sensor. 

e) For the shipment of mounted substrates use boxes treated for the prevention of static 
charges. 

2) Soldering 

a) Make sure the package temperature does not exceed 80 °C. 

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. 
Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For 
repairs and remount, cool sufficiently. 

c) To dismount an imaging device do not use a solder suction equipment. When using an 
electric desoldering tool use a thermal controller of the zero cross On/Off type and 
connect to ground. 

3) Dust and dirt protection 

a) Operate in clean environments (around class 1000 will be appropriate). 

b) Do not either touch glass plates by hand or have any object come in contact with glass 
surfaces. Should dirt stick to a glass surface blow it off with an air blow. (For dirt 
stuck through static electricity ionized air is recommended) 

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be 
careful not to scratch the glass. 

d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or 
precool when moving to a room with great temperature differences. 

e) When a protective tape is applied before shipping, just before use remove the tape 
applied for electrostatic protection. Do not reuse the tape. 

4) Do not expose to strong light (sun rays) for long periods, color filters are discolored. 

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid 
storage or usage in such conditions. 

6) CCD image sensor are precise optical equipment that should not be subject to mechanical 
shocks. 

7) Defect compensation ROM 

This is shipped in its own case in pair with the CCD image sensor. 

Pair with the CCD image sensor bearing the same serial number during mounting. When 

the CCD image sensor has no defect, there is no ROM or serial number. 



294- 




CCD Imager System 




3) CCD Imager System 



Type 


Application 


Function 


Page 


IS018CL 


CCD imager system kit 
for B/W camera 


ICX018CL and three peripheral hybrid 
ICs, for EIA 


297 


IS021CL 


ICX018CL and three peripheral hybrid 
ICs, for CCIR 


IS026BK 


CCD imager system kit 
for color camera 


ICX018CL and five peripheral hybrid 
ICs, for NTSC 


301 


IS027BK 


ICX018CL and five peripheral hybrid 
ICs, for PAL 



-296 



SONY. 



IS018CL/IS021CL 



B/W CCD Imager System 



Description 

This new B/W imager system consists of a 
CCD imager IC with peripheral hybrid ICs, and 
makes possible the realization of very compact 
B/W CCD cameras. 
CCD imager 

ICX018CL: for EIA (51 OH x 492V) 
ICX021CL: for CCIR (500H x 582V) 

Hybrid ICs 

BX-1430: for CCD drive and timing (EIA) 
BX-1431: for CCD drive and timing (CCIR) 
BX-1432: for signal processing (EIA) 
BX-1432A: for signal processing (CCIR) 
BX-1433: for Gen Lock (EIA) 
BX-1433A: for Gen Lock (CCIR) 

Features 

CCD imager 

• High sensitivity 

• Gamma characteristic 7 = 1 

• Low lag, no burning 

• Low smear 

P-sub, P-well structure 

• Anti-blooming 

Hybrid ICs 

• No adjustment require 

• Gamma correction ON/OFF (0.45/1) 

• AGC ON/OFF 

• UL approved 



Top View 




See page 4 



System Combination 



Type Name 


System Combination 


IS018CL-1 


ICX01 8CL + BX-1 430 + BX-1 432 + BX-1 433 


2 


ICX01 8CL + BX-1 430 + BX-1 432 


3 


ICX018CL + BX-1430 + BX-1433 


4 


ICX018CL + BX-1430 


IS021CL-1 


ICX021 CL + BX-1 431 + BX-1 432A + BX-1 433A 


2 


ICX021CL + BX-1 431 + BX-1432A 


3 


ICX021CL + BX-1431 + BX-1433A 


4 


ICX021CL + BX-1 431 



I 



Absolute Maximum Ratings (Ta = 25°C) 



Jtem 


Hybrid ICs 


CCD imager 


Supply voltage 


BX-1 430/ 1431 
VCC1 20 V 
VCC2 16 V 
VCC3 10 V 

BX-1432/1432A 
VCC1 15 V 
VCC2 15 V 

BX-1433/1433A 
VCCl 12 V 
VCC2 65 V 


VDD1 

VDD2 -0 3 to 30 V 

VPO 


Allowable power 
dissipation 


BX-1430 1431 

850 mW 
BX-1432/1432A 

870 mW 
BX-1433/1433A 

350 mW 




Operating temperature 


-10 to +60 °C 


-10 to +55 °C 


Storage temperature 


-30 to +85 °C 


-30 to +80 °C 



60707B-TO 



-297- 



SONY® 



IS018CL/IS021CL 



Block Diagram 



Lens 



BX-1433/BX-1433A 



ICX018CL/021CL 

r -- 



Phase 
Comparator 



CCD 
Imager 



c 



Vertical 
Driver 



Horizontal 
Driver 



Timing 
Generator 



± 



Sample Hold 



Pulse 
Generator 



I Hybrid IC 
J for Ext Sync 



Synchronous 

Signal 

Generator 



BX-1430/BX-1431 



__ AGC. _ 

Auto Iris 



7 ON/OFF 



LPF 



±2: 



Hybrid IC 
for Driver 



Hybrid IC 

for Signal 

J Processor 



Y Signal 
Processor 



BX-1432/BX-1432A 




CCD B/W IMAGER SYSTEM 
IS018CL/IS021CL 



AGC ON/OFF 



EXT SYNC IN 
(HD.VD) 



"@ 



VIDEO OUT 
© 



Operating Characteristics 

Evaluation Board 



Item 



EIA specification 



CCIR specification 



Scanning system 



525 lines 
30 frame/sec. 



625 lines 
25 frame/sec. 



2 : 1 interlace 



Video signal 



1 .0 Vp-p, 75 O, negative sync 



Horizontal resolution 



350 TV lines 



S/N ratio 



More than 50 dB 
(with AGC off, y off) 



Power dissipation 



1.6W 
(without auto iris) 



Sync system* 



Internal/External 
(external using BX-1433A, external input pulses HP, VD) 



•Note) Recommended external VCO sync signal : quasi-sinusoidal output 

FOSC-04 manufactured by FUJI SANGYO CO. 



298- 



SONY® 



IS018CL/IS021CL 



» 















> 
8 


> 


> 


> 


o 

z 
o 


a 

Z 
U 



o 2 "" " 

s ' 

Sz«~ 

© - CM 

> as§ 



TOP 



i ii.i 



o en g ; 



ni 






COT 



-io74*- 



I 



COT 



Vcont 
OSC 



r a 7i 

6 I 



I •- N QD 0> O 



T 



i¥ 



TT 



TT 



Ilk 



k 1 



E 
2 

(0 

5 
m 



!©, 



299- 



SONY® 



IS018CL/IS021CL 



Package Outline 



2-^2.5 



02.0 



Unit: mm 




.,■1.27 _. 
ICX018CL/ICX021CL 





BX-1430/BX-1431 






BX-1432 



BX-1433 



1430/31 


37.0 


31.2 


3.5 


7.0 


1432/A 


37.0 


31.0 


3.5 


7.0 


1 433/A 


37.0 


26.0 


3.5 


7.0 



Allowable tolerance: 0.3 mm 
BX-1430/BX-1431 
BX-1432/BX-1432A 
BX-1433/BX-1433A 



300 



SONY. 



IS026BK/IS027BK 



CCD Color Imager System 



Description 

This new color imager system made up of a CCD 
imager and peripheral hybrid IC's realizes very com- 
pact CCD color cameras. 

Improvement in sensitivity characteristic has been 
realized through the adoption of ICX 026 BK/027 BK. 
The system is available whereas independent hybrid 
IC's are not. 

• CCD imagers 
ICX026BK (NTSC) 
ICX027BK(PAL) 



Top View 



• Hybrid IC 


s 






SBX1 547-01 


Drive and AGC circuit 




SBX1 543-01 


Matrix circuit 


NTSC 


SBX1 548-01 


Encoder 




SBX 1599-01 


VBS gen-lock 




SBX1 546-01 


AWB circuit 




SBX 1547-21 


Drive and AGC circuit 




SBX1 543-01 


Matrix circuit 


PAL 


SBX1 548-21 


Encoder 




SBX1 599-21 


VBS gen-lock 




SBX 1546-01 


AWB circuit 



Features 

• CCD imager 

High sensitivity (Low dark current) 
High resolution 

Variable speed electronic shutter function 
N-sub, P-well structure 

• Hybrid IC's 

No adjustment required : Function trimming used 

Highly compact mounting : Small size IC package 

used 

UL approved 

• System kit 

Peripherals greatly reduced 

Gen lock for color framing adaptable 

Color difference signals, Y/C separated signals 

output 

AGC ON/OFF possible 



ICX026/027BK 




SBX 1547 




SBX 1546 



Imager system 


System structure 


N 

T 
S 
C 


IS026BK-30F 


ICX026BK-3 +SBX1 54701 


IS026BK-30G 


ICX026BK-3 +SBX1 54701 

+SBX1 54301 + SBX1 548-01 


IS026BK-30J 


ICX026BK-3 +SBX1 54701 

+SBX1 543-01 +SBX1 548-01 
+ SBX1 599-01 


IS026BK-30H 


ICX026BK-3 +SBX1 54701 

+SBX1 543-01 +SBX1 548-01 
+SBX1 54601 


IS026BK-30K 


ICX026BK-3 +SBX1 54701 

+SBX1543-01 + SBX1548-01 
+ SBX1 599-01 +SBX1 546-01 


P 
A 
L 


IS027BK-30F 


ICX027BK-3 +SBX1 547-21 


IS027BK-30G 


ICX027BK-3 +SBX1 547-21 

+SBX1 54301 +SBX1 548-21 


IS027BK-30J 


ICX027BK-3 +SBX1 547-21 

+SBX1543-01 + SBX1548-21 
+ SBX1599-21 


IS027BK-30H 


ICX027BK-3 +SBX1547-21 

+ SBX1543-01 +SBX1548-21 
+SBX1546-01 


IS027BK-30K 


ICX027BK-3 +SBX1 547-21 

+SBX1 543-01 +SBX1 548-21 
+SBX1 599-21 +SBX1 546-01 



E89420-HP 



-301 - 



SONY® 



IS026BK/IS027BK 



Systems 

Absolute maximum ratings (Ta : 



25X) 



Item 


Hybrid ICs 


CCD 
Image 


r 


SBX1547 


SBX1543 


SBX1548 


SBX1599 


SBX1546 


Supply 
voltage 


Vccl 6.3 V 


Vccl 6 V 


Vccl 6.3V 


Vccl 6.3V 


Vccl 7V 


VddI i 




Vcc2 20V 






Vcc2 12V 




Vdd2 


20V 


Vcc3 25V 










Vpd 




Vcc4 -16V 










Vss J 














VSUB 


55V 


Operating 
temperature 


-10 to +60°C 


Storage 
temperature 


-30 to +80°C 



Hybrid ICs recommended operating conditions 



SBX1547 


SBX1543 


SBX1548 


SBX1599 


SBX1546 


Supply 
voltage 
(V) 


Current 

consumption 

(mA) 


Supply 
voltage 
(V) 


Current 

consumption 

(mA) 


Supply 
voltage 
(V) 


Current 

consumption 

(mA) 


Supply 
voltage 
(V) 


Current 

consumption 

(mA) 


Supply 
voltage 
(V) 


Current 

consumption 

(mA) 


Vccl 
5±0.25V 


105(Typ.) 


Vcci 
5±0.25V 


100(Typ.) 


Vcci 
5±0.25V 


95(Typ.) 


Vcci 

5 ± 0.25V 


20(Typ.) 


Vcci 
5±0.25V 


2.5(Typ.) 


VCC2 

15±0.45V 


12(Typ.) 










VCC2 

8.5±0.5V 


15(Typ.) 






VCC3 
22+1.5V 


0.5(Typ.) 


















VCC4 

-9.5±0.5V 


2(Typ.) 



















System Operating Characteristics 
Evaluation board 





NTSC Specifications 


PAL Specifications 


Scanning system 


525Lines 
30fra me/sec. 


625Lines 
2 5fra me/sec. 


2: 1 Interlace 


Video signal 


l.OVp-p, 750, Negative sync signal 


Horizontal resolution 


330TV Lines 


S/N ratio 


More than 43dB 
(AGC off, yon) 


Power consumption 


1.8W 
(Without AWB, Gen-lock) 


Sync system 


Internal/External selection possible, 
/composite video signal input to\ 
\hybrid IC for external sync use / 



-302- 



SONY® 



IS026BK/IS027BK 



Electrical characteristics 1 (Ta = 25°C) 












Item 


Symbol 


Test condition 


Min. 


Typ. 


Max. 


Unit 


E 

<D 

w 

>> 
CO 

Hi 

o 

< 


Vertical 
transfer clock 
^Vl, ^V3 


H level 


Vt 




13 


15 


17 


V 


M level 


VVM 




-0.5 





0.7 


Amplitude 


V*v 




8 




11 


Vertical transfer 
clock 4>M2, 4>\I4 


H level 


VVM 




-0.5 





0.7 


V 


Amplitude 


V*v 




8 




11 


Horizontal 
transfer clock 
^Hl, ^H2 


L level 


Vhl 








0.5 


V 


Amplitude 


V*H 




4.5 


5 


5.5 


Precharge clock 
<£PG 


L level 


Vpgl 








0.5 


V 


Amplitude 


V^PG 




9 




12 


Substrate clock 
<£SUB 


Amplitude 


V^SUB 




30 




35 


V 


Color separation 
output 


Sl S 2 , Y output 


Vf 


Input data 150mVp-p 




500 




mVp-p 


DC output 


VfDC 


DC bias 


1.8 


1.9 


2.0 


V 


IRIS output 


IRIS output 


VlR 






285 




mVp-p 


DC output 


VlRDC 


DC bias 


1.8 


1.9 


2.0 


V 



Electrical characteristics 2 (Ta = 25°C) 



Item 


Symbol 


Test condition 


Min. 


Typ. 


Max. 


Unit 


E 

CO 
UJ 

o 
CD 


R, G, B, 
output 


o 
en 

i- 
z 


R 


Vrnt 


Standard Imaging Condition, 
Application system circuit 


340 


400 


460 


mV 


G 


Vgnt 


Standard Imaging Condition, 
Application system circuit 


450 


520 


590 


B 


Vbnt 


Standard Imaging Condition, 
Application system circuit 


210 


260 


310 


< 

0_ 


R 


Vrpa 


Standard Imaging Condition, 
Application system circuit 


310 


370 


430 


mV 


G 


Vgpa 


Standard Imaging Condition, 
Application system circuit 


480 


550 


620 


B 


Vbpa 


Standard Imaging Condition, 
Application system circuit 


240 


290 


340 


DC 


VCLDC 


DC bias 


1.7 


1.9 


2.0 


V 


WB Control 


Cont32 


VC32 


Typ. (3200°k) DC bias 




1.0 




V 


Set up level 


Vset 






20 


50 


mV 


Sync level 


NTSC 


VSYNT 




250 


285. 


320 


mV 


PAL 


VSYPA 




270 


300 


330 


Burst level 


NTSC 


Vbunt 




250 


285 


320 


mV 


PAL 


Vbupa 




270 


300 


330 



Definition of Standard Imaging condition 

A pattern box (luminance 706 Nit, Color temperature 3200°K, with halogen lamp) is imaged using a test 
standard lens, F5.6 contraction, at that time there is no pattern and CM-500S l.Ommt is utilized as I.R 
cut filter. 



303- 



SONY® 



IS026BK/IS027BK 



AGC Amp gain control characteristics 

(SBX1547) 



20 



o 

o 
o 

< 10 

















cc=5V, 
b=25*C 
















V 

T 












































' 


















/ 








































AG 
AG 


-CMAX 
= 4V 
















£SEL 










/ 








l] 


4V 




I 




/ 


/ 



















12 3 4 

AGC CONT Voltage (V) 



AGC Amp Max. gain control characteristics 

(SBX1547) 

























CD 40 
■D 
















Ta = 25*C 






















< 30 

1- 

< 








































Q 

)Z 20 

O 
























I 












AGC 
CONT 


O 

2 <° 


















= 4V 
















AGC SEL 
= 4V 

























12 3 4 5 

AGC MAX control voltage (V) 



O soo 






y=1.8V 



Yy characteristics 

(SBX1543) 






YIN input level (mV) 



-304- 



SONY® 



IS026BK/IS027BK 



SYNC level temperature characteristics 

(SBX1548) 



o 



50 

Ta-Ambient temperature CC) 

Burst level temperature characteristics 

(SBX1548) 















































> 

E 










































ST leve 
o 














































cr 

Z) 

m 
































































200 























50 

Ta-Ambient temperature (°C) 
C-y control characteristics 

(SBX1548) 



000 


















1 











































































































































































































VIDEO OUT pin pedestal DC 

(SBX1548) 



£ 2.2 

































Y„ 


IN = 


= 250mV 





































































































































































50 

Ta-Ambient temperature (°C) 

SET UP level temperature characteristics 

(SBX1548) 



























































































50 












































































































«>n 























I 



50 

Ta-Ambient temperature (°C) 
WB R, B CONT control characteristics 

Output is taken at 1 when (SBX1548} 



R,B CONT control is IV. 




Input voltage (mV) 



R,B CONT Control Voltage (V) 



305 - 



SONY® 



IS026BK/IS027BK 



*$h-® = : 




.* 


xt 


o 


CD , 


o 


w fe 






OQ 


o 


E 


I 


a> 




+* 




CO 




>, 




to 





-306 



SONY® 



IS026BK/IS027BK 




I 



-307- 



SONY® 



IS026BK/IS027BK 



Package Outline Unit: mm 



20pin DIP (Ceramic) 



■fv Effective elements }*■ 
f picture center 



il> 



ICX026BK-3 
ICX027BK-3 






SBX1547-01/02 




SBX 1548-01/21 




©PIN 



SBX1 599-01/02 



SBX1 546-01 








19. C m 






1 








vD 








• 


2 


i ^ 


_, 1.8^8=14.4 







-308- 



SONY® 



IS026BK/IS027BK 



CCD image sensor Handling Instructions 

1) Static charge prevention 

CCD image sensor are easily damaged by static discharge. Before handling be sure to take the following 
protective measures. 

• Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. 

• When handling directly use an earth band. 

• Install a conductive mat on the floor or working table to prevent the generation of static electricity. 

• Ionized air is recommended for discharge when handling CCD image sensor. 

• For the shipment of mounted substrates use boxes treated for the prevention of static charges. 

2) Soldering 

• Make sure the package temperature does not exceed 80°C. 

• Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 
30 W soldering iron and solder each pin in less than 2 seconds. For repairs and remount cool 
sufficiently. 

• To dismount an imaging device do not use a solder pult. When using an electric desoldering tool use 
a thermal controller of the zero cross On/Off type and connect to ground. 

3) Dust and dirt protection 

• Operate in clean environments (around class 1000 will be appropriate). 

• Do not either touch glass plates by hand or have any object come in contact with glass surfaces. 
Should dirt stick to a glass surface blow it off with an air blow. (For dirt stuck through static electricity 
ionized air is recommended). 

• Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to 
scratch the glass. 

• Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool when 
moving to a room with great temperature differences. 

• When a protective tape is applied before shipping, just before use remove the tape applied for 
electrostatic protection. Do not reuse the tape. 

4) Do not expose to strong light (sun rays) for long periods to ultra violet rays, color filters are discolored. 

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or 
usage in such conditions. 

6) CCD image sensor are precise optical equipment that should not be subject to mechanical shocks. 

7) Defect compensation ROM 

• This is shipped mounted on SBX1547 in pair with the CCD image sensor. To load on the set, match 
with a CCD image sensor bearing an indentical serial number label. 

When there is no defect there is no ROM or serial number. 



I 



309- 



IC for Scanning System 
of Video Camera 




4) IC for Scanning System of Video Camera 



Type 


Application 


Function 


Page 


CXD1030M 


Sync signal generator 


14MHz (18MHz) demultiplier, for 
NTSC, PAL 


313 


CXD1158M 


Sync signal generator 


14MHz (18MHz) demultiplier, for 
NTSC, PAL sub carrier output X 3 


322 


CXD1159Q 


Sync signal generator 


14MHz (18MHz) demultiplier, for 
NTSC, PAL window pulse output 


332 


CXD1217M 


Sync signal generator 


Compatible with the respective systems, 
NTSC, PALM, PAL and SECAM 
color framing by the respective systems, 
NTSC, PALM, PAL and SECAM 


341 


CX23047B 


Timing pulse generator 
for scanning system 


CCD drive timing pulse generation, sig- 
nal processing pulse generation, for 
ICX018CK/CL, ICX021CK/CL 


353 


CXD1035BQ-Z 


Timing pulse generator 
for scanning system 


CCD drive timing pulse generation, sig- 
nal processing pulse generation, for 
ICX022AK/AL, ICX024AK/AL 


364 


CXD1141M 


Variable electric shut- 
ter timing generator 


Variable electronic shutter timing gener- 
ation (1/60 to 1/10000 sec.) for 
ICX022AK/AL, ICX024AK/AL 


376 


CXD1156Q/R 


Timing Generator for 
CCD driving Camera 


CCD drive timing pulse generation, Vari- 
able electronic shutter timing generation 
(1/60 to 1/10000 sec,) for ICX026BK/BL, 
ICX027BK/BL 


380 


CXD1251Q 


Blemish compensation 
timing generator 


Blemish compensation timing generator, 
for ICX026BK/BL, ICX027BK/BL 


393 


CXD1255Q 


Timing Generator for 
CCD driving Camera 


CCD drive timing pulse generation, sig- 
nal processing pulse generation, for 
ICX038AK/ICX039AK 
variable electronic shutter timing gener- 
ation (1/60~1/10000 sec) 


398 


CXB0026AM 


CCD clock driver 


CCD imager driver X 2, compatible with 
high frequency operation 


412 


CX20180 


Vertical clock drive 


CCD imager driver X 4, lead-out genera- 
tion inverter, negative voltage genera- 
tion inverter 


415 


CXA1065M 


Vertical clock drive 


CCD imager driver x 4, lead-out genera- 
tion inverter, negative voltage genera- 
tion inverter 


426 


CXD1250M 


Vertical clock drive 


CCD imager driver X 4, lead-out genera- 
tion inverter 


441 



312- 



SONY. 



CXD1030M 



Sync. Signal Generator for Camera 



Description 

The CXD1030M is a sync, signal generator for 
video cameras. 

Features 

• Adapts to NTSC or PAL by switching mode 

• Low power consumption 

(Standard NTSC: 25 mW; PAL: 30 mW) 

• Built-in phase comparator and inverter for ac- 
tive filter (separate power supply for the filter 
inverter) 

• External sync. 

Function 

Sync, signal generator 

Structure 

Silicon gate CMOS IC 



Package Outline 



Unit: mm 



28 pin MFP 




hnnnnnnnnnnniinil 



~J H&±QM\®\ 



MFP-28P-L02 



Application 

Video • Camera 

Absolute Maximum Ratings (Ta = 25°C) 

• Supply voltage 

• Input voltage 

• Output voltage 

• Operating temperature 

• Storage temperature 
* VSS = 0V 

Recommended Operating Conditions 

• Supply voltage 

• Operating temperature 



VDD 


VSS*-0.3 to 7.0 


V 


VI 


VSS*-0.3 to VDD + 0.3 


V 


VO 


VSS*-0.3 to VDD + 0.3 


V 


Topr 


-20 to +75 


°C 


Tstg 


- 55 to + 1 50 


°C 


tions 

VDD 


4.50 to 5.50 


V 


Topr 


-20 to +75 


°C 




70110-TO 



313- 



SONY® 



CXD1030M 



Block Diagram 



FSCI 
FSC0(25] 




CLKI (JO 
CLKO (u 




1/7 or 6 
I 



L-^KiMBK^ 



I 



O 



PHASE 
COMPARATOR 



1/525 or 625 



I 



I 



V- CONTROL 



U. OUTPUT CONTROL 



OK£HyKfK2H^H!3> 



<20)C0MP 




314 



SONY® 



CXD1030M 



Pin Configuration (Top View) 

^e][i71[iil|ii|R|Hl|iilF[|i5|HP8]p7|ni1[m 



1 pin indication 




LilliJLiJLiJliJLiJLiJliJliJli£JliLJlHJlHJliiJ 



Pin Description 



No. 


Symbol 


I/O 


Description 


1 


HDO 





Horizontal drive pulse 


2 


VDO 





Vertical drive pulse 


3 


SYNC 





Complex synchronized pulse 


4 


BLKO 





Complex branking pulse 


5 


BFO 





Burst flug pulse 


6 


HR 




H reset input 


7 


VR 




V reset input 


8 


LR 




LALT reset input 


9 


EXT 




Internal/external mode switching INT/EXT 


10 


CLKI 




Clock input (NTSC: 14.31818 MHz, PAL: 14.1875 MHz) 


11 


CLKO 





Clock output 


12 


FLD 





Field pulse 


13 


LALT 





Line alternate pulse 


14 


VSS1 


- 


GND 


15 


SCOF 


1 


Sub carrier suppress input L: OFF 


16 


MODE 


1 


NTSC/PAL mode switching NTSC/PAL 


17 


VINT 


1 


Initialize input 


18 


PSEL 


1 


Phase comparator polarity switching 


19 


VDD2 


- 


Inverter + 5V for filter 


20 


COMP 





Phase comparator output 


21 


AIN 


1 


Inverter input for filter 


22 


AOUT 





Inverter output for filter 


23 


VSS2 


- 


Inverter GND for filter 


24 


FSCI 


1 


4fsc clock input 


25 
26 
27 
28 


FSCO 





4fsc clock output 


SC 





Sub carrier output 


TEST 
Vddi 


1 


Test input (L normal) 


- 


+ 5V 




-315 



SONY® 



CXD1030M 



Electrical Characteristics 

DC characteristics 









VDD = 5V ± 1 0% , VSS = OV, Topr = 


-20 to 


+ 75°C 


Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Supply current 


IDD 


Test circuit (2) 




2.0 




mA 


IDDS 


Static state* 1 







0.1 


mA 


Output voltage I* 2 


H level 


VOH 


Ioh= - 1.0 mA 


Vdd-0.5 




Vdd 


V 


L level 


Vol 


Iol= 1.0 mA 


Vss 




0.4 


V 


Output voltage II* 3 


H level 


Voh 


Ioh= -0.5 mA 


Vdd-0.5 




Vdd 


V 


L level 


Vol 


Iol = 0.5 mA 


Vss 




0.4 


V 


Input voltage 


H level 


Vih 




0.7VDD 






V 


L level 


VlL 








0.3VDD 


V 


Input leak current 


lu 


Vi = OV to Vdd 


-25 




25 


tiA 


Input leak current* 4 


ILZ 


-40 




40 


MA 



Note) *1 Vih = Vdd, Vil-Vss 

*2 Output pins except "AOUT" 
*3 "AOUT" pin 
*4 Three state pin 

I/O Capacitance 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Input pin 


ClN 






12 


pF 


Output pin 


COUT 






12 


pF 



Test condition: Vdd = Vi = 0V, f M = 1 MHz 

Filter amplifier characteristics 

Voltage gain Gv 23dB (Typ.) 
Test circuit (1 




14MHz 
External clock 



-316- 



SONY® 



CXD1030M 



Description of Function 

1. Generation of various sync, signals (See the Timing Chart.) 
Various sync, signals are generated from clocks. 

• Clock frequencies 

NTSC: 910 fH (14.31818 MHz) 
PAL : 908 fH (14.1875 MHz) 

4fSC (17.734475 MHz) 

2. PAL 4 fSC PLL 

Using 908 fH as the master clock, the 4 fSC is put in phase. Corresponding to an external filter 
(passive or active), the phase comparator polarity can be switched. 



Filter 


PSEL 


Master 
(908fH) 


4fSC 


COMP 


Passive 


L 


Fast 


Slow 


H 


Slow 


Fast 


L 


Active 


H 


Fast 


Slow 


L 


Slow 


Fast 


H 



Mode 


INT or EXT 


SC 


NTSC 


INT 


910fH/4 


NTSC 


EXT 


4fSC/4 


PAL 


X 


4fSC/4 



3. SC (SubCarrier) generation 

' INT : INTERNAL mode 

(EXT = L) 

EXT: EXTERNAL mode 
(EXT = H) 

Unused counters are stopped in any of the mode. 

When SC is not required, any counters on SC are stopped and SC is not output by SCOF being 
set to L. 

4. Initialization and Reset 

In the INT mode, the circuit is initialized with the fall of VINT. At this time, the H reset, V reset, 
and LALT reset are not accepted. In the EXT mode, VINT is not accepted but the H reset, V reset, 
and LALT reset are accepted. 
• Initialization (VINT) 
When EXT is L, the fall of VINT is detected and operation is started by the circuit being initial- 
ized at the VD fall position immediately prior to field I. (The initialization is completed within 
100 ns after the fall is detected.) 



1 



u — u — u — u — u~ 



~~U U U LT 



U 



Initialize point 



Initialize point 



-317 



SONY® CXD1030M 

• H reset (HR) 
A reset is executed with the first fall but no reset will be done as long as the subsequent 
edges do not deviate by more than two clocks (0.98 fis). 
The minimum reset pulse width is 0.98 ^s. 
HD is reset 2.94 to 3.43 us in advance of HR input. 



0.98 /ts or more 

hr — |j ,. — ,p- 



HD' 



2.94 to 3.43/is 



V reset (VR) 

VD is reset 3.5H in advance of VR input. 

The minimum reset pulse width is 32 /is. 





32/ts 


or 


more 




t 




zr\ 


VD — 


V3.5H— ►! 






I 



LALT reset (LR) 

LALT is reset in the same phase as the LR input. 

The minimum reset pulse width is 32 /ts. 



32/ts or more 




JT 



-318 



SONY® 



CXD1030M 



Timing Chart H (NTSC) 



















HDO 


-6.36— | 






1 












BLKO 


10.76 -J 






1 






"1 




HSYNC 
(SYNC) 


r 


-4.8»-J 






1 


1.47- 






EO 

(SYNC) 




B 


1.47-^ 




u 

L_ 




VSYNC 1 
(SYNC) J 




1 


P 


r~ 




*~ * 




i 












BFO 
VD 


*- 


-6.85 —$^\ 




U 












[Unit: /is] 






1) 


■ 













Timing Chart H (PAL) 



*-6.41-J~ 



m — 

i 

j 



t 



& 



u 




u~ 



[Unit: us] 



-319- 



SONY® 



CXD1030M 



Timing Chart V (NTSC) 



FIELD I 



^r-irnr^r^Lf^rLnriririr^u^Lrir^L 

j. J 9H .[ | 

i^^irionnnrYinriJULJU^^ 



HDO 
VDO 
SYNC 




nririorirfnnmnajuuLJUu^^ 

— 1 2qh :i H n n n n r 

— [ inrxiririnnr 



bfo ^rr - ir~ir^r 

FLD 



Timing Chart V (PAL) 



FIELD I,m — 



-FIELD I , W 



HDO 
VDO 
SYNC 
BLKO 



iriririrnr^rir^mrirT^ririr^r*ir^r^rior 



irnjnj^r-irinnnnrliiJLiJirTiiTir^^ 



ir^nnr^n: 



^Lf^ru^r 



BFO(I-W) ~u u u u u 

BFO(I-II) ~~ If 




-irir^rnrnjirrrrriJULjLjunrini^^ 

— — 25H „ '!n r^rv- 



BFO.K-I. U 1 U If 

BFO(D-II> [J If 



innnnrir 

FT 




320- 



SONY® 



CXD1030M 



Application Circuits 
NTSC (Internal mode) 



•HQh< 






1 



In 



PAL (Filter configuration 1 , Internal mode) 



4f«c 
(17.73MHz)KXX3PK)OKlOK °^ 

■IDhrl" 




PAL (Filter configuration 2, Internal mode) 




I 



321 - 



SONY. 



CXD1158M 



Synchronizing Signal Generator for Consumer Video Camera 



Description 

CXD1 1 58M is a synchronizing signal genera- 
tor for video camera. 

Features 

• Adapts to NTSC or PAL by switching mode 

• Low power consumption 

• Built-in phase comparator and inverter for 
active filter (separate power supply for the filter 
inverter) 

• External sync 

Structure 

Silicon gate CMOS IC 

Application 

Consumer video camera 



Absolute Maximum Ratings (Ta = 25°C) 



Package Outline 



Unit: mm 



30 pin SOP (Plastic) 




innnnnnnnnnnnni i|i 



Supply voltage Vdd 

Input voltage Vi 

Output voltage Vo 

Operating temperature Topr 

Storage temperature Tstg 



VSS* 1 -0.3 to +7.0 V 

VSS* 1 -0.3 to Vdd + 0.3* 2 V 

VSS* 1 -0.3 to VDD + 0.3* 2 V 

-20 to +75 °C 

-55 to +150 °C 



SOP-30P-L01 



Note) *1. Vss = 0V 

*2. Normal value, Transient value 0.5V (20 to 30 ns) 



Recommended Operating Conditions 

• Supply voltage VDD 

• Operating temperature Topr 



4.5 to 5.5 
-20 to +75 



80307-TO 



322- 



SONY, 



CXD1158M 



Block Diagram 



FSCI (&} 
FSCO(» 




A IN (21 
A OUT (22)- 



O V 




UJ< \ 

LuUJ »/ 



■KgKSHgKsh 



> > > 



Pin Configuration (Top View) 



PHASE 
COMPARATOR 



4 SUB-CARRIER 
CONTROL 



n 



H -DECODER 



1/525 or 625 



H 



V-DECODER 



H 



V-CONTROL 



JSZ 



OUTPUT CONTROL 




<4< 



~® 




30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 

nnnnnnnnnnnnnnn 



Indicates pin 




uuuuUUUUUUUUUUU 

2 3 4 5 6 7 8 9 10 11 12 13 14 15 



-323 



SONY. 



CXD1158M 



Pin Description 



No. 


Symbol 


I/O 


Description 


1 


HDO 





Horizontal drive pulse 


2 


VDO 





Vertical drive pulse 


3 


SYNC 





Composite sync, pulse 


4 


XBLK 





Composite blanking pulse 


5 


XBFO 





Burst»flag pulse 


6 


HR 


I 


H reset input 


7 


VR 


I 


V reset input 


8 


LR 


I 


LALT reset input 


9 


EXT 


I 


INT/EXT mode switching 


10 


CLKI 


I 


Clock input 


11 


CLKO 





Clock output 


12 


FLD 





Field pulse 


13 


LALT 





Line alternate pulse 


14 


MODE 


I 


NTSC/PAL mode switching NTSC/PAL 


15 


Vss1 


- 


GND 


16 


XWHD 





Wide Horizontal drive pulse 


17 


CPO 





Clamp pulse 


18 


VINT 


I 


Initialize input 


19 


COMP 





Phase comparator output 


20 


Vdd2 


- 


Inverter + 5V for filter 


21 


AIN 


I 


Inverter input for filter 


22 


AOUT 





Inverter output for filter 


23 


Vss2 


- 


Inverter GND for filter 


24 


FSCI 


I 


Clock input 4 fsc 


25 


FSCO 





Clock output 4 fsc 


26 


SC1 





Sub carrier 1 


27 


SC2 





Sub carrier 2 


28 


BSC 





Bursted sub carrier 


29 


TEST 


I 


Test input (Normally L) 


30 


Vdd1 


- 


+ 5V 



-324 



SONY. CXD1158M 


Electrical Characteristics 

DC characteristics Vdd = 5V ± 1 0% VSS = OV Top =-20 to +75°C 


Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Supply current 


Idd 






2.0 




mA 


Idos 


Static state* 1 







0.1 


mA 


Output voltage I* 2 


H level 


Voh 


Ioh= -2mA 


Vdd -0.5 




Vdd 


V 


L level 


Vol 


Iol = 4mA 


Vss 




0.4 


V 


Output voltage II* 3 


H level 


Voh 


Ioh= - 1.5mA 


2.5 




Vdd 


V 


L level 


Vol 


Iol= 1.5mA 


Vss 




2.5 


V 


Input voltage 


H level 


VlH 




0.7 Vdd 






V 


Level 


VlL 








0.3 Vdd 


V 


Input leak current 


Ili 


Vi = 0V to Vdd 


-10 




10 


nA 


Output leak current* 4 


loz 


-10 




10 


mA 



*1. Vih = Vdd, Vil = Vss 

*2. Output pins except "A OUT' 

*3. "A OUT" pin 

*4. Tri-state pin 19 

AC characteristics 



Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


H to L Propagation delay time 


tPDL 


Vol = 0.4V 






45 


ns 


L to H Propagation delay time 


tPDH 


Voh = 2.4V 






45 


ns 



CLKI 




HDO 



I. IV 






l.-lV 



■ 



I/O capacitance 








VddVi = 0V, fM=1MHz 


Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Input pin 


ClN 






8 


pF 


Output pin 


COUT 






8 


PF 



-325 



SONY, 



CXD1158M 



Filter Amplifier Characteristics 

Voltage gain Gv: 25dB (Typ.) 



600Q 



O.l/uF 
II- 



lkHi 




Test circuit 



Description of Function 

Generation of various synchronizing signals (See the Timing Chart). 

Generates various synchronizing signals from Clock. 
• Clock frequency: 

NTSC: 910 fH (14.31818 MHz) 

PAL: 908 fH (14.1875 MHz) 
4fSC (17.734475 MHz) 



PLL for PAL 4 f SC 

Matches 4 fsc phase, with 908 fH as Master clock. 
An active filter is used as filter. 



908 fH 


4 fsc 


COMP 


Forward 


Back 


L 


Back 


Forward 


H 



Generation of SC (Sub-Carrier) 

Generates three kinds of sub-carrier. 

SC1, SC2 and BBC. (Refer to the Timing Chart for phase.) 



Mode 


Sync. 


Sub-carrier (SC) 


NTSC 


INT 


910fH/4 


NTSC 


EXT 


No output 


PAL 


INT or EXT 


4 fsc/4 



INT: INTERNAL mode (EXT = L) 
EXT: EXTERNAL mode (EXT = H) 



Any unused counter is stopped in any mode. 



326 



SONY* 



CXD1158M 



Initialize and Reset 

In the INT mode, the circuit is initialized at falling edge of VINT. H reset, V reset and LALT reset 
are not accepted in this mode. In the EXT mode, in contrast, VINT is not accepted, while H reset, 
V reset and LALT reset are accepted. 

• Initialize (VINT) 

Detection of VINT's falling edge causes, at the first clock, initialization at the position of falling 
edge of VD immediately before the ODD (1st) field to start operation. (Initialization is completed 
within 100 ns from the detection of falling edge.) 



NTSC VINT 




t 


















VD 












HD 






J u 


u u 


l-T 


FLD 


r 








' 


nitialization 


point 




PAL VINT 




♦ 
















VD 


~~ u 










HD 




u 


u u 


u 


FLD 


I 










Initialization 


point 





H reset (HR) 

It is reset at the first falling edge, and not reset unless there is an offset of over 2 clocks (0.98 

lis) for the next and subsequent edges. The minimum pulse duration is 0.98 us. 

The position of reset is at 2.94 to 3.43 us forward from HR input. 

Over 0.98 /is 



HR- 



HD- 



■ 



2.94 to 3.43 fis 

i ' 

• V reset (VR) 

It is reset at a position of VD at 3.5 H forward from VR. The minimum reset pulse duration is 32 jts. 



• LALT reset (LR) 

LALT is reset to the same phase as that of LR input. The minimum reset pulse duration is 32 /is. 



LR 



LALT 



JT 



327 



SONY. 



CXD1158M 



Timing Chart 



NTSC H 



HIX) 
XWHI) 
XBLK 



■»-6.36 — »| 

9.78 "J 



1ISYNC 

ISVNCI1.W 



(SYNC) 



i_r 



r~ 



u 



XBFO 
Cl'O 
YD 
FU) 



d^L 



~^r 



_n 



n 



Unit [/is] 



PAL H 











1 


i 


1 


MIX) 


«H 


1 




r~ 








xwni) 




9.80 mi 


i 












XBI.k 




-«■" -H 








1 






IISYXC 


; 


.,.H 






i r~ 








FQ 
(SYNC) 


~3 




u 


u 


V SYNC 


1 .„j 


q r 


h 






i 


i 
XBFO j» 


-6.9. -p] 


n 


I 

cpo j 


««] 




n 










™ IX 


\ 
/ 


' 
i 




■ 


1 










Fl.I) ' 


ODD 


EVEN 


~i 










I.AI.T 








X 












Unit [^S] 





-328- 



SONY. 



CXD1158M 



NTSC V 



HDO ~U U U U U U 

XWHD 

cpo i n i - i n a 

VDO 

SYNC ~U U U IT 

XBLK 
XBFOJ 

FLD 




HDO U U U U 

XWHD 

CPO n ( i n n n a 

VDO 

sync — u u — inrinnnr 

XBLK 

xbfo n n (i 

FLD 



PALV 




HDO 
XWHD 
CPO 
VDO 

SYNC ~U U IT 

XBLK 

XBFOdH -IV) _J1_J__L 

XBFO(I-II)_ll L 

LALT(III-IV)~1 T 

LALT(I-II) _T 
FLD 



FIELD II,IV 



"U LT 



HD 

XWDO 

CPO 

VDO 

SYNC 

XBLK 

XBFO(IV-I) 

XBFO(II-III) 

LALT(IV-I) 

LALT(II-III) — i i L 

FLD 



n r 



j L 



-FIELD I.III 



I 



U U U U U 1 J U U U U U U U LH U LT 



-7.5H- 



■_ii_ji_iLJLjr 



U U U ITl — U IT 



25H 



| n IL 



J L 



j L__r 



j 1 r 



329 



SONY. 



CXD1158M 



Sub Carrier 



NTSC 




PAL 

LALT=H 




LALT=L 




-330- 



SONY. 



CXD1158M 



Application Circuit 

NTSC (Internal mode) 





PAL (Internal mode) 



(17.73MHz! 10OOP 100K 10K0.01>J 75K 

HOI- - , , 




2 H3H 4 M 5 H 6 /v/y 



I 



331 - 



SONY. 

Sync. Signal Generator for Camera 



CXD1159Q 



Description 

CXD1159Q is a sync, signal generator for 
consumer video cameras. 

Features 

• Adapts to NTSC or PAL through mode 
switching. 

• Low power consumption. 

• Phase comparator and built in inverter for 
active filter. 

• Internal/External sync. 

Functions 

• Generator of various sync, signals. 

Structure 

Silicon gate CMOS 

Application 

• Video cameras 



Package Outline 



Unit : mm 



32 pin QFP (Plastic) 




m 



Hfll o.» 5 ! 



QFP-32P-L01 



Absolute Maximum Ratings (Ta = 25°C) 

• Supply voltage Vdd Vss * - 0.5 to 7.0 V 

• Input voltage Vi Vss *- 0.5 to Vdd + 0.5 V 

• Output voltage Vo Vss* -0.5 to Vdd + 0.5 V 

• Storage temperature Tstg -55 to +150 °C 
*Vss = 0V 

Rcommended Operating Conditions 

• Supply voltage Vdd 4.5 to 5.5 V 

• Operating temperature Topr - 20 to + 75 °C 



80924 - ST 



-332- 



SONY* 



CXD1159Q 



Block Diagram 



FSCI 
FSCO 




CLKI (6 
CLKO (7 




L-QH®-©-®- 



T 



i±. 



O 



PHASE 
COMPARATOR 



1/525 or 625 



I 



I 



L— V- CONTROL 



i± 



OUTPUT CONTROL 



#^^>4KiKl>-©^H4 



-<§< 




Pin Configuration 



HHHHRHHfl 



25 I I I 

an 
an 
an 
an 




I I I 16 

am 
am 
am 
am 
am 
nm 

I I I 9 



I 



-333 



SONY® 






CXD1159Q 


Pin Description 


No. 


Symbol 


I/O 


Description 


1 


BFO 





Burst flag pulse 


2 


HR 




H reset input 


3 


VR 




V reset input 


4 


LR 




LALT reset input 


5 


EXT 




Internal/External mode switching INT/EXT 


6 


CLKI 




Clock input (NTSC : 14.31 81 8MHz, PAL : 1 4.1875MHz) 


7 


CLKO 





Clock output 


8 


FLD 





Field pulse 


9 


N.C. 







10 


N.C. 







11 


LALT 





Line alternate pulse 


12 


Vssi 


— 


GND 


13 


SCOF 


I 


Sub carrier suppress input L : OFF 


14 


MODE 


I 


NTSC/PAL mode switching NTSC/PAL 


15 


VINT 


I 


Initialize input 


16 


PSEL 


I 


Phase comparator polarity switch 


17 


COMP 





Phase comparator output 


18 


VDD2 


— 


+ 5 power supply for filter inverter 


19 


AIN 


I 


Input for filter inverter 


20 


AOUT 





Output for filter inverter 


21 


VSS2 


— 


GND for filter inverter 


22 


FSCI 


I 


4 fsc clock input 


23 


FSCO 





4 fsc clock output 


24 


SC 





Sub carrier output 


25 


WNDE 


I 


WND output enable input (at L : Enable) 


26 


WND 





Window output 


27 


TEST 


I 


Test input (Normally "L") 


28 


Vddi 


— 


+ 5V 


29 


HDO 





Horizontal drive pulse 


30 


VDO 





Vertical drive pulse 


31 


SYNC 





Composite sync, pulse 


32 


BLKO 





Composite blanking pulse 



-334 



SONY® 



CXD1159Q 



Electrical Characteristics 
DC characteristics 









Vdd = 5V ± 


10%, Vss 


= 0V, Topr = - 20 


to +75^C 


Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Supply current 


I DO 






2.0 




mA 


Idds 


Static state*' 







0.1 


mA 


Output voltage I * 2 


H level 


Voh 


Ioh = — 2mA 


Vdd - 0.5 




Vdd 


V 


L level 


Vol 


Iol = 4mA 


Vss 




0.4 


V 


Output voltage II * 3 


H level 


Voh 


Ioh = — 1 .5mA 


2.5 




Vdd 


V 


L level 


Vol 


Iol = 1 .5mA 


Vss 




2.5 


V 


Input voltage 


H level 


VlH 




0.7Vdd 






V 


L level 


VlL 








0.3VDD 


V 


Input leak current 


Ili 


Vi = OV to Vdd 


-10 




10 


uA 


Input leak current* 4 


Ilz 


-10 




10 


uA 



* 1 . Vih = Vdd, Vil = Vss 

* 2. Output pins except "AOUT" 

AC characteristics 



* 3. "AOUT" pin. 

* 4. Three state pin. 



Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Falling edge delay time 


tPDL 


Vol = 0.4V 






45 


ns 


Rising edge delay time 


tPDH 


Voh = 2.4V 






45 


ns 




I/O capacitance 



Test circuit 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Input pin 


ClN 






8 


PF 


Output pin 


COUT 






8 


PF 



Test conditions : Vdd = Vi = 0V, fM = 1 MHz 
Filter amplifier characteristics 

Voltage gain Gv 25dB (Typ.) 




-335- 



SONY® 



CXD1159Q 



Functions 

1. Generation of various sync, signals (See the Timing Chart.) 
Various sync, signals are generated from clocks. 

• Clock frequencies 
NTSC:910f H (14.31818MHz) 
PAL: 908f H (1 4.1875MHz) 

4fsc (17.734475MHz) 
For the System Clock 
NTSC : 910f H /7 
PAL : 908f H /7 or 6 

2. PAL PLL for 4fsc 

To a master clock of 908fH is matched a phase of 4fsc The polarity of the phase comparator 
can be switched according to the type of external filter (passive or active). 



Filter 


PSEL 


Master 
(908f H ) 


4fsc 


CCMP 


Passive 


L 


Fast 


Delay 


H 


Slow 


Fast 


L 


Active 


H 


Fast 


Delay 


L 


Slow 


Fast 


H 



3. SC (Sub-Carrier) generation 

SC I 

INT : Internal mode 

(EXT = L) 

EXT : External mode 

(EXT = H) 

In either mode unused counters are stopped. When SC is not required, by setting SCOF to L 
all SC counters are stopped and SC is not output. 



Mode 


INT or EXT 


SC 


NTSC 


INT 


910f H /4 


NTSC 


EXT 


4fsc/4 


PAL 


X 


4fsc/4 



-336- 



SONY® 



CXD1159Q 



4. Initialization and Reset 

In INT mode the circuit is initialized with the fall of VINT. At that time, H, V and LALT resets 

are not accepted. In EXT mode, VINT is not accepted, whereas H, V and LALT resets are. 

• Initialize (VINT) 
When EXT = L, VINT fall is detected and operation is started as the circuit is initialized at 
the VD fall position just before field 1. (Initialization is completed within 100ns after the fall 
is detected). 



11 



U — U U — U U~ H0 LT 



u — u — u — if 



Initialize point Initialize point 

H reset (HR) 

Reset is performed with the first fall. However reset is not done anymore unless there is a 

deviation of more than 2 clocks (0.98 us) to the subsequent edges. 

The minimum reset pulse width is 0.98 us. 

HD.is reset 2.94 to 3.43 in advance of HR input. 

more than 0.98 us 



~L 



2.94 to 3.43 us 



• V reset (VR) 

VD is reset 3.5H in advance of VR input. 
The minimum reset pulse width is 32 us. 

• LALT reset (LR) 

LALT is reset in the same phase as LR input. 
The minimum reset pulse is 32 us. 

« 1 

^ _j i n 



■ 



-337 



SONY® 



CXD1159Q 



Timing Chart H (NTSC) 











1/2H 


1 


H 




H00 


-6.36^| 








1 




^_ 








BLKO 


10.76 •] 








1 








HSYNC 
ISYNCI 


F 


-4.89-J 








1 1 








EO 
(SYNC) 




a 


1. 


47-' 


u 




VSYNC I 
(SYNC) J 






_J 


r^ 


1 






' 


4.89 


n 














BFO 
VD 


^_ 


-6.B5 .[2| 




u 
















FLD 


ODD 






1 EVEN 
























"•—-~ 













Unit : (is 



Timing Chart H (PAL) 



»i-4.93-r 



+LT 



T_T 



__J 4.93 



I , T^ K- 47 ! 



i_r 



Unit : ms 



-338 



SONY® 



CXD1159Q 



Timing Chart V (NTSC) 



0: ODD 
E: EVEN 



moo nrTjnr^riry~irirTjnririr^rirnrnrijnnri^^ 

voo J" I — 9H 'I ! 

s^Nc -ir^riririr^nrTinnrjjuujjLJUTi^^ 

blko innnn n- i 20H - ~ } — -in nnT" 



B ro TTTTT 



H0O 
VDO 



blko "TTU - ITLT Ut 
TTTTT 



Tnrnr~ir~rnrirnr 



JUl Jl 



TTJT~irirnrirTrTrirTirirYrTrnr n J~Troririririr 



nriririrTirFirTirTLXJLJiJLJUinnrT^ 



^raLrrrTJTJ 



T~ir~irrnry 



JLJl. 



Timing Chart V (PAL) 



FIELD LID *p ntLU * . i* 

i J r -ir- i r^nrTnnrTn J ^LrTrir^^T r -i_r 



unnfirinr 



irTfirTTr|jTinnriJULJuij]nr^^ 

:£jnJTI 
"ITT 



in_rLn_n_rt 




onnnr 



I 



Yinnnnnnnnnnr 



"TfTr~irTrTnirorTruji^ 

nnnnn n 1 ■ " H „ 'lnnnr 

aroor-i. ~" FITT"! j j rTfTTHTTTr 

bfoii -mi y ~U If 

LALTIJT-l I 




339- 



SONY® 



CXD1159Q 



Application Circuit 
NTSC (Internal mode) 



PAL (Filter configuration 2, Internal mode) 




■m irr 

9101m 

[14.31818MH1I 




908 IM 
IH.I87SMHII 



PAL (Filter configuration 1, Internal mode) 




VT TIT 
908 tK 
I14.I875MHII 



340 



SONY. 



CXD1217M 



Synchronizing Signal Generator for Video Camera 



Description 

The CXD1217M is a synchronizing 
generator for color video cameras. 



signal 



Features 

• Compatible with the respective systems, 
NTSC, PALM, PAL and SECAM 

• Output is synchronized with the clock of 
910fH or 908fH 

• 25Hz offset processing by PAL system 

• Color framing by the respective systems, 
NTSC, PALM and PAL 

• Possible external synchronization by H reset, 
V reset and line-switchover reset pins 




Applications 

Synchronizing signal generator for color video 
cameras. 

Structure 

Silicon gate CMOS IC 

Absolute Maximum Ratings (Ta = 25°C) 



• Supply voltage Vdd 

• Input voltage Vi 

• Output voltage Vo 

• Operating temperature Topr 

• Storage temperature Tstg 



Vss-0.5 to +7.0 V 

Vss-0.5 to Vdd + 0.5 V 

Vss-0.5 to Vdd + 0.5 V 

-20 to +75 °C 

- 55 to + 1 50 t 



Recommended Operating Conditions 

• Supply voltage Vdd 4.5 to 5.5 V 

• Operating temperature Topr — 20 to + 75 °C 



E89626 - ST 



341 



SONY® 



Block Diagram and Pin Configuration 



*-(24) HCOMOUT 




♦{3 OBF/COLB 



Note : Pin 19 output is (a) a signal based on Pin 26 in INT mode at NTSC. 
(b) each signal is based on Pin 10 in other modes. 



-342 



SONY® 



CXD1217M 



Pin Description 



Pin No. 


Symbol 


I/O 


Description 


1 


VRI 


I 


Vertical reset signal 


2 


OFLD1 





First field output 


3 


OBF/COLB 





Burst flag/color blanking output 


4 


OSYNC 





Composite sync output 


5 


OFLD 





Even and Odd output 


6 


OBLK 





Composite blanking output 


7 


OLALT 





Line alternate output 


8 


OHD 





Horizontal drive output 


9 


4fscOUT 





4fsc output 


10 


4fsclN 


I 


4fsc input 


11 


NC 


— 




12 


OVD 





Vertical drive output 


13 


NC 


— 




14 


Vss 


— 


GND pin 


15 


LALTRI 


I 


Line alternate reset input 


16 


TEST 


I 


Test input 


17 


02FH 





2fH output (Double the frequency of Pin 27) 


18 


NC 


— 




19 


OSC 





Sub carrier output 


20 


EXT 


I 


Internal and external synchronizing modes switchover 
L : Internal synchronization H : External synchronization 


21 


MODE1 


I 


System selecting input 1 


22 


MODE2 


I 


System selecting input 2 


23 


HRI 


I 


Horizontal reset input 


24 


HCOMOUT 





Phase comparator output 


25 


CLOUT 





Clock output 


26 


CLIN 


1 


Clock input 


27 


OFH 





Horizontal frequency output 


28 


Vdd 


— 


Power supply pin 



343 



SONY® 



CXD1217M 



Electrical Characteristics 



DC characteristics 




(Vdd = 5V ± 1 %, Vss = OV, Topr = 


-20 to 


f 75^) 


Item 


Symbol 


Conditions 


Min. 


Typ. 


Max. 


Unit 


Output voltage 1 


Voh 


Ioh = - 2mA 


Vdd - 0.5 




Vdd 


V 


Vol 


Iol = 4mA 


Vss 




0.4 


V 


Output voltage 2* 1 


Voh 


Ioh = - 4mA 


Vdd - 0.5 




Vdd 


V 


Vol 


Iol = 4mA 


Vss 




0.4 


V 


Output voltage 3* 2 


Voh 


Ioh = — 4mA 


Vdd/2 






V 


Vol 


Iol = 8mA 






Vdd/2 


V 


Input voltage 


VlH 




0.7VDD 






V 


VlL 








0.3VDD 


V 


Input current* 3 
(Pull-down pin) 


llH 


Vih = Vdd 


20 


50 


120 


MA 


Output leak current* 1 


Ilz 


At high impedance 




±30 




nA 


Power current supply 


Idd 


At output pin in 
no-load 




8 




mA 


Feedback resistance* 4 


Rfb 


Vdd = 5V 


250k 




2.5M 


O 



*1 HCOMOUT pin 

*2 4fscOUT and CLOUT pins 

*3 LALTRI, TEST, EXT, MODE1 and MODE2 pins 

*4 4fscOUT, 4fsclN, CLOUT and CL IN pins 



I/O capacitance 



(Vdd = Vi = OV, f M = 1 MHz) 



Item 


Symbol 


Conditions 


Min. 


Typ. 


Max. 


Unit 


Input pin 


ClN 










9 


PF 


Output pin 


COUT 










11 


PF 



344- 



SONY® 



CXD1217M 



Description of Operation (See Block Diagram.) 

The CXD1217 is applicable to 4 systems; namely, NTSC, PAL, PALM and SECAM. In order 
to realize them, the following relative equations of Sub-carrier (4fsclN) and Clock (CLIN) are 
adopted. 





Sub carrier 


Clock 


NTSC 


4fsc = 910fH 


910fH 


PAL 


4fsc= 1135fH + 2fv 


908fH 


PALM 


4f sc = 909f H 


910fH 


SECAM 




908fH 





As it is obvious from the above equations, the 4fsc and clock frequency do not coincide with 
each other in the PAL and PALM. Therefore matching of the clock frequency is carried out by 
providing PLL. 



1. MODE specified input 

The CXD1217 provides 4 inputs to specify the respective modes. 

* EXT input : Set this pin to Vdd side, and it becomes into external synchronizing mode. At this 

time, the counters in connection with the PLL loop as shown in the upper part 
of the block diagram become into stand still state. 

* MODE1 and MODE2 inputs : These are inputs for the system selection. 



M0DE1 


M0DE2 


System 








NTSC 





1 


SECAM 


1 





PALM 


1 


1 


PAL 



"0" — Vss 
"1" -*Vdd 

* TEST input : An input to be used to measure IC. This input is normally kept opened. 
(Because it is dropped internally to Vss with MOS resistance.) 

2. Reset operation 

The CXD1217 has three reset inputs; namely, HRI, VRI, LALTRI, and it works to perform reset 
operation when it detects falling edge. These three inputs are so designed as to take in 
synchronization with the IC internal clock. Therefore, it is a prerequisite that both systems should 
have clock frequencies that are matched as a reset operation to each other (GEN locked). 



I 



* H reset (HRI input) 

When the HRI input is continuous with H synchronization, resetting is activated with the initial 
falling edge, and for the subsequent edges they do not have to be reset unless they are deviated 
more than 2-bit (140ns) against the initial edge in the internal clock. That is, if the jitter of 
HRI input is less than 140ns, it is absorbed. The minimum resetting pulse width is over 0.3 us. 

The phase to be reset is the advanced point of 6.3 to 6.37 ms (=90 to 91-bit X 70ns) than 
the HRI input as shown in the diagram below. 



\ 



HRI input 

CXD1217 |_jj 

HD OUT output 



A. Reset 



6.3-6.37 (us) 



-345- 



SONY® 



CXD1217M 



V reset (VRI input) 

When the VRI is input as shown in figure below, OSYNC can be reset at the same phase 

with the SYNC signal. 

Counter State^i 2 3 4 5 6 7 8 (?) 10 11 12 13 14 15 

sync signTin — IT~II — U LJLJLJL-Jl-JLJIJ U U IT 

^~ Falling edge permitted span 

: fc^- 



VRI 



CXD1217 internal clock (2th) 
(See Timing Chart Diagram) 

V reset pulse 
After reset SYNC OUT U 




t t 



u u ifflniiJi^JL^Jir^ir7ir~ 



A 

Reset State 

Since the falling edge point in the diagram above (marked with t) is the boundary of reset, 

if the falling edge of the VRI input traverses that point, it causes 1/2H deviation to the reset 

state. 

Accordingly, if resetting is applied between two similar systems whose frequency are different, 

the V to which resetting is applied generates jitter of 1/2H. (When the resetting is applied 

continuously.) 

• LALT reset (LALTRI input) 
Phase relation between LALTRI pulse polarity and 2FH is the same as in the case of V 
resetting. 

Resetting operation is basically required only in the external synchronizing mode (GEN LOCK 

mode). However, even in the internal synchronizing mode, it sometimes requires H and V 

outputs whose phases are deviated against a certain output. In that case, it suffices to use 

two CXD1217s and conduct the operation as follows: 

Clock 



CXD1217 
0HD1 OVD1 



Input 



Shift Reg. 



Output 



Clock 



Delay 



VRI2 

CXD1217 

VRI2 

OHD2 OVD2 



* It suffices to set IC-1 and IC-2 into INT mode. 



By varying the Delay and Shift Reg. of the above diagram, any phases of OHD2 and OVD2 
can be provided against the respective OHD1 OVD1. 

. Color framing 

In the case of internal synchronization in the individual NTSC, PAL and PALM systems, the 
phase relationships between SYNC of the 1st field and sub-carrier are kept stable regardless 
of the power supply being ON or OFF. However, as the PAL and PALM systems are 
comprised of PLL, the absolute values concerning the phase according to variation of the 
ambient temperature drifts. 



-346 



SONY® 



CXD1217M 



Timing Chart 

Output Timing Chart Diagram 



CXD1217 NTSC, PALM 



SYNC OUT 



f rnr~irirnnjTYinriJUU^^ — ir~ir~ir~ir~ir~ir~ Field 1 0DD 

nrnrnrnriiTTirririJUU^^ 2 EVEN 
j— inj — iHrrwTnruuLiLA^^ 

~ir-ir~ir~iiTinnrTTiJiJiJJL^ irir~ir~Lnr~ir~ir 



BF/COLB OUT 
(PALM) 



LALT OUT 
(PALM) 



BF/COLB OUtI ~U U II tl~ | 



(NTSC) 



HD OUT 



BLK OUT 



VD OUT 



FLD OUT 



FLD1 OUT (fv/4) 
(NTSC) 



FLD1 OUT (fv/8) 
(PALM) 




I 



Field 1 



CLIN 4f sc IN 

(ntsc) (palm) riJHJHJHjnj - iJ - LrLn 

SC OUT 



1 



_r 



-347- 



SONY® 



CXD1217M 



CXD1217 PAL, SECAM 



SYNC OUT 



Field 4 EVEN 



r rirnrirTYrriruuiJjjr^^ 

nririr~irnnnnruuLiu^^ 1 0DD 

j-ir~ir^Hrrtrrruuui^^ 2 EVEN 

. nrnrirnriiTTinriJiJUiJ^^ 3 odd 



BF/COLB OUT . 
(PAL) 



LALT OUT 
(PAL) 



"~ inrj- 
T~irr- 



~u — ^r 



i s~u~\r\rt 



BF/COLB OUT 

(secam) [ 1J - LHLTUii 



HD OUT 



BLK OUT 



OVD 



FLD OUT 



FLD1 OUT (fv/8) 
(PAL) 

FLD1 OUT (fv/4) 
(SECAM) 



10H 



~!T~\i II U U IT" Field 4 

jr~ir~ inr~ir~ir-ir 1 

2 
3 



~ir~ir~ ir~ir~ir~u— ir~ 
irinrir~\r~ ir~ir~ir 




,ir*y ~ij~l n : 1 1 1 i even 
IHrnr i m p . nnr odd 



EVEN 
ODD 




348- 



SONY® 



CXD1217 fH 






o 




* 


z 




J 


>- 




CO 


OT 


&. 


x 


X 


CQ 





o 








2 




c 


<y 


>- 
w 


OS 


X 2 


w 


> 


X 


CM ^ 



Q J 
J < 



349 



SONY® 



CXD1217M 



Application Circuit 

Basic connection in individual systems 

Basic connection in individual systems at internal synchronization mode (EXT input = "0") is 
as follows. See waveform diagram for each output. 

• NTSC 



14.318MHx(=910fH) 




•4— <P^ 



VDO VSS 



Synthesizer 























z 


* 




-, 










>- 


_l 




< 




d 








CD 




_l 


ll. 


o 


o 


o 


o 




o 


o 


o 




* H/2 is output for LALT OUT even in NTSC mode. 

* MODEL MODE2, EXT, TEST and LALTRI pins can be kept open. 
(If noise annoys, connect to Vss by low impedance.) 



PAL 



]4.187MH i(908fH) 




* Inverter of CLin or CLout pins are usable as VCO. 



350 



SONY® 



CXD1217M 



PALM 



14318MHz OlOfHl 



OSC 

(4- 



^r 




d^ 



i-jiyx 



I4 302MH: 
<4f je) 



/c 



S.C. 
Reset 



'/, 



r— L*»F. — ► vco 



Phase 
Comparison 




* Internal inverter is usable as VCO. 

• SECAM 



14.187MHz 1:908 fH) 




— ®— <*> 



VSS VOO 



Synthesizer 




■10K 
MODE 2 



"~1 HRI 



I 























I 










■I 



























































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o 


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3W4 


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777 



©k£>-®-<5^ 



* COLB is output to BF/COLB OUT pin. 

* Sdr and Sob are formed in PLL using 908fH. 



-351 - 



SONY® 



CXD1217M 



Package Outline Unit : mm 



28 pin SOP (Plastic) 375mil 0.6g 



+ 0.4 

ia8-o.i 



15 



| 8 H33HR3SRHRRRR 



O 



yyyyyyyyyyyyil 



0.4 5 



±0.1 



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. 



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5OP-28P-L02 



-352 



SONY. 



CX23047B 



CCD Camera Scanning System Timing Signal Generator 



Description 

CX23047B has been developed as a CMOS type LSI to 
be used for the scanning system for both imagers of 
ICX018CK/CL(NTSq, and ICX021 CK/CL(CCIR), and displays 
the following functions by using together with CX-7930A 
(synchronized signal generator). 

Features 

. Generates imagers (ICX018CK/CL and ICX021CK/CL) 
drive pulses. 

• Generates signal processing pulses for color and B & W 
cameras. 

• Switchover of NTSC/CCIR modes is possible. 

• Correction of defect of 1 picture element of every 1 H of 
imager is possible, (external ROM is appended) 

Structure 

Silicon gate CMOS 

Absolute Maximum Ratings (Ta=25°C, Vss=OV) 

• Supply voltage Vdd Vss— 0.5 to 7.0 V 

• Input voltage Vi Vss— 0.5 to Vdd+0.5 V 

• Output voltage Vo Vss— 0.5 to Vdd+0.5 V 

• Operating temperature Topr —20 to +75 °C 

• Storage temperature Tstg —55 to +150 °C 

• Allowable power Pd 500 mW 
dissipation 



Package Outline 



Unit: mm 



48pinQIP 
17.6 MAX 



<¥ 



2 4 MAX 005 MIN 



JL 8 J 0.3 t 0.06 J[gi7 ± 0.I 



QIP-48P-L021 



Recommended Operating Conditions 

• Supply voltage Vdd 4.5 to 5.5 

• Operating temperature Topr —20 to +75 

Block Diagram 

(30) CPf> « |l/2k 




£>CL(36) 



{>XPG(12> 

->SPI-2(1 )H8) 
XDLI.2 (451(441 
SH1-2(47)(46> 



XVI<2'3'4!9)IS)<8><4 
XSGI'2(II)(10) 
XVCT VAAI28K27] 



A0-6(17)(16l(15«ie)(20)121)(22) 



■ 



353 



SONY® 




-354 



SONY® 



CX23047B 



Pin Configuration (Top View) 



1 SP1 



I 1 SHD 



| 3 SHP 



f4 XV4 



f 5 XV2 



1 6 Vss 



LL 



I 8 XV3 



I 9 XV1 



I 10 XSG2 



111 XSG1 



I 12 XPG 



O 



CX23047B 



CL 


36 1 




HD 


35 




FLD 


34 




CK 


33 




XCK 


32 




Vss 


31 




CP 


30 




TEST 


29 




XVC1 


28 




D1 


27 




D2 


26 




D3 


25 | 



Pin Number and Name 



No. 


I/O 


Symbol 


No. 


I/O 


Symbol 


No. 


I/O 


Symbol 


No. 


I/O 


Symbol 


1 





SP1 


13 





XH2 


25 


I 


D3 


37 





VAA 


2 





SHD 


14 





XH1 


26 


I 


D2 


38 





HBLK 


3 





SHP 


15 





A2 


27 


1 


D1 


39 





ID 


4 





XV4 


16 





A1 


28 





XVCT 


40 





CLP3 


5 





XV2 


17 





A0 


29 


1 


TEST 


41 





CLP2 


6 


p* 


Vss 


18 





A3 


30 


1 


CP 


42 





CLP1 


7 


I 


HTSG 


19 


p* 


Vdd 


31 


p* 


Vss 


43 


p* 


Vdd 


8 





XV3 


20 





A4 


32 





XCK 


44 





XDL2 


9 





XV1 


21 





A5 


33 


1 


CK 


45 





XDL1 


10 





XSG2 


22 





A6 


34 


1 


FLD 


46 





SH2 


11 





XSG1 


23 


I 


CM 


35 


1 


HD 


47 





SH1 


12 





XPG 


24 


I 


D4 


36 





CL 


48 





SP2 



■ 



P: power source 



-355- 



SONY® 



CX23047B 



Pin Description 



No. 


Symbol 


I/O 


Description 


4, 5, 8. 9 


XV1 to XV4 





Imager driving pulse. 

Add inverse shape driver and drive CCD imagers (ICX-018 and ICX-021). 


10, 11 


XSG1, 2 





12 


XPG 





13. 14 


XH1, 2 





15 to 18 
20 to 22 


A0 to A6 





Address output for external ROM. 
A6 is MSB. 


23 


CM 


1 


Test pin. Normally GND. 


24 to 27 


D4 to D1 


1 


External ROM input pin. When external ROM is not used, mode setting is 
possible by pulling up or pulling down. 
When ROM is not used: 

D1 . . . always GND 

D2 . . . GND: monochrome mode, Vcc: color mode 

D3 . . . always Vcc 

D4 . . . GND: CCIR, Vcc: NTSC 


28 


XVCT 





ROM (MB7052) power supply switching pulse. 

When performing switching, it is necessacy to add PNP transistor. 


29 


TEST 


1 


Test pin. Normally GND. 


30 


CP 


1 


Clock input. NTSC: 28.6364 MHz, 
CCIR: 28.3750 MHz 


32 


XCK 





Inverter circuit 


33 


CK 


1 




34, 35 


FLD, HD 


1 


Synchronizing signal input. It is taken in by trailing of CL (Pin 36). 


36 


CL 





Clock output for SYNC generator (CX-7930A). 
Half the frequency of CP 


37 


VAA 





Vertical effective sphere of CCD imager output. Used together with CLP1 in 
the clamping circuit. 


38 


HBLK 





Horizontal effective sphere of CCD imager output. Used for pre-blanking. 


39 


ID 





R/B lines discriminating signal. 
B line . . . "H", R line . . . "L" 


40, 41 


CLP2, 3 





Clamping pulse. Continuous pulse. 


42 


CLP1 





Clamping pulse. CCD output optical black section clamping pulse. 


44, 45 


XDL1, 2 





1H delay line (CX23039) driving pulse. 


46, 47 


SH1, 2 





Sample hold pulse for 1 H delay line (CX23039). 


48, 1 


SP1, 2 





Sample hold pulse for color separation. 
Possesses defect correction function. 


2 


SHD 





Sample hold pulse for imager output. 
Possesses defect correction function. 


3 


SHP 





Pulse to sample hold the pre-charge level of imager output. 


7 


HTSG 


1 


Test pin. Normally GND. 


6, 31 


Vss 


1 


Ground pin. 


19, 43 


Vdd 


1 


+5V power source pin. 



-356 



SONY® 



CX23047B 



Electrical Characteristics 



DC characteristics 



Vdd =5V ± 10% Vss = OV, 
Topr = -20 to +75°C 



Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Power supply current 


Idds 


Static state* 







0.02 


mA 


Output , 
voltage 


H level 


Voh 


Ioh = —0.4 mA 


Vdd 
-0.5 




Vdd 


V 


L level 


Vol 


Iol = 3.2 mA 


Vss 




0.4 


V 


Input 
voltage 


H level 


Vih 




2.2 






V 


L level 


VlL 








0.8 


V 


Input leakage current 


Ili 




-5 




5 


JLlA 



'Note) Vih = Vdd, Vil = Vss 



I/O Capacity 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Input pin 


ClN 






12 


PF 


Output pin 


Cout 






12 


PF 



Test condition: Vdd = Vi = OV, fM = 1 MHz 



357- 



SONY® 



1 










— 2 










_ 








— 








1 




— 1 

— 525- 




— 


— 


— 








— 



















_ 


_ 


CN 

— or - 






J — 


















— 


— 


— 


t _ 


— 




— 










_ 








— 


— 


— 




— 




— 


















— 


— 


— 


— — 


— 




— 


















— 


— 


— 


— — 


— 




— 














— 520 




— 


— 


— 


— — 


— 




— 


















— 


— 


— 


— — 


— 




— 












— 






— 


— 


— 


— — 


— 




— 


















— 


— 


— 


«— — 


— 




— 














— 285 




— 


— 


— 




— 




— 


















— 


— 


— 




— 




— 




— ' — 














— 


— 


— 




— 




— 




— 1— 














— 


— 


— 




— 




— 




— '— 














— 


— 


— 


T _ 


— 




— 




— 1 — 












— 280 




— 


— 


— 







— 




— 














— 


— 


— 


— ^ _ 


— 




— 




— 1— 














— 


— 


— 




— 




— 




— r— 














— 


— 


— 




— 




— 




— ' — 










— 275 




— 


— 


— 


— - 


— 




— 




— r— 














— 


_ 


— 








"I — 












— 





— 





— 


— 


L. 












1— 










— 270 




= c 


c 


3 


3 






= 






a> 
u 

c 

J > 

-o 








— 






— 


— 








— 






1 m 








— 265 




z 


— 


_ 








— 






1 I 








^ 






— 


— 








— 






TJ 








— 






— 


— 








— 






1 ° 










— 260 




— 5r 

■» _ 


1 e 

-, _i 
J o 














— 


— 


— 


























— 


— 


— 


























— 


— 


— 




















— 






— 


— 


— 




















— 






— 


— 


— 










— ■— 








— 






— 


— 


— 


— 


— 





























_ 


_ 


_ 
















— 


— 20 




— 


— 


— 


— 


— 
















— 






— 


— 


— 


— - 


— 
















= 








^ 


^ 


^ 


O 




















— 15 




— 


— 


— 


— "~ - 




















= 




^ 


2 


= 


= : 


O — 
IS 

.o 








- £ 










— 10 






— 


— 


— 


I 








— i- 










- 


= 




^ 


^ 


^~ 


o 








^"^ 










— 






— 


— 


— 






— 




— r- 










— 5 






— 





— 






__ 




_ 










— 3 






— 


— 


— 






— 




— •— 










— 2 






— 


— 


— 






^ 




— r- 










— 1 

— 525- 






— 


— 


— 






— 




— 














_ 





CN 

— or 






J ~ 




_ c 










— 






— 


— 


TT . 


- — 








— r- 










— 






— 


— 


— 










— '- 


~\ > 






— 


— 






•_< 


^ 


— 










— r- 


c 






— 


— 520 






— 


— 


— 










— *- 


-l o 






— 


— 






— 


— 


— 










— r- 


J V 






— 


— 






— 


— 


— 










— *- 


1 o 












— 






— 


— 


— 










— r 


J E 



I 



X X X X 



o o 



358 



SONY® 



163 
60 



55 



10 

<5 
13 

|1 2 

;8 

15 
•3_ 



h 4' 



>30 



i20 



1 
'510 



OS 

U CQ 



< 

< 
Q 

5 

y_ O 

o £ - - 



CM 



0-0- 3. 



w w x x x x 



359 



SONY® 



CX23047B 



L 



■2 
■1 
■625 



CCPJ 



— I— I X 



— 25 



— 20 



8- 



— 5 



3 

2 
• 1 
■625 





















CM 


<•> 








> 


> 


> 


> 


X 


X 


X 


X 


X 


X 



-360 



SONY® 



CX23047B 



63 



35 
30 



20 



LL. ~ " 

LL, 

O 

o 



20 



10 



5 
3 

: 2 
1 

500 C 



3 495 



I 



U m 



»- CM 
> > 
X X 



1-O.o.B ^rg 3 ■£ 

" E ^ CN J J N - 

> Q. Q. Q Q I I 

X <n co x x co co 



Q. Q. Q. 
■ ■ I 

o o o 



m m m oo 

2: 9 *- cm 



n i/i in i/i 



-361 - 



SONY® 



CX23047B 



5. (C-L-ROM OFF) 




XPG l_f 



_r 



SHP 



SHD ~~|_ 



SP1 ~1_ 



SP2 



XDL2 

SH1 
SH2 



u 



u 



IS 



362 



SONY® 



CX23047B 



6. (B/W.ROM OFF) 



XH1 ~|_ 



XH2 J 
XPG -1 r 
SHP 



n 



SHD 



SP1 



i r 



u 



n 



j — L 



u 



n 



r 



u 



n 



i i 



■ 



363- 



SONY. 



CXD1035BQ-Z 



CCD Camera Scanning System Timing Signal Generator 



Description 

CXD1035BQ-Z is a CMOS type LSI developed 
for use with the scanning system of both ICX022AK 
(NTSC) and ICX024AK (PAL). 

This IC is employed in conjunction with either 
CXD1030M or CXD1158M (synchronized signal 
generator). 

Features 

• Generates drive pulses for imagers (ICX022AK, 
ICX024AK). 

• Generates signal processing pulse for color 
cameras. 

• Switchover of NTSC/PAL modes is possible. 

• Blemish compensation is possible (through usage 
of external ROM). 




Structure 

Silicon gate CMOS IC 



Absolute Maximum Ratings (Ta=25°C, Vss=0V) 

• Supply voltage Vdd Vss-0.5 

• Input voltage Vi Vss-0.5 

• Output voltage Vo Vss-0.5 

• Operating temperature Topr -25 

• Storage temperature Tstg -40 

• Allowable power dissipation Pd 



to 
to 
to 
to 
to 
500 



6.0 

Vdd+0.5 

V 
+85 
+125 



V 

V 

V 

°C 

°C 

mW 



Recommended Operating Conditions 

• Supply voltage Vdd 4.75 to 5.25 V 

• Operating temperature Topr -20 to +75 °C 



E89Z23-YA 



-364- 



SONY® 



CXD1035BQ-Z 



<<<«<<< 



0. 0. 0. I 



A 




* •" *H 



TTT 



X 



>>>>QO__ 
xxxx>>>> 



Tt 



i ui 



I 



TT 



y 



■ 



-@-©— ©- 



-®- 



-© — ®- 



-365 



SONY® 



CXD1035BQ-Z 



Pin Configuration (Top View) 



— CM K> 



HTSG 


(37) 








CLSG 


(38) 








CLP 2 


(39) 








CLP 1 


® 








CLP 3 


© 








PBLK 


© 








Vdd 


® 








N.C. 


© 








N.C 


© 








SH 3 


6v 








SH 2 @ 








SH 1 


® 


O 

■CT) 


(z) 


-(? 






ro 

a. 


CM 

a. 


a. 



en o CM 



O) C/l <J1 </) cr> 







(24) 


A6 






(3) 


A5 






@ 


A4 






(2l) 


A3 






® 


AO 






© 


VDD 






(18) 


A1 






\l) 


A2 






® 


XVI 






© 


XV 2 






@ 


XV 3 






© 


XV 4 


®K5) 


"^)" 






Q_ o 
C/5 


CM 
<£> 
CO 







Pin Name 



No. 


I/O 


Symbol 


No. 


I/O 


Symbol 


No. 


I/O 


Symbol 


No. 


I/O 


Symbol 


1 





SP3 


13 





XV4 


25 


I 


DAT4 


37 


I 


HTSG 


2 





SP2 


14 





XV3 


26 


I 


DAT3 


38 


I 


CLSG 


3 





SP1 


15 





XV2 


27 


I 


DAT2 


39 





CLP2 


4 





SHD 


16 





XV1 


28 


I 


DAT1 


40 





CLP1 


5 





SHP 


17 





A2 


29 





XVCT 


41 





CLP3 


6 


- 


Vss 


18 





A1 


30 


I 


TEST 


42 





PBLK 


7 





XPG 


19 


- 


Vdd 


31 


- 


Vss 


43 


- 


Vdd 


8 


o 


XH2 


20 





AO 


32 


I 


CK 


44 


- 


N.C. 


9 





XH1 


21 





A3 


33 





XCK 


45 


- 


N.C. 


10 





PS 


22 





A4 


34 


I 


VD 


46 





SH3 


11 





XSG1 


23 





A5 


35 


I 


HD 


47 





SH2 


12 





XSG2 


24 





A6 


36 


O 


CL 


48 


o 


SH1 



-366- 



SONY® 



CXD1035BQ-Z 



Pin Description 



Symbol 


I/O 


Description 


XV1 to XV4 





Drive pulses for the imagers (ICX022, ICX024) through CCD drivers. 


XSG1.2 





XPG 





XH1,2 





AO to A6 





Address output for external ROM. A6 is MSB. 


D4 to D1 


I 


External ROM data input pin. 


XVCT 





ROM (MB7144) power supply switching pulse. 


TEST 


I 


Test pin. Normally GND. 


CK 


I 


Clock input. NTSC : 28.6364 MHz 
PAL : 28.3750 MHz 


XCK 





CK inversion output « ^o xck 


VD.HD 


I 


Synchronizing signal input. 

Latched by falling edge of CL (Pin 36). 


CL 





Clock output for synchronized signal generator. 
Half CK's frequency. 


PBLK 





Horizontal and vertical effective area of CCD imager output. 
Used for pre-blanking. 


PS 





Power save for V driver IC. 


CLP1,2,3 





Clamping pulse. 


SH1.2, 3 





Sampling pulse for signal processor. 


SP1.2, 3 


O 


Sampling pulse for color separation. 


SHD 





Sampling pulse for imager output signal. 


SHP 





Sampling pulse for pre-charge level. 


HTSG, CLSG 


I 


Test pin. Normally GND. 


Vss 


I 


Ground pin. 


Vdd 


I 


+5V power supply pin. 



■ 



-367 



SONY® 



CXD1035BQ-Z 



Electrical Characteristics 
DC characteristics 



Vdd=5V±5%, Vss=0V, Topr=20 to +75°C 



Item 


Symbol 


Conditions 


Min. 


Typ. 


Max. 


Unit 


Supply current 


Idds 


Static state* 







0.1 


mA 


Input voltage 


H level 


Voh 


Ioh = -0.4 mA 


4.2 




Vdd 


V 


L level 


Vol 


Iol = 3.2 mA 


Vss 




0.4 


V 


Output voltage 


H level 


Vih 




2.4 






V 


L level 


VlL 








0.8 


V 


Input leakage current 


Ili 


Vi = 0V to Vdd 


-10 




+10 


jiA 



*Note) Vih = Vdd, Vil = Vss 



I/O characteristics 



Item 



Input pin 



Output pin 



Symbol 



ClN 



COUT 



Min. 



Typ. 



Max. 



Unit 



PF 



PF 



Test condition: Vdd=Vi=0V, fM=1MHz 



-368- 



SONY® 



CXD1035BQ-Z 



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-369 



SONY® 



CXD1035BQ-Z 



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Frame Integration 



Field Integration 



-370 



SONY® 



CXD1035BQ-Z 



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-371 



SONY® 



CXD1035BQ-Z 



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Frame Integration 



Field Integration 



372- 



SONY® 



CXD1035BQ-Z 




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-373 



SONY® 



CXD1035BQ-Z 



Readout Period 

Field Integration mode 



XSG 1 


XSG2 


ODD field 


XV t 


XV 2 


XV 3 


XV 4 


EVEN field 


XV 1 


XV 2 


XV 3 


XV 4 



J L 



Frame Integration mode 



H-BLK 

XSG 1 
XSG 2 

ODD field 
XV 1 
XV 2 
XV 3 
XV 4 

EVEN field 



XV 1 
XV 2 
XV3 
XV 4 



FhH 



Note) Number: Clock (1 clock = 70ns) 



Fm. 



N'NTSC 
P'PAL 



-374- 



SONY® 



CXD1035BQ-Z 



H clock • Signal Processing Pulse Phase 



XH,| | | 


J L_ 


J L 


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J L_ 


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n n n 


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n n n n 


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SP2 


n 


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__r^ 


n 




n 


SP3 




n ' 




SH1 | | 

SH2 

SH3 


n 


n 


_n_ 


n 


n 


n 



Package Outline Unit: mm 



48p i n QFP (Plastic) . 7g 
D15.3 ±w 




SONY NAME 


QFP-48P-L022 


EIAJ NAME 


•QFP048-P-1212-BF 


JEDEC CODE 







I 



-375 



SONY. 



CXD1141M 



Timing setting for Electronic Shutter (CCD imager) 



Description 

The CXD 1 1 41 M developed for CCD cameras 
is an LSI that sets the timing of electronic 
shutters. 

Features 

• Compatible with variable shutters (1/60 to 
1/10000 sec) 

• Compatible with flickerless 

• Compatible with NSTC/PAL 

• Mode setting compatible with serial/parallel 

Function 

Sets the timing of electronic shutters. 



Structure 

Silicon gate CMOS 

Absolute Maximum Ratings (Ta = 25°C) 

Vdd 

VlN 

Vo 

Topr 

Tstg 



Package Outline 



Unit: mm 



Supply voltage 
Input voltage 
Output voltage 
Operating temperature 
Storage temperature 
* Vss = OV 



16 pin SOP 



O 



OA 5 10 



d~ \D\ 0.1 5 ~| 

+ 0.2 
g.l-ft05 



3 



tunmru-unni) 



~I- H€H ± o.i 2 | 



Vss-0.5* to +7.0 V 

Vss-0.5* to Vdd + 0.5 V 

Vss-0.5* to Vdd + 0.5 V 

-20 to +75 °C 

-55 to +150 °C 



SOP-16P-L01 



Recommended Operating Conditions 

• Supply voltage Vdd 

• Operating temperature Topr 



4.5 to 5.5 (5.0V Typ.) V 
20 to +75 °C 



Block Diagram 



®to® 
D2 to DO 



m 



:> 



©EN 

®FL1 

®FL2 - 

®MOD1- 

®MOD2 - 

®XSG1 - 

®VD - 
©HD 

©PS 
©XV4 - 



Register ^> Serial 



0> 



parallel 
selector 



V 



Counter 



Gate 



►®XSUB 



70620-YA 



-376 



SONY® 



CXD1141M 



Pin Configuration and Description (Top View) 



16 



§JJJJJJ_I 




¥¥¥¥¥¥¥¥ 

8 



No. 


Symbol 


I/O 


Description 


1 


VD 




Vertical drive pulse 


2 


HD 




Horizontal drive pulse 


3 


XV4 




Vertical scanning clock 


4 


XSG1 




Sensor electric charge lead out pluse 


5 


PS 




Power save pulse 


6 


EN 




Enable signal L: Normal mode, H: Electronic shutter mode 


7 


M0D1 




Mode switching L: PAL, H: NTSC 


8 


Vss 


- 


GND 


9 


XSUB 





Electric charge sweep out pulse 


10 


MOD2 




Mode switching L: serial input H: Parallel input 


11 


FL1 




Mode switching L: flickerless H: Normal 


12 


FL2 




Mode switching L: 60Hz H: 50Hz 


13 


D2 




Shutter speed setting 


14 


D1 




Shutter speed setting 


15 


DO 




Shutter speed setting 


16 


Vdd 


- 


+ 5V 



I 



377 



SONY® 



CXD1141M 



Electrical Characteristics 



DC characteristics 






Vdd = 4.5 to 5.5V, Vss = OV, Topr= -20 to +75°C 


Item 


Symbol 


Conditions 


Min. 


Typ. 


Max. 


Unit 


Supply current 


Idd 








2 


mA 


Idds 


Static state* 1 







0.1 


mA 


Output voltage 


H level 


Voh 


Ioh= - 1.5mA 


Vdd -0.5 




Vdd 


V 


■ L level 


Vol 


Iol = 4.0mA 


Vss 




0.4 


V 


Input voltage 


H level 


VlH 




0.7VDD 






V 


L level 


VlL 








0.3VDD 


V 


Input threshold 
voltage 


H level 


VlH 




0.7VDD 


3.0 




V 


L level 


VlL 






2.0 


0.3VDD 


V 


Hysteresis 


Vh 




0.5 






V 


Input leak current 


Ili 


Vi = 0V* 2 


-20 


-50 


-120 


fiA 



Note)*1 Vdd is applied to all input pins. 

*2 Pull up resistance is provided to all input 



pins. 



AC characteristics 

For serial input mode 



D2 



D1 



X 



X 



tS2 



th2 



DO 



tsi 



two 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


D2 set up time with regards to D1 rising edge. 


tS2 


20 






ns 


D2 hold time with regards to D1 rising edge. 


th2 


20 






ns 


D1 rising edge set up time with regards to DO Falling 
edge. 


tS1 


20 






ns 


DO pulse width 


two 


20 






ns 



Input/Output Capacitance 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Input pin 


ClN 






8 


pF 


Output pin 


Cout 






8 


pF 



Testing conditions Vdd = Vi = 0V, fM = 1MHz 



-378- 



SONY® 



CXD1141M 



Mode setting 

1) Parallel input mode (MOD2 = H) 



EN 


MOD1 


MOD2 


FL1 


FL2 


D2 


D1 


DO 


Shutter speed 


Theoretical value 


H 


H 


H 


H 




L 


L 


L 


1/60 


1/60 


H 


H 


H 


H 




L 


L 


H 


1/125 


1/125 


H 


H 


H 


H 




L 


H 


L 


1/250 


1/252 


H 


H 


H 


H 




L 


H 


H 


1/500 


1/499 


H 


H 


H 


H 




H 


L 


L 


1/1000 


1/1013 


H 


H 


H 


H 




H 


L 


H 


1/2000 


1/2088 


H 


H 


H 


H 




H 


H 


L 


1/4000 


1/4450 


H 


H 


H 


H 




H 


H 


H 


1/10000 


1/10256 


H 


L 


H 


H 




L 


L 


L 


1/60 


1/60 


H 


L 


H 


H 




L 


L 


H 


1/125 


1/125 


H 


L 


H 


H 




L 


H 


L 


1/250 


1/250 


H 


L 


H 


H 




L 


H 


H 


1/500 


1/495 


H 


L 


H 


H 




H 


L 


L 


1/1000 


1/1005 


H 


L 


H 


H 




H 


L 


H 


1 /2000 


1/2070 


H 


L 


H 


H 




H 


H 


L 


1 /4000 


1/4403 


H 


L 


H 


H 




H 


H 


H 


1/10000 


1/10090 


H 


H 




L 


H 








1/100 


1/100 


H 


H 




L 


L 








1/120 


1/120 


H 


L 




L 


H 








1/100 


1/100 


H 


L 




L 


L 








1/120 


1/120 


L 
















NORMAL 





2) Serial input mode (M0D2 = L) 
D1 



D2 



DO 



n 



D2 data is latched at register with the rising edge of D1 and shifted 
inside with the DO. 



■ 



Application Circuit 



CXD1035B 

timing 
generator 


XSG1, 


XV4, PS 


XSUB 






















CXD1141M 








CCD 








Driver 


CXD1030 
Sync signal 
generation 




imager 
















HD, \ 


m 









379 



SONY 8 



CXD1156Q/R 



Timing Generator IC for ICX026/027 



Description 

CXD1 156Q/R is a timing generator IC for 
CCD imagers ICX026AK/AL and ICX027AK/AL 

Features 

• NTSC/CCIR 

• Field accumulation mode 

• Color/Black and White mode 

• 1/60 to 1/10,000 sec. variable speed, built- 
in electronic shutter. 

• Built-in horizontal driver. 

• Initialize operation at every field. 

Functions 

Timing generation for CCD imagers. 

Structure 

Silicon gate CMOS 

Application 

CCD camera system 

Absolute Maximum Ratings (Ta = 25°C, Vss = 0V) 

• Supply voltage Vdd 

• Input voltage Vi 

• Output voltage Vo 

• Operating temperature Topr 

• Storage temperature Tstg 



48pin QFP (Plastic) 




48pin VQFP (Plastic) 



Vss-0.5 to +7.0 


V 


Vss-0.5 to Vdd + 0.5 


V 


Vss-0.5 to Vdd + 0.5 


V 


-20 to +75 


°C 


- 55 to + 1 50 


°C 



E89X12-YA 



- 380 - 



SONY® 



CXD1156Q/R 



t^ iii^xxa,ii->>>>oo 



0.0. 




w 



A 



E 

n 



O 

o 
S 



A 



l-Kgwa> 



i 

° i 
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7T 



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A 



A 



1 
IS 

cJiS 



I 



Si 



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Q Q Q 



-381 - 



SONY® 



CXD1156Q/R 



Pin Configuration (Top View) 




Pin Description 



No. 


Symbol 


I/O 


Description 


1 


SP1 





Color separation pulse CL' in B/W mode) 


2 


SHD 





Data sample hold pulse 


3 


SHP 





Precharge level sample hold pulse 


4 


XV4 





Vertical scanning clock 


5 


XV2 





Vertical scanning clock 


6 


Vss 


- 


GND 


7 


TEST1 


I 


GND 


8 


XV3 





Vertical scanning clock 


9 


XV 1 





Vertical scanning clock 


10 


XSG2 





Sensor charge read out pulse 


11 


XSG1 





Sensor charge read out pulse 


12 


XPG 





Precharge gate pulse 


13 


FL1 


I 


Mode select L: Flicker less H: Normal, (pull up) 


14 


FL2 


I 


Mode select L: 60Hz H: 50Hz, (pull up) 


15 


Vss2 


- 


GND for driver 


16 


H2 





Horizontal scanning clock 


17 


H1 





Horizontal scanning clock 


18 


VDD2 


- 


+ 5V supply pin for driver 


19 


Vdd 


- 


+ 5V 


20 


MODE4 


I 


Mode select L: Serial input H: Parallel input, (pull up) 


21 


XSUB 





Discharge pulse 


22 


ENB 




Enable signal L: Normal H: Electronic shutter (pull up) 


23 


D2 




Shutter speed setting (schmitt input), (pull up) 


24 


D1 




Shutter speed setting (schmitt input), (pull up) 


25 


DO 




Shutter speed setting (schmitt input), (pull up) 


26 


MODE3 




Mode select L: NTSC H: PAL., (pull down) 


27 


TEST2 




GND 


28 


MODE1 




Mode select L: Color H:B/W, (pull down) 


29 


OSCI 




Ocsillation input oscillation frequency. NTSC: 28.6364 MHz CCIR: 28.3750 MHz 


30 


OSCO 





Oscillation output 


31 


VSS 


- 


GND 


32 


CK 


I 


Duty control inverter input 


33 


XCK 





Duty control inverter output 



382- 



SONY® 






CXD1156Q/R 




No. 


Symbol 


I/O 


Description 


34 


VD 


I 


Vertical drive pulse 


35 


HD 


I 


Horizontal drive pulse 


36 


CL 





4 fsc clock output (Sync generator clock input) 


37 


TESTO 


I 


GND 


38 


PBLK 





Blanking cleaning pulse 


39 


ID 





Line discrimination pulse 


40 


CLP3 





Clamp pulse 


41 


CLP2 





Clamp pulse 


42 


CLP1 





Clamp pulse 


43 


Vdd 


- 


+ 5V 


44 


XDL2 





Delay line pulse CL' in B/W mode) 


45 


XDL1 





Delay line pulse CL' in B/W mode) 


46 


TEST3 


I 


GND 


47 


TEST4 


I 


GND 


48 


SP2 





Color separation pulse CL' in B/W mode) 



Recommended Operating Conditions 
Electrical characteristics (DC characteristics) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply voltage 


Vdd 


4.75 


5.0 


5.25 


V 


I/O voltage 


Vi, Vo 


Vss 




VDD 


V 


Input voltage (Logical value) CMOS input cell 


VlH 


0.7 Vdd 






V 


VlL 






0.3VDD 


Schmitt trigger input voltage (DO, D1, D2) 


Vt+ 


0.8VDD 






V 


Vt- 






0.2VDD 


VT+-VT- 


0.7 


0.9 




Input rising, falling time 


tr,tf 







500 


ns 


Operating temperature 


Ta 


-20 




+ 75 


°C 


Output voltage 1 


IOH=-2mA 


V0H1 


»3 






V 


Iol = 4mA 


V0L1 






0.4 


V 


Output voltage 2 


Ioh = -4mA 


VOH2 


«3 






V 


Iol = 8mA 


VOL2 






0.4 


V 


»2 

Output voltage 3 


Ioh = -8mA 


VOH3 


• 3 






V 


Iol= 8mA 


VOL3 






0.4 


V 



I 



*1. Pin 12 (XPG). 

'2. Pins 16 and 17 (H1,H2) 

*3. Vdd-0.5 



-383 



SONY® 



CXD1156Q/R 



Oscillation I/O Electrical Characteristics (OSCI, OSCO, CK, XCK) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Logical threshold value 


Vth 




VDD/2 




V 


Input voltage 




VlH 


0.7 Vdd 






V 




VlL 






0.3VDD 


V 


Feedback resistor 


Vin = Vss or Vdd 


Rfb 


500k 


2M 


5M 


G 


Output voltage 


Ioh = -1mA 


VOH 


Vdd/2 






V 


Iol= 1mA 


Vol 






Vdd/2 


V 



AC Characteristics 
Serial input mode 



D2 



D1 



I 



tS2 



I 



th2 



tS1 



TSO 



DO 



] TWO | 



u 



Symbol 


Item 


MIN. 


MAX. 


ts2 


D2 set up time vs. D1 rising edge 


20nS 


— 


th2 


D2 hold time vs. D1 rising edge 


20nS 


— 


ts1 


D1 rising edge set up time vs. DO falling edge 


20nS 


— 


twO 


DO pulse width 


20nS 


50uS 


tsO 


DO falling edge set up time vs. D1 rising edge 


20nS 


— 



384- 



SONY® 



CXD1156Q/R 



Mode Setting 

1. Parallel input (mode 4 = 'H') 











Table- 1 








ENB 


MODE 
3 


MODE 
4 


FL1 


FL2 


D2 


D1 


DO 


Shutter 
speed 


H 




H 


H 




L 


L 


L 


1/60 


H 




H 


H 




L 


L 


H 


1/125 


H 




H 


H 




L 


H 


L 


1/250 


H 




H 


H 




L 


H 


H 


1/500 


H 




H 


H 




H 


L 


L 


1/1000 


H 




H 


H 




H 


L 


H 


1/2000 


H 




H 


H 




H 


H 


L 


1/4000 


H 




H 


H 




H 


H 


H 


1/10000 


H 


H 


H 


H 




L 


L 


L 


1/60 


H 


H 


H 


H 




L 


L 


H 


1/125 


H 


H 


H 


H 




L 


H 


L 


1/250 


H 


H 


H 


H 




L 


H 


H 


1/500 


H 


H 


H 


H 




H 


L 


L 


1/1000 


H 


H 


H 


H 




H 


L 


H 


1/2000 


H 


H 


H 


H 




H 


H 


L 


1/4000 


H 


H 


H 


H 




H 


H 


H 


1/10000 


H 


L 




L 


H 








1/100 


H 


L 




L 


L 








1/120 


H 


H 




L 


H 








1/100 


H 


H 




L 


L 








1/120 


L 
















NORMAL 



2. Serial input mode (mode 4 = '!_') 



D1 
D2 
D3 



I^EEiMEBJOi 



D2 data is latched by the register with the rising edge of D1, and taken inside with the 
falling edge of DO. 



-385- 



SONY® 



CXD1156Q/R 



Application Circuit (NTSC mode, color mode) 



PROCESS 
CIRCUIT 




CCD IMAGER 
DRIVER 



CXD1251Q 

Timing Chart 1 . [High speed timing] 

NTSC 



xck UUUjrLiftjiririjT^^ 



XPG U 

shp _TL 



SHD 

spi _n 

SP2 



-rU 



XDL1 
XDL2 



n 



TV — U U LT 

L_n n n n 



ji n n n n 



a 



XL 



_n 



-I— TL 



J~L 



TT~U U LTTU U — U 

n n rLji n 



_n n n n n_ 



TL 



J~L 



_TL 



TL 



TL- 

r 



CCIR 

hi n_ri/- 

xck injiMJuinnjmiuinnnnju^^ 
xpg ~ u — d - 



i\ n 



SHP 

shd n n n_ 



ru — u — u~ 
_n n n 



SP1 
SP2 



-a 



ji- 



ii — u — u — u 
_n ru_n__ 



n n n__n n__n_ 



J~L 



_n_ 



XDL1 1 I jl 

XDL2 _J L 



TL 



TL 



-386- 



SONY® 



CXD1156Q/R 






O 

■o 
o 

E 

o 

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CD 

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c 

1 



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a. 


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CM 


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X 


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SONY® 



CXD1156Q/R 



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CXD1156Q/R 



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CXD1156Q/R 



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CXD1156Q/R 



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SONY® 



CXD1156Q/R 



Package Outline Unit, mm 



48pin QFP (Plastic) . 7g 
D 1 5.3 ±<M 




SONY NAME 


Q.FP-48P-L04 


EI Ad NAME 


•QFP048-P-1212-B 


JEDEC CODE 







48p i n VQFP (Plastic) . 2g 




SONY NAME 


VQFP-48P-L01 


EIAJ NAME 


*QFP048-P-0707-A 


JEDEC CODE 







Detaild diagram of A 



Note) Dimensions marked with * do not include residual resin. 



392 



SONY. 



CXD1251Q 



Timing Generator for Blemish Compensation 



Description 

CXD1251Q is a CMOS LSI IC used for 
blemish compensation in CCD imagers such as 
ICX026AK/AL. ICX022AK (NTSC), ICX027AK/ 
AL. ICX024AK (PAL), CCD blemishes can be 
compensated at a rate of up to 10 per field. 

Features 

• Generation of blemish compensation pulses. 

• When used for blemish compensation in ICX 
026AK/AL and ICX027AK/AL it is combined 
with scanning IC's CXD1156R (Q). 

• For the blemish compensation in ICX022AK 
or 024AK it is combined with scanning IC 
CXD1149R. 

Structure 

CMOS LSI 

Application 

• Blemish compensation in CCD imagers 



Package Outline 



Unit : mm 



32 pin QFP (Plastic) 




H2CH 



w*T® 




QFP-32P-L01 



Absolute Maximum Ratings (Ta = 25 ° C) 

• Supply voltage Vcc Vss-0.5 to +7.0 V 

• Input voltage Vi Vss - 0.5 to Vdd + 0.5 V 

• Output voltage Vo Vss - 0.5 to Vdd + 0.5 V 

• Operating temperature Topr - 20 to + 75 °C 

• Storage temperature Tstg -55 to +150 °C 

Recommended Operating Conditions 

• Supply voltage Vcc 4.75 to 5.25 V 

• Operating temperature Topr - 20 to + 75 °C 



I 



80642 - ST 



-393 



SONY. 



CXD1251Q 



Block Diagram 



SP1I 



SP2I 



SP3I 



SHDI 



H2 



NC COL TG NTSC H2 6 




U<J<J<} 





MULTIPLEX 



01 02 03 04 AO A1 A2 A3 A4 A5 




BLEMISH ADDRESS 
COUNTER 



TIMING 
GENERATOR 



d 



_L_i. 



ROM ADDRESS 
COUNTER 



DECODER 



ttt t 



BLEMISH 
CORRECTION 




6) XVCT 



J 



394- 



SONY. 




CXD1251Q 


Pin Description 


No. 


Symbol 


I/O 


Description 


1 


A0 





Address output pin for external ROM 


2 


A3 





Address output pin for external ROM 


3 


A4 





Address output pin for external ROM 


4 


A5 





Address output pin for external ROM 


5 


NC 







6 


XVCT 





Control output pin for external ROM supply 


7 


DAT1 




Data input pin from external ROM 


8 


DAT2 




.Data input pin from external ROM 


9 


DAT3 




Data input pin from external ROM 


10 


DAT4 




Data input pin from external ROM 


11 


TEST 




Test pin. Normally GND 


12 


Vss 






13 


SP30 





S/H pulse output pin for blemish compensation 


14 


SP20 





S/H pulse output pin for blemish compensation 


15 


SP10 





S/H pulse output pin for blemish compensation 


16 


SHDO 





S/H pulse output pin for blemish compensation 


17 


SHDI 




S/H pulse input pin for blemish compensation 


18 


SP1I 




S/H pulse input pin for blemish compensation 


19 


SP2I 




S/H pulse input pin for blemish compensation 


20 


SP3I 




S/H pulse input pin for blemish compensation 


21 


H2G 




CCD horizontal scanning clock input pin 


22 


H2 




CCD horizontal scanning clock input pin 


23 


XV 1 




CCD vertical scanning clock input pin 


24 


XV3 




CCD vertical scanning clock input pin 


25 


HD 




Horizontal drive pulse input pin from sync generator IC 


26 


VD 




Vertical drive pulse input pin from sync generator IC 


27 


NTSC 




NTSC/PAL Mode select pin H : PAL L : NTSC 


28 


Vdd 




Supply 


29 


COL 




Color/B/W mode select pin H : B/W L : Color 


30 


TG 




TG mode select pin H : 1 149R L : 1 156R 


31 


A2 





Address output pin for external ROM 


32 


A1 





Address output pin for external ROM 



I 



395- 



SONY® 



CXD1251Q 



Peripheral Circuit (CXD1156 checkers in use) 




Electrical Characteristics 
DC characteristics 



Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Input voltage 


VlHC 




0.7VDD 






V 


VlLC 








0.3VDD 


V 


Input voltage 


VlH 


SP1 1. SP2I, SP3I, SHDI 


2.8 






V 


VlL 








0.6 


V 


Output voltage 


Voh 


Ioh = — 2mA 


Vdd - 0.5 






V 


Vol 


Iol = 4mA 






0.4 


V 



I/O capacity 



Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Input pin 


ClN 








9 


PF 


Output pin 


COUT 








11 


PF 



-396- 



SONY* 



CXD1251Q 



Connection Diagram for Respective Modes 

CXD1156 CXD1251 



SP1 
SP2 



XV1 



H2 



SP1I SP10 — 
SP2I SP20 
SP3I 
SHDI 

XV1 



H2 
H26 



CXD1149 



SP1 
SP2 



XV1 



XH1 



CXD1251 



SP1I SP10 
SP2I SP20 
SP3I 
SHDI 

XV1 



H2 
H2G 



Fig. 1. With CXD1156 checkers in use 



Fig. 2. With CXD1149 checkers in use 



CXD1156 



CXD1251 



SHD 

XV1 

XV3 

H2 

or 

XH1 



Phase regula- 
tion circuit ftr 
necessary 



SP1I 

SP2I 

SP3I SHDO 

SHDI 

XV1 

XV3 

H2 

H2G 



SHDR 
SHDG 
SHDB 



Fig. 3. CXD1 1 56 : BW in use 



■ 



-397 



SONY. 



CXD1255Q 



Timing Signal Generator of CCD Camera Scanner (for ICX038AK/039AK) 



Description 

CXD1255Q is a CMOS-type LSI developed for use 
in the imager scanner for both ICX038AK/AL(NTSC) 
and ICX039AK/AL (PAL). This IC is used in conjunc- 
tion with signal generators CXD1030M or 
CXDU58M. 

Features 

• Generates pulses for driving imagers ICX038AK/ 
AL and ICX039AK/AL 

• Generates signal processing pulses for chequered 
coding 

• NTSC (EIA)/PAL (CCIR) mode switchover. 

• Field/frame accumulation 

• Color and B/W mode 

• Electronic shutter operation 

• Built-in clock oscillation inverter 




Applications 

• CCD camera (NTSC/PAL) 

Structure 

• Silicon gate CMOS 



Block Diagram and Pin Configuration 




398 



SONY® 



CXD1255Q 



Pin Configuration (Top View) 




Absolute Maximum Ratings (Ta=25°C)V ss =0V 



• Storage temperature 

• Operating temperature 

• Supply voltage 

• Input voltage 

• Output voltage 



•stg 
' opr 

v DD 
v, 

V 



Recommended Operating Conditions 

• Supply voltage V DD 



-55 to +150 °C 

-20 to +75 °C 

V ss -0.5 to +7.0 V 

V ss -0.5toV DD + 0.5 V 

V ss -0.5toV DD + 0.5 V 



+4.75 to +5.25 



Pin Description 



No. 


Symbol 


I/O 


Description 


1 


SP1 





Color separation S/H pulse (Note 1) L 


2 


SHD 





CCD data output S/H pulse 


3 


SHP 





CCD precharge level S/H pulse 


4 


XV4 





Clock pulse for V register 


5 


XV2 





Clock pulse for V register 


6 


V ss 


— 


GND 


7 


TEST1 


1 


OPEN Pull-Up resistance 


8 


XV3 





Clock pulse for V register 


9 


XVI 





Clock pulse for V register 


10 


XSG2 





Sensor charge Read out pulse 


11 


XSG1 





Sensor charge Read out pulse 


12 


XRG 





CCD output reset pulse 


13 


FL 


1 


Electronic shutter flickerless, L: Flickerless, H: Normal 


14 


VAA 





Vertical blanking cleaning pulse 



I 



-399- 



SONY® 



CXD1255Q 



No. 
15 
16 



17 



18, 19 



20 



21 



22 



23 



24 



25 



26 



27 



28 



29 



30 



31 



32 



33 



34 



35 



36 



37 



38 



39 



40 



41 



42 



43 



44 



45 



46 



47 



48 



Symbol 



XH2 



XH1 



M0DE4 



XSUB 



EN 



D2 



Dl 



DO 



MODE3 



MODE2 



MODE1 



OSCI 



OSCO 



CK 



XCK 



VD 



HD 



CL 



TEST2 



PBLK 



ID 



CLP3 



CLP2 



CLP1 



I/O 



XDL2 



XDL1 



MODE6 



MODE5 



SP2 



Description 



GND 

Clock pulse for H register 



Clock pulse for H register 



Power supply 



Input switchover of electronic shutter speed, L: Serial input, H: parallel input 



Sensor discharge pulse 



Electronic shutter ON/OFF, L : Shutter OFF, H : Shutter ON 



Electronic shutter speed switchover input 



Electronic shutter speed switchover input 



Electronic shutter speed switchover input 



NTSC/PAL switchover, L: NTSC, H: PAL 



Field/frame accumulation switchover, L: Field H: Frame 



(Note 2) 



Oscillation inverter input 



Oscillation inverter output 



GND 



Duty controlling inverter input 



Duty controlling inverter output 



Vertical sync signal input 



Horizontal sync signal input 



Sync Generator clock output 



GND 



Pull-Down resistance 



Pre-blanking pulse 



Line identification pulse 



(Note 1) L 



Clamp pulse 



Clamp pulse 



Clamp pulse 



Power Supply 



Clock pulse for delay line 



(Note 1) SHDP 



Clock pulse for delay line 



(Note 1) L 



PBLK control pulse, L: Narrow H: Wide 



(Note 2) 



(Note 2) 



Color separation S/H pulse 



(Note 1) L 



Note 1) B/W mode output 

Note 2) See Operation (p.5) for MODE1, 5, and 6 switchover. 



-400- 



SONY® 



CXD1255Q 



Electrical Characteristics 
DC characteristics 



V DD = 5V±5%, V ss = 0V, T opr = -20to + 75°C 



Item 


Symbol 


Conditions 


Min. 


Typ. 


Max. 


Unit 


Input voltage 


H level 


v,„ 




0.7V DD 






V 


L level 


V, L 








0.3V DD 


V 


Input voltage 
(FL.EN.D0 to 2) 
* Schmitt trigger 


H level 


V T+ 




0.8V DD 






V 


L level 


V T - 








0.2V DD 


V 


Hysteresis 


»T+ " T _ 




0.7 


0.9 




V 


Output voltage 


H level 


VoH 


l 0H =-2mA 


V DD -0.5 






V 


L level 


Vol 


l 0L = 4mA 






0.4 


V 


Output voltage 

(Oscillation cell) (OSCO, XCK} 


H level 


Voh 


l 0H = -lmA 


V DD /2 






V 


L level 


V 0L 


l QL = lmA 






V DD /2 


V 


Input leak current 




V, = 0VtoV DD 


-10 




10 


*A 


Oscillation cell feedback resistance 


Rfb 




500K 


2M 


5M 


fi 



I/O capacity 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Input pin 


ClN 






9 


PF 


output pin 


CqUT 






11 


PF 



Test condition: V DD =V, = 0V, f = lMHz 

Operation 

CXD1255Q is provided with input pins for the setting of various modes. Related input pins are pulled up or 
pulled down beforehand inside the IC. Should an input pin be left open a certain.mode is selected. (The pull up/ 
down resistance value is approx. lOOkQ.) 

<For color usage) 



Pin 


No. 


Preset 


Description 


Input: "H" 


Input: "L" 


MODE1 


28 


L 


Normal : "L" 


MODE2 


27 


L 


Normal : "L" 


MODE3 


26 


L 


PAL 


NTSC 


M0DE4 


20 


H 


(Electronic shutter speed setting) 
Parallel input | Serial input 


MODE5 


47 


L 


Normal : "L" 


MODE6 


46 


L 


(PBLK control puis 
Wide 


s width switchover) 
Narrow 


EN 


22 


H 


Electronic shutter ON 


OFF 


FL 


13 


H 


Electronic shutter Normal 


Flickerless 


D2 


23 


H 


Electronic shutter speed control (described later in detail) 


Dl 


24 


H 


DO 


25 


H 







401 - 



SONY® 



CXD1255Q 



<For black-and-white usage) 



Pin 


No. 


Preset 


Description 


Input: "H" 


Input: "L" 


M0DE1 


28 


L 


Normal: "H" 


M0DE2 


27 


L 


Frame accumulation 


Field accumulation 


M0DE3 


26 


L 


PAL 


NTSC 


M0DE4 


20 


H 


(Electronic shutter speed setting) 
Parallel input | Serial input 


M0DE5 


47 


L 


Normal "H" 


M0DE6 


46 


L 


Normal "H" 


EN 


22 


H 


Electronic shutter ON 


OFF 


FL 


13 


H 


Electronic shutter Normal 


Flickerless 


D2 


23 


H 


Electronic shutter speed control (described later in detail) 


Dl 


24 


H 


DO 


25 


H 







Operating conditions are shown in timing charts 

• NTSC vertical timing chart 

• NTSC horizontal timing chart 

• PAL vertical timing chart 

• PAL horizontal timing chart 



402 



SONY® 



CXD1255Q 



Electronic shutter speed control 


























External pin 


Internal register 


Shutter speed 
XSUB® 


P/S 


EN 


CRNT 


FL 


D2 


Dl 


DO 






EN 


FL2 


FL1 


D2 


Dl 


DO 


T© 


t@ 


i® 


t© 


T@ 


t@ 


T@ 


D7 


D6 


D5 


D4 


D3 


D2 


Dl 


DO 


Parallel mode 
P/S=H 


H 


H 




H 


L 


L 


L 


















1/60 Note) 


H 


H 




H 


L 


L 


H 


















1/125 


H 


H 




H 


L 


H 


L 


















1/250 


H 


H 




H 


L 


H 


H 


















1/500 


H 


H 




H 


H 


L 


L 


















1/1000 


H 


H 




H 


H 


L 


H 


















1/2000 


H 


H 




H 


H 


H 


L 


















1/4000 


H 


H 




H 


H 


H 


H 


















1/10000 


H 


H 


L 


L 
























1/100 


H 


H 


H 


L 
























1/120 


H 


L 




























H 


Serial mode 

P/S=L 
FL=H 
EN = H 


L 


H 




H 












H 




H 


L 


L 


L 


1/60 Note) 


L 


H 




H 












H 




H 


L 


L 


H 


1/125 


L 


H 




H 












H 




H 


L 


H 


L 


1/250 


L 


H 




H 












H 




H 


L 


H 


H 


1/500 


L 


H 




H 












H 




H 


H 


L 


L 


1/1000 


L 


H 




H 












H 




H 


H 


L 


H 


1/2000 


L 


H 




H 












H 




H 


H 


H 


L 


1/4000 


L 


H 




H 












H 




H 


H 


H 


H 


1/10000 


L 


H 


H 


H 












H 


H 


L 








1/100 


L 


H 


H 


H 












H 


L 


L 








1/120 


L 


H 


L 


H 












H 


H 


L 








1/100 


L 


H 


L 


H 












H 


L 


L 








1/120 


L 


H 




H 












L 












H 


Serial mode 

parallel CTL 

P/S=L 


L 


H 


L 


L 
























1/100 


L 


H 


H 


L 
























1/120 


L ' 


L 




























H 










L 


MO 
-MO 


DE 3 
DE4 


CR/ 
P/S 


NT 


Ab 


brevi 


ation 


s 
C 


P : F 
)R: f 


>aral 
>AL 


el inf 


)Ut 

f 


S : Serial input 
MT : NTSC 




Note) 1/30 at accumulating NTSC frame. 



403- 



SONY® 



CXD1255Q 



AC Characteristics 

In serial input mode (M0DE4=L) 



"ZDS0S0QSDOC 



Jl 



Mode setting in serial input 



! ts2 ! th2 



i_r 



two i thO 



Symbol 


Item 


MIN 


ts2 


D2 set up time vs. Dl raising 


20ns 


th2 


D2 hold time vs. Dl raising 


20ns 


tsl 


Dl raising set up time vs. DO raising 


20ns 


twO 


DO pulse width 


20ns 


thO 


Dl raising timing vs. DO falling 


20ns 



404- 



SONY® 



CXD1255Q 



Applicaiton circuit 

< Color mode> 















■s 


^ 




■s 


















CXD1030 
(CXD1158) 



(Sync signal generation) 
NTSC 28.6363MHz 
PAL 28.375MHz 



Signal processing circuit 



<B/W mode> 




CXD1030 
(CXD1158) 




(Sync signal generation) 
NTSC 28.6363MHz 
PAL 28.375MHz 



Frame accumulation 



Field accumulation 



Signal processing circuit 



-405 



SONY® 



CXD1255Q 



UU3 



XI 



406 



SONY® 



CXD1255Q 



O 






I 



407 



SONY® 



CXD1255Q 



rrj3 



cxn 



w 



o 
o 



Z3 



n 



408- 



SONY® 



CXD1255Q 



o 



I 



409 



SONY® 



CXD1255Q 



High-speed clock detailed timing 

1. Color mode 



CHI 



~L 



_n 



j 



r 



n 



2. B/W mode 



XDL2 

(SHOP) 



LJ 



-410 



SONY® 



CXD1255Q 



Readout period extension chart 





N 
P 


10 

1 1 


7 






N:52. 
P:52. 


8 
1 












H.BLK 


^J 








r~ 
























XSG 1 i 


























XSG 2 1 


Ns42.2 
Ps43.3 


2.5 


2.5 


1 1 

2.5 i 










ODD field 






, 












| 






i i 












• 




mKm ^ 


I — l 




XV 2 


1 




1 






1 




XV 3 


1 


| 






i 












j 










XV 4 


1 


1 




2 


5 1 


i r 






' N:40.6 
Ps4 1 .8 












1 






xv ' . 


r~ 






XV 2 1 I 








L_ 




XV 3 | | 


i 




XV 4 


i 






_J 












1 


r 





Unit: ,uS 



Package Outline Unit: mm 



48pin QFP (Plastic) 0.6g 

D15.3 ±a4 




+ 0.1 

0.1 5 -0.05 



HZ7I Q.15 



^t^0-12|®l + .35 
22-0:i 5 



+ 0.2 

O.I-0.1 



I 



QFP-48P-L04 



411 



SONY. 



CXB0026AM 



CCD Driver 



Description 

CXB0026AM is a special version of CXB0026M 
with the following improvements: 

1) High frequency operation ability. 

2) Improved output voltage amplitude (voltage 
usage ratio). 

Other specifications match those of CXB0026M. 

Features 

• High frequency operation ability. 

• Improved output voltage amplitude. 

• TTL compatible input. 

• High output current drive. 

• 2.0 mW low consumption when input at low 
level. 

Structure 

Bipolar silicon monolithic IC 

Absolute Maximum Ratings (Ta=25°C) 

• Supply voltage 

• Input current 

• Input voltage 

• Instant output current 

• Junction temperature 

• Operating temperature 

• Storage temperature 

• Allowable power dissipation 
(Ta=70°C, PC Board Mount) 

Pin Configuration 



Package Outline 



Unit: mm 



8 pin SOP 



8 r n h h" 




o 


X 

<t 
2 
in 
in 


itl □ □ Da 

5.5 MAX 





2.0 MAX 




















f 


/ 


b 










+i 










00 




^ 


y 


d 

-H 
in 






^~ 






i. 




< 


3.22 „ 


m _ 



VCC-EE 


22 


V 


h 


100 


mA 


Vi 


Vee+5.5 


V 


lopk 


±1.5 


A 


Tj 


+ 150 


°C 


Ta 


to 70 


°C 


Tstg 


-65 to 1 50 


°C 


Pd 


400 


mW 



NC (l) (s) NC 

INPUT A (2) P>0 (7) OUTPUT A 

VEE (t) (£) vcc 

INPUT B (4) P>0 (5) OUTPUT B 



70847A-ST 



-412- 



SONY® 



CXB0026AM 



Equivalent Circuit 



— INPUT R1 
(2) O^-^AAr 

© 




OVEE (J) 



Electrical Characteristics 



Ta=0 to 70° C, Vcc-Vee=10 to 20V, Cl=1000 pF, Ta=25°C (Typ.) 



Item 


Symbol 


Min. 


Typ. 


• Max. 


Unit 


H level input voltage 
Vo=Vee+1.0 Vdc 


V1H 


Vee+2.0 


Vee+1.5 


- 


V 


H level input current 
Vi-Vee=2.4 Vdc, 
Vo=Vee+1.0 Vdc 


Mh 


- 


10 


15 


mA 


L level input 
Vo=Vcc-1.0 Vdc 


V1L 


- 


Vee+0.6 


Vee+0.4 


V 


L level input current 
Vi-VEE=0Vdc, Vo=Vcc-1.0 Vdc 


In 


- 


-0.005 


-10 


mA 


Output voltage at L level input 
Vi-Vee=0.4 Vdc 


VOH 


Vcc-1.0 


Vcc-0.7 


- 


V 


Output voltage at H level input 
Vi-VEE=2.4Vdc 


Vol 


- 


Vee+0.5 


Vee+1.0 


V 


Supply current at ON (1 circuit) 
Vcc-Vee=20 Vdc, 
Vi-Vee=2.4 Vdc 


ICCL 


- 


30 


40 


mA 


Supply current at OFF (1 circuit) 
Vcc-Vee=20 Vdc, Vi-VEE=OVdc 


ICCH 


- 


10 


100 


MA 



I 



-413 



SONY® 



CXB0026AM 



Switching Characteristics 



Vcc=7V, Vee=0V, Ta=25 C, Cl=270P 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Clock level 


Voh— Vol 


Vcc-0.5 


- 


Vcc 


V 


Propagation time (H-*L) 


tPHL 


4.75 


- 


6.75 


ns 


Propagation time (1_— »H) 


tPLH 


- 


- 


14 


ns 


Transition time (H— »L) 


tTHL 


- 


- 


11 


ns 


Transition time (L— »H) 


tTLH 


- 


- 


17 


ns 



Characteristics Test Circuit 




Vi=5.0V 
f=14 MHz 

tTLH=tTHL^8nS 

Duty 50% 



I/O Waveforms 



Input Waveform 




VOH 



VOL 



tTHL 



tTLH 



414 



SONY. 



CX20180/CXA1180N 



Vertical Clock Driver for CCD Imager 



Description 

CX20180 and CXA1180N are ICs which have 
been developed as a large capacitor drive for the 
vertical clock driver, etc. of the CCD imager. These 
are provided with the functions of incorporating 
almost all of the circuit necessary to the vertical 
clock driver of the CCD imager. 

Features 

• Low power consumption : 76 mW during CCD 
imager pick up ICX021 drive. 

• High efficiency power supply : Obtains the almost 
same amplitude of power supply voltage 

• Built-in interference suppression circuit : 
Suppression voltage approximately 0.4V. 

• Built-in almost all functions necessary to vertical 
driver circuits. 

1. Provided with 4 independent CCD imager driver 

blocks. 
2. Provided with inverter block for generating 

read out pulse. 
3. Provided with inverter block for generating 

negative voltage. 
4. Provided with saving circuit power consumption. 

Structure 

Bipolar silicon monolithic IC 



Package Outline 



Unit : mm 



Absolute Maximum Ratings (Ta = 25°C) 



• Input step bias voltage 

• Output step bias voltage 



• Operating temperature 

• Storage temperature 



Vcc1 

Vcc2-1 

Vcc2-2 

Vcc2-3 

Vcc2-4 

Vcc3-1 

Vcc3-2 

Topr 

Tstg 



• Allowable power dissipation Pd 



6 

25 

25 

25 

25 

25 

25 

-20 to +75 
- 55 to + 1 50 
CX20180 830 



CX20180 24 pin SOP (Plastic) 

1.85 ; &15 



2« 


15J3-OJ 


13 






BBBBBBBBBBBR 






O 


32 


5 
k 


HNH 


yyyyyyi 


in 


i 


MS' U 


12 
1.2 7 



r-lHfflO.15 I 



■ ! '- | (D |toj2)®| 



S0P-24P-L01 



CXA1180N 24 pin VSOP (Plastic) 



"i m i" an 



O 

TmiWBTET 



, 1.2 5 - o 



— Iffl Q-i Q 



.. _*0j05 I 



innnnnnnnnntri 




I 



VSOP-24P-L01 



mW 



CXA1180N 560 mW 



Recommended Operating Conditions 



• Input step bias voltage 

• Output step bias voltage 



Vcc1 

Vcc2-1 

Vcc2-2 

Vcc2-3 

Vcc2^t 

Vcc3-1 

Vcc3-2 



4.5 
5.5 
5.5 
5.5 
5.5 
5.5 
5.5 



5.5 
23 
23 
23 
23 
23 
23 



80846 -ST 



-415 



SONY® 



CX20180/CXA1180N 



Block Diagram and Pin Configuration (Top View) 



Vcc2-3(8] 



:c 2-1(9} 
V01 (10} 




6ND2 (12 



Block 2 




1 



24)Vcc3-2 




<mxvi 




13)Vcc3-1 



Pin Description and Equivalent Circuit 



No. 


Symbol 


Equivalent circuit 


Description 


1 


GND1 




Ground 


2 


NV 




Drive signal output of negative voltage generating 
circuit. 







416 



SONY® 



CX20180/CXA1180N 



No. 



Symbol 



Equivalent circuit 



Description 



V<t>4 




Output of imager drive circuit 4. 



Vcc2-4 



Output stage bias power supply of imager drive 
circuit 4. 



Output stage bias power supply of imager drive 
circuit 2. 



Vcc2-2 



V02 



V $3 




Output of imager drive circuit 2. 



Output of imager drive circuit 3. 



Vcc2-3 



Output stage bias power supply of imager drive 
circuit 3. 



Output stage bias power supply of imager drive 
circuit 1. 



Vcc2-1 



10 



11 



V<{» 1 



SG 




Output of imager drive circuit 1. 



Output of inverter for generating read out pul 



pulse. 



12 



GND2 



Ground 



13 



Vcc3-1 



Output stage bias power supply of inverter for 
generating read out pulse. 



14 



Vcc1 



Power supply of respective input stage and bias 
circuit. 



Input 1 of inverter for generating read out pulse. 
Input 2 of inverter for generating read out pulse. 



15 
16 
17 
18 
19 



XSG1 

XSG2 

XVI 

XV3 

XV2 




Input of imager drive circuit 1 , 



Input of imager drive circuit 3. 



Input of imager drive circuit 2. 



20 



21 



HBLK 



VAA 



■i-^W 



7 



Input 1 of power saving circuit. 



Input 2 of power saving circuit. 



22 



23 



XV4 



XNV 






Input of imager drive circuit 4. 



Input of drive circuit of negative voltage generating 
and rectifier circuit. 



24 



Vcc3-2 



Power supply of drive circuit of negative voltage 
generating and rectifier circuit. 



-417 



SONY® 



CX20180/CXA1180N 



Electrical Characteristics (Ta = 25°C) 

DC characteristics 

During open state of output Pin. 

Measuring condition (See the DC Characteristics Test Circuit.) 

Vcc1=5V Vcc2-4=11V 

Vcc2-1 = 11V Vcc3-1 = 11V 
Vcc2-2=11V Vcc3-2=11V 

Vcc2-3 = 1 1 V 



Item 


Symbol 


Test condition 


Input H 


Input L 


Unit 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Input current of 
XV 1, XV2. XV3, XV4 
or XNV 


IinXV 






0.10 


15 


- 15 


-2.5 




uA 


Input current of 
XSG1 


IinXSG 
1 


XSG2-H 




0.03 


15 


- 15 


-2.5 




uA 


Input current of 
XSG2 


IinXSG 
2 


XSG1-L 




0.03 


15 


-15 


-2.5 




HA 


Input current of 
HBLK or VAA 


IinHBL 
K 

IinVAA 


VAA- -L 

during HBLK-H 
VAA-H 

during HBLK-L 




55 


100 


-500 


-300 




HA 


Input voltage H level 






4.95 






^^— ^^_ 


V 


Input voltage L level 


VlN H 










0.05 


V 



Item 


Symbol 


Test condition 


Ouput H 


Ouput L 


Unit 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Output clip level 


Vo CLP 






11.1 


11.45 


-0.47 


-0.38 




V 



(See the Test Circuit) 



Item 
(Consump- 
tion 
current) 


Symbol 


HBLK-L VAA -L 


BLK-H VAA-H 


Unit 


Remarks 


Input H 


Input L 


Input H 


Input L 


Typ. 


Max. 


Typ. 


Max. 


Typ. 


Max. 


Typ. 


Max. 


Vcc2-1 or 
Vcc2-2 


Icc2-1 
lcc2-2 


2.0 


2.5 


2.3 


3.0 


3.4 


4.5 


0.5 


1.0 


mA 


Input indicates 
XV 1 or XV2 


Vcc2-3 or 
Vcc2-4 or 
Vcc3-1 


lcc2-3 
lcc2-4 
Icc3-1 


2.0 


2.5 


2.3 


3.0 


0.5 


1.0 


3.4 


4.5 


mA 


Input indicates 
XV3 or XV4 or 
XSG1 or XSG2 


Vcc3-2 


lcc3-2 


1 


100 


200 


300 


1 


100 


300 


500 


MA 


Input indicates 
XNV 


Vcc1 


Iccl 


2.0 


2.7 


3.8 


4.8 


1.2 


1.6 


3.1 


3.9 


mA 


Input indicates all 
input pins except 
HBLK and VAA 



-418- 



SONY® 



CX20180/CXA1180N 



Characteristics during CCD imager ICX021 drive 

Vcc1 = 5V, Vcc2 = 7.5V, Vcc3 = 11V (See the Characteristics Test Circuit during the operating) 



Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Subsequent to XV1 becoming H level, 
the V <t> 1 output level after T1 sec 


V<|> 1l 


T1 = 590 ns 




0.22 


0.4 


V 


Subsequent to XV2 becoming H level, 
the V <}> 2 output level after T1 sec 


V$2l 


T1 =530 ns 




0.22 


0.4 


V 


Subsequent to XV3 becoming H level, 
the V <t> 3 output level after T1 sec 


V4>3l 


T1 = 590 ns 




0.22 


0.4 


V 


Subsequent to XV4 becoming H level, 
the V <J> 4 output level after T1 sec 


V<|>4l 


T1 = 500 ns 




0.1 


0.4 


V 


Subsequent to XV1 becoming L level, 
the V 1 output level after T2 sec 


V$ 1h 


T2 = 1 .47 us 


6.8 


7.2 




V 


Subsequent to XV2 becoming L level, 
the V <(> 2 output level after T2 sec 


V<|>2h 


T2= 1.18 us 


6.8 


7.2 




V 


Subsequent to XV3 becoming L level, 
the V (J> 3 output level after T2 sec 


V4>3h 


T2 = 1 .24 us 


6.8 


7.2 




V 


Subsequent to XV4 becoming L level, 
the V $ 4 output level after T2 sec 


v>4h 


T2= 1.17 us 


6.8 


7.2 




V 


Current consumption Vcc1 


loci 




1.4 


2.0 


2.5 


mA 


Current consumption Vcc2 


Icc2 




5.0 


7.0 


9.0 


mA 


Current consumption Vcc3 


Icc3 




1.0 


1.5 


2.0 


mA 



DC Characteristics Test Circuit 



Output Open 




■ 



419 



SONY. 



CX20180/CXA1180N 



Electrical Characteristics Test Circuit 

(During CCD Imager ICX021 drive) 



Vcc 2 +7.5V 



CX23047A 
Timing 

generator for 
CCD 



3.3>/F 
10V 



3->r^ 



Operate With PAL spec. 



Vcd 




sgOi 

Vcc 2-3(8 
Vcc2-1(9 
Vcc2-4(4 
Vcc 2-2 (5 

)hblkCX20180/ 
)vaa CXA1180N 




10pF 
35V 



V V 




20 pin (ceramic) CCD 
ICX021 



4 6 12 13 15 16 17 18 19 



+\- 



£ £ T 01 > J 

ceramic 



i00p/T\ i* -r 



10p 



100)1 10)i Tantalum 
10V 10V 



O.lp 



Input voltage 








xvi 5V — \ , 
XV2 \ ; 
XV3 \ 


/ .: 


\ 


XV4 25V V- 




ZJ\ 


\ 


ov ' - 






Output voltage 


^ K" 


f 


V02 ] / 
V03 [/ 


T2 


1 \ T1 1 


1 


\/<M / 





Output High level voltage 
Output Low level voltage 



-420- 



SONY® 



CX20180/CXA1180N 



Standard Circuit Designing Material 

DC characteristics 

When right circuit has been constructed 
DC current during all inputs have 
been set to "L" 

led = 3.8 mA 

Icc2 = 9.2 mA 

Icc3 = 2.5 mA 
DC current during all inputs have 
been set to "H" 

Icc1 = 2.0 mA 

Icc2 = 8.0 mA 

Icc3 = 2.0 mA 



Input 



GNDO 
GNDO 



Input 



Vcc3 +11 V 



Vcc2 +7.5V 



Qlccl Qicc3 • Q|, 



SBO u V SBO 

10>i 35V "*" "*" 




Application Circuit 




ICX018 / ICX021 

CCD Imager 



. Timing generator for 
CX23047A CCD 



Operation 

CX20180 and CXA1 180N are composed of 7 blocks necessary to the V clock driver, and these 
are compact and enable to drive of the CCD imager with low power consumption. (See the 
Block Diagram.) 

Block 1, SG2 input inverter circuit 

Inverter which has 2 input AND Gate as the input, and it is a block used to produce read 
out pulse outside of the IC. 



-421 



SONY® CX20180/CXA1180N 



Block 2 to 5 inverter circuit 

Inverter which has 4 entirely identical circuit compositions, and these actually drive the CCD 
imagers. These drive circuits build-in interference suppressed circuits so as not to accept 
interference due to junction capacity among phases of the CCD. 

Block 6 negative voltage generating circuit 

Output pulse of this block is rectified and made into negative voltage with the external 
circuit, and applied to signals of blocks 2 to 5. 

Block 7 power save mode and normal mode 

Performs switchover of Power save mode * and Normal mode * of blocks 1 to 6. Input is 
of 2 input AND gate. 

* Power save mode and normal mode 

This IC supplies output stage drive current during blanking period only as low power 
consumption is realized when used to drive CCD imager. Effective use of electrical power 
is exercised by saving the output stage drive current during other periods. Power save mode 
is a mode in which the output stage drive current is saved, and Normal mode is defined 
as a mode in which the general drive current is flowed fully. 
Power save mode 
HBLK- "H" VAA- "H" 



Normal mode 






HBLK- "L" 


VAA- 


«L» 


HBLK- "H" 


VAA •• 


• "L" 


HBLK-- "L" 


VAA- 


"H" 



Bias circuit is built-in. 

Note on Use 

• Special care should be taken for the following points on printed circuit board design. 
During CCD image device driving, a large inrush current flows. 

1. Connect the grounding pin of IC and the grounding pattern of printed circuit board in the 

shortest distance. 
2.Connect the decoupling capacitor and the grounding pattern of printed circuit board in the 

shortest distance. 

• Driving condition 

1.A general purpose CMOS IC can be used to drive this IC. The input current is maximum 

500 uA. 
2.Wiring of the input signal line of the drive should be made as short as possible to keep 

it away from the effect of stray capacitance. 
3. There may be a possibility of ringing due to the inductance of the line, if wiring of the 

output signal line is long. In the event that, countermeasure for it should be performed by 

inserting resistors in series to the signal line, etc. 
4. There may be possibility of causing an operational error, if there is a voltage difference 

between the CMOS IC which drive this IC and the bias voltage of Vcc1 of this IC, therefore, 

the Vcc1 and the CMOS IC Bias should use the same power supply. 



-422 



SONY® 



CX20180/CXA1180N 



Characteristics during CCD imager ICX021 drive. (See the Electrical Characteristics Test Circuit) 



Vcc1 consumption current vs. 
Ambient temperature 



2.00 
1.00 

































































Un 


used 


»S mo 


de * 








Us 


ed PS 


mode 


* 

















-20 20 40 60 80 

Ta-Ambient temperature (°C) 



Vcc2 consumption current vs. 
Ambient temperature 



512.00 
E 11.00 



> 7.00 









I I I 

Unused PS mode * 

























































































-20 20 40 60 80 

Ta-Ambient temperature (°C) 



Vcc3 consumption current vs. 

Ambient temperature 



< 6.00 

E 

I 500 

u 

c 4.00 

o 

E 3.00 

3 

V) 

c 

9 2.00 

m 

o 
o 

> 1.00 

































































Un 


used 


S S mo 


de * 




































ed PS 


mod* 













-20 20 40 60 80 

Ta-Ambient temperature (°C) 




*) P.S mode : See power save mode. 



-423 



SONY® 



CX20180/CXA1180N 



Temperature characteristics of rising and falling waveforms of output voltage V 4> 1 , V $ 2, 
V <t> 3 and V <t> 4 



5V 

Input voltage waveform 
(XV\,XV2\ 
\XV3, XV4/ OV 



7V - 



Output voltage waveform 

/V<*>1,V02\ 

\.V*3, V<tA) 















































' 




















/ 
























\ 
















J 










































































































Ta = - 


-20° C 






-Ta 


= 25 


C 






































1 

— Ta 


1 1 

= 75 


1 

3 C 














































T 


a = — 


20° C 




[•- Ta = 75°C 


































\ 1 1 1 
l_Ta = 25°C 




























































I 



























































































































Time (1 OOns/div) (t) 



Temperature characteristics of rising and falling waveforms of NV output voltage 



































5V 

Input voltage waveform 
(XNV) 




\ 














f 


















\ 










J 
















OV 
































11V 
































Output voltage waveform 






I 


-Ta 


= 75 


°C 


a = 2E 
= -2C 




L 


_Ta 


= 75 c 


C 








Ta 


a = 2 
= -2 


5°C-- 
3°C 


H 






— T 
Ta 


°cj 


i 
































1 


















































i 














. 












OV 

































Time C1 OOns/div] (t) 



424- 



SONY® 



CX20180/CXA1180N 



Rising and falling waveforms of V <|> 1 , V <t> 2, V<t>3 and V <t> 4 SG output voltage at capacity 
load (Normal mode) 



5V 



Input voltage waveform 
XV1, XV2 
XV3, XV4 
XSG1.2 



OV 



100% 
90% 

Output voltage waveform 

/V01,V02\ 

( V03, V<*>4 J 

10% 
0% 



















































^~ 






























. 


































































\ 
































\ 

















































































































































































































Test Circuit 



Time C200ns/div) (t) 



V CC 1=+5V +7V V cc 2-1,2-2 
2-3, 2-4 
or 3-1 



Input XV1, XV2 
XV3, XV4 



XSG1 lis measured by connection 
XSG2 / 




Output V01 , V02 
V<J>3, V04 
or SG 



I 



-425 - 



SONY. 



CXA1065M 



Vertical clock driver for CCD imagers 



Description 

The CXA1065M is a bipolar IC developed to 
drive the vertical shift register of CCD imagers 
(ICX022 etc.). 

It is composed of seven drivers that can drive 
large capacitors with wide voltage amplitude. A 
suppressing function of coupling between phases 
reduces blooming and smear to make this IC ideal 
for vertical clock driving of CCD imaging devices. 

Features 

• Almost all functions required for vertical clock 
driving of CCD imager are provided. 

• Negative voltage source is not needed. 

• Suppressing function of coupling between 
phases. 

• Wide output amplitude — Output voltage am- 
plitude is almost equal to supply voltage. 

• Wide operating voltage range -5.5 to + 25 V 

• Low power consumption with the built-in 
power-saving circuit — 1 16 mW Typ. when 
the ICX022 equivalent circuit load is driven. 



Package Outline 



Unit: mm 



24 pin SOP 



24 


1M-(1 


13 




^BfH BBBBHBBE 






O 


33 


a 


=1 N N t 


y y y y y y iji k 






(M5 ±<u 


— — 




2 

J.2 7 




SOP-24P-L01 



Block Diagram 



Structure 






Silicon monolithic IC 






Absolute Maximum Ratings (Ta 


= 25°C) 




• Supply voltage Vcd 


6 


V 


Vcc2-1 


27 


V 


Vcc2-2 


27 


V 


Vcc2-3 


27 


V 


Vcc2-4 


27 


V 


Vcc3 


27 


V 


Vcc4 


27 


V 


• Operating temperature Topr 


-20 to +75 


°C 


• Storage temperature Tstg 


-55 to +150 


°C 


• Allowable power 






dissipation Pd 


560 


mW 


Recommended Operating Conditions 




Vcd 


4.5 to 5.5 


V 


Vcc2-1 


5.5 to 25 


V 


Vcc2-2 


5.5 to 25 


V 


Vcc2-3 


5.5 to 25 


V 


Vcc2-4 


5.5 to 25 


V 


Vcc3 


5.5 to 25 


V 


Vcc4 


5.5 to 25 


V 



®- 



@h 



<SG2 ©■ 



@- 



XVI (% 




Negative 
voltage^ 
generation^ 
driver. 







) V » 4 

) VC C 2-4 

) vc c 2-3 
) v» 3 



<6) SG2 



I V« 2 
vc c 2-2 



-0 



426- 



SONY® 



CXA1065M 



Pin Configuration (Top View) and Description 



24 



13 



flflHHBRRBHRHR 




r¥¥T¥¥¥¥TO¥¥ 



12 



No. 


Symbol 


Description 


Equivalent circuit 






Function of each driver is inverter. 




Truth table 


Input 


Output 




L 


H 


H 


L 


1 


SG1 


Sensor gate driver 1 


Output 
pins 




Vcc 


2 


Vcp1 


Vertical clock driver 1 


5 


V02 


Vertical clock drivr 2 


6 


SG2 


Sensor gate driver 2 




r 1 




pin 

: 

Output 
Din 


7 


V03 


Vertical clock driver 3 


K 

— £ 


k 


i 


10 


V<*>4 


Vertical clock driver 4 


11 


NV 


Negative voltage generation driver 




; 


k 


0000 
©0© 


3 


Vcc2-1 


Vertical clock driver 1 


Vcc 
pins 


K 1 


4 


Vcc2-2 


Vertical clock driver 2 




\ 




8 


Vcc2-3 


Vertical clock driver 3 


i 


' " k 


9 


Vcc2-4 


Vertical clock driver 4 


13 


Vcc4 


Negative voltage generation driver 


23 


Vcc3 


Sensor gate driver 1, 2 


12 


GND1 






24 


GND2 









I 



-427- 



SONY® 



CXA1065M 



No. 



Symbol 



Description 



Equivalent circuit 



14 



15 



16 



17 



18 



19 



20 



XNV 



XV 4 



XV3 



XSG2 



XV 2 



XV 1 



XSG1 



Negative voltage generation driver 



Vertical clock driver 4 



Vertical clock driver 3 



Sensor gate driver 2 



Vertical clock driver 2 



Vertical clock driver 1 



Sensor gate driver 1 



Input 
pin 



© 
® 



- Vcd 



^ 



21 PS Input pin for the power-saving signal 

(For the power-saving function, refer to 
the Description of Functions.) 




Vcd 



22 



Vcd 



Power supply of the bias circuit. 



428- 



SONY® 



CXA1065M 



Electrical Characteristics 



DC characteristics 

Ta = 25°C 

Vcci = 5V, VCC2-1 = 1 2V, Vcc2-2= 1 2V, Vcc2-3= 1 2V, Vcc2-4= 12V, Vccs= 1 2V, Vcc4= 1 2V 

With outputs open 





Parameter 




Symbol 


.... Blank OV 
Input condition _.. 


Min. 


Typ. 


Max. 


Unit 




PS 


XV 1 


XV2 


XV3 


XV4 


XSG1 


XSG2 


XNV 


Input current into PS pin 


Input current 
low level 


IlLPS 


















-500 


-270 




tA 


Input current 
high level 


llHPS 


H 


















0.03 


15 


nA 


Input current 
into 7 drivers 


Input 
current 
low level 


XV 1 


IlLXVI 


















-15 


-2.5 




pA 


XV 2 


IILXV2 


















XV3 


IILXV3 


H 
















XV4 


IILXV4 


H 
















XSG1 


IILXSG1 


H 
















XSG2 


IILXSG2 


. H 
















XNV 


IlLXNV 


















Input 
current 
high level 


XV 1 


llHXVI 




H 
















0.03 


15 


pA 


XV2 


IIHXV2 






H 












XV3 


IIHXV3 








H 










XV4 


IIHXV4 










H 








XSG1 


IIHXSG1 












H 






XSG2 


IIHXSG2 














H 




XNV 


llHXNV 
















H 


Input 
voltage 


Low level 


VlL 






















0.05 


V 


High level 


VlH 


















4.95 






V 



I 



-429 



SONY® 



CXA1065M 



Parameter 




Symbol 


... Blank OV 
Input condition H _ y 


Min. 


Typ. 


Max. 


Unit 




PS 


XV 1 


XV2 


XV3 


XV4 


XSG1 


XSG2 


XNV 


DC supply cuttent of 
bias circuit at Vcci 


PS: L 

All inputs: L 


Icci LL 


















1.5 


3.5 


5.5 


mA 


PS: L 

All inputs: H 


led LH 




H 


H 


H 


H 


H 


H 


H 


0.5 


1.7 


3.0 


mA 


PS: H 

All inputs: L 


ICCI HL 


H 
















1.5 


3.2 


5.0 


mA 


PS: H 

All inputs: H 


ICC1 HH 


H 


H 


H 


H 


H 


H 


H 


H 


0.5 


1.3 


2.5 


mA 


DC supply current of 
vertical clock driver 1 at 

VCC2-1 


PS: L 
XV1: L 


ICC2-1 LL 


















0.5 


2.0 


3.0 


mA 


PS: L 
XV1: H 


ICC2-1 LH 




H 














PS: H 
XV 1: L 


ICC2-1 HL 


H 
















0.1 


0.5 


1.0 


mA 


PS: H 
XVI: H 


ICC2-1 HH 


H 


H 














1.5 


3.2 


5.0 


mA 


DC supply current of 
vertical clock driver 2 at 

VCC2-2 


PS: L 
XV2: L 


ICC2-2 LL 


















0.5 


2.0 


3.0 


mA 


PS: L 
XV2: H 


ICC2-2 LH 






H 












PS: H 
XV2: L 


ICC2-2 HL 


H 
















0.1 


0.5 


1.0 


mA 


PS: H 
XV2: H 


ICC2-2 HH 


H 




H 












1.5 


3.2 


5.0 


mA 


DC supply current of 
vertical clock driver 3 at 

VCC2-3 


PS: L 
XV3: L 


ICC2-3 LL 


















0.5 


2.0 


3.0 


mA 


PS: L 
XV3: H 


ICC2-3 LH 








H 










PS: H 
XV3: L 


ICC2-3 HL 


H 
















1.5 


3.2 


5.0 


mA 


PS: H 
XV3: H 


ICC2-3 HH 


H 






H 










0.1 


0.5 


1.0 


mA 


DC supply current of 
vertical clock driver 4 at 

VCC2-4 


PS: L 
XV4: L 


ICC2-4 LL 


















0.5 


2.0 


3.0 


mA 


PS: L 
XV4: H 


ICC2-4 LH 










H 








PS: H 
XV4: L 


ICC2-4 HL 


H 
















1.5 


3.2 


5.0 


mA 


PS: H 
XV4: H 


ICC2-4 HH 


H 








H 








0.1 


0.5 


1.0 


mA 


DC supply current of 
sensor gate drivers 1 , 2 
at Vcc3 


PS: L 
XSG1, 2: L 


ICC3 LL 


















1.0 


4.0 


6.0 


mA 


PS: L 
XSG1, 2: H 


ICC3 LH 












H 


H 




PS: H 
XSG1, 2: L 


ICC3 HL 


H 
















3.0 


6.4 


10.0 


mA 


PS: H 
XSG1, 2: H 


ICC3 HH 


H 










H 


H 




0.1 


0.7 


1.4 


mA 


DC supply current of 
negative voltage genera- 
tion driver at Vcc4 


XNV: L 


ICC4L 


















0.5 


2.0 


3.0 


mA 


XNV: H 


ICC4H 
















H 



-430- 



SONY® 



CXA1065M 



Characteristics when CXA1065M drives the equivalent circuit of CCD imager, ICX022 
Supply current 



Ta = 25°C, Vcci = 5V, Vcc2= 10.6V, Vcc3= 13.4V, Vcc4= 10.6V 
The CXD1035B (timing generator) is used as the input signal source. 



Parameter 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Supply current at Vcci 


Icci 




0.5 


1.9 


3.0 


mA 


Supply current at Vcc2 


ICC2 




3.0 


7.1 


8.5 


mA 


Supply current at Vcc3 


ICC3 




0.2 


0.8 


1.5 


mA 


Supply current at Vcc4 


ICC4 




0.5 


2.0 


3.0 


mA 



Output waveform of each driver 



Ta = 25°C, Vcci = 5V, Vcc2=10V, Vcca=13.4V, Vcc4=10.6V 
The CXD1035B (timing generator) is used as the input signal source. 



Parameter 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Output 

waveform 

of negative 

voltage 

generation 

driver 


Falling edge voltage 


Vnvl 


Voltage at NV at 350ns after 
XNV rising edge 


0.05 


0.71 


1.15 


V 


Rising edge voltage 


Vnvh 


Voltage at NV at 350ns after 
XNV falling edge 


9.45 


10.13 


10.55 


V 


L level voltage 


Vnvll 


Voltage at NV at 2100ns after 
rising edge of XNV 


-0.08 


-0.02 


0.04 


V 


H level voltage 


Vnvhh 


Voltage at NV at 2100ns after 
at XNV falling edge 


10.52 


10.58 


10.64 


V 



I 



-431 - 



SONY® 



CXA1065M 



Parameter 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Output 
waveforms 
of vertical 
clock drivers 
1. 2, 3, 4 


L 

level 

voltage 


V«i 


V*1L 


Voltage at V*i at 490ns after XV 1 rising edge 


0.06 


0.32 


0.80 


V 


V«2 


V«2L 


Voltage at V*2 at 490ns after XV 2 rising edge 


0.35 


V*3 


V*3L 


Voltage at V«3 at 490ns after XV3 rising edge 


0.45 


V*4 


V«4L 


Voltage at V*4 at 490ns after XV4 rising edge 


0.47 


H 

level 

voltage 


V*i 


V01H 


Voltage at V«1 at 1050ns after XV 1 falling edge 


9.91 


9.98 


10.06 


V 


V«2 


V«2H 


Voltage at V«2 at 1050ns after XV2 falling edge 


V*3 


V«3H 


Voltage at V«3 at 1050ns after XV3 falling edge 


V«4 


V«4H 


Voltage at V#4 at 1 050ns after XV4 falling edge 


L 

coupling 
voltage 


V*1 


V«1LL 


Voltage at V«1 at 280ns after XV2 rising edge 


-0.58 


-0.29 


0.01 


V 


V«2 


V«2LL 


Voltage at V02 at 280ns after XV3 rising dege 


-0.55 


-0.34 


-0.12 


V 


V«3 


V«3LL 


Voltage at V«3 at 280ns after XV4 rising dege 


-0.60 


-0.37 


-0.13 


V 


V*4 


V«4LL 


Voltage at V«4at 280ns after XV 1 rising dege 


-0.60 


-0.42 


-0.23 


V 


H 

coupling 

voltage 


V*1 


V*1HH 


Voltage at V«1 at 280ns after XV2 falling edge 


10.16 


10.46 


10.62 


V 


V«2 


V«2HH 


Voltage at V«2 at 280ns after XV3 falling edge 


10.45 


V*3 


V«3HH 


Voltage at V«3 at 280ns after XV4 falling edge 


10.37 


V*4 


V«4HH 


Voltage at V«4at 280ns after XV 1 falling edge 


10.44 


L 

coupling 

amplitude 


V*1 


V011-LI 


V*1L— V*1LL 


0.14 


0.61 


1.07 


V 


V«2 


V«2L-LL 


V«2L — V«2Ll 


0.25 


0.68 


1.10 


V 


V«3 


V«3L-LL 


V«3L — V«3LL 


0.36 


0.81 


1.26 


V 


V*4 


V*4L-LL 


V*4L— V«4LL 


0.44 


0.88 


1.32 


V ~ 


Output 
waveforms 
of sensor 
gate drivers 
1, 2 


Falling 

edge 

voltage 


SGi 


VSG1L 


Voltage at SGi at 350ns after XSG1 rising edge 


0.14 


0.84 


1.46 


V 


SG2 


VSG2L 


Voltage at SG2 at 350ns after XSG2 rising edge 


0.88 


Rising 

edge 

voltage 


SGi 


VSG1H 


Voltage at SGi at 350ns after XSG1 falling edge 


11.94 


12.74 


13.26 


V 


SG2 


VSG2H 


Voltage at SG2 at 350ns after XSG2 falling edge 


12.59 


L 

level 

voltage 


SGi 


VSG1LL 


Voltage at SGi at 1330ns after XSG1 rising edge 


-0.11 


0.00 


0.11 


V 


SG2 


VSG2LL 


Voltage at SG2 at 1330ns after XSG2 rising edge 


H 

level 

voltage 


SGi 


VSG1HH 


Voltage at SGi at 1330ns after XSG1 falling edge 


13.25 


13.36 


13.47 


V 


SG2 


VSG2HH 


Voltage at SG2 at 1 130ns after XSG2 falling edge 



432- 



SONY® 



CXA1065M 



Electrical Characteristics Test Circuit 1 

DC characteristics testing 



5V O- 



5V O- 



5V O- 



5V o- 



5V o- 



5V o- 



5V O- 





vXV3 



,XSG2 



,XV2 



XSG1 










£ 



> 



Vcc2-3 




Vcc2-2 



Vcc2 -1 



CXA1065M 



^L vcc2 
12V 



i Outputs 
open 



I 



Fig. 1 



-433 



SONY® 



CXA1065M 





a> 




> 








T3 




S 


OJ 


in 




CO 




o 


3 




O 


< 


u 


X 


** 


u 




c 
a> 

.c 


w 


S 


o 




** 


03 


(0 


r 










0) 


v> 


♦* 


<n 


o 




(0 





co c 
O t 



a a. 
o a 

HI (/) 




iZ 



-434- 



SONY® 



CXA1065M 




O 



n 
O 



i 5 



rA & ^^^ 



^A 



>4r 4-Sci 




CO 



I 



435 - 



SONY® 



CXA1065M 



Timing Chart 

Waveform testing of 4-phase vertical clock drivers 




Fig. 4 



Waveform testing of sensor gate drivers and negative voltage generation drivers 



XSG1 


5V 


XSG2 


OV 


SG1 
SG2 






5V- 
OV- 





- - T - VNVL 



Fig. 5 



-436 



SONY® 



CXA1065M 



Description of Operation 

Description of functions and operation of the CXA1065M internal circuits 

The CXA1065M is composed of a bias circuit and seven drivers. 

Apply a voltage of 5 V to the Vcc1 terminal of the bias circuit. This circuit not only determines 
the DC bias for the seven drivers, but also has a power-saving function which reduces the power 
consumptions of four vertical clock drivers and two sensor gate drivers. 

Directly connect the output of a CMOS IC to the input pins of the seven drivers. (Signal level, H: 
5V, L: OV) The output signal of each driver is inverted with low output impedance and wide ampli- 
tude. The output H level voltage of each driver is almost equal to the bias voltage of output stage 
and the L level output voltage is almost equal to the ground level. (See Fig. 6.) 



Input pin (/y 




Output stage of 
power supply pin 

Output pin 



Input 
signal 



Output_ 
signal 



\ 



-— 5V 

— ov 



Output stage 
bias voltage 



OV 



Fig. 6 

The 4-phase clock drivers have a suppressing function of the coupling between phases when a 
CCD imager is driven. This function is suppress coupling voltage from other phases through the im- 
ager junction capacitances. 
*Power-saving function 

The CCD imaging device is equivalently, capacitive load. 
Then a large driving ability is required only in the transient period of the output, and there is no need 
for such a large ability in other periods. The DC bias of the 4-phase clock drivers and 2 sensor gate 
drivers is changed by the input signal at the PS pin with appropriate timing, to reduce bias current 
when a large driving ability is not needed and achieve low power consumption. 

Reference data: Typical va'ues of supply current when the ICX022 equivalent circuit is driven (See 
Fig. 2) 





Using power-saving 
function 


Not using power- 
saving function 
(PS pin fixed at OV) 


Supply current at Vcc1 


1.9 mA 


2.3 mA 


Supply current at Vcc2 


7.1 mA 


12.7 mA 


Supply current at Vcc3 


0.8 mA 


3.3 mA 


Supply current at Vcc4 


2.0 mA 


2.0 mA 



437 



SONY® 



CXA1065M 



Description of Operation (CCD imager (ICX022) vertical clock driving system) 

(For further information on the driving system of the CCD imager, refer to the specifications.) 

Connect the output pin of the CXD1035B (CMOS IC) which is the CCD camera scanning timing 
generator, to the respective pins (Pin 14 through 21) of CXA1065M. 

Clamp the output signal of the 4-phase vertical clock driver to the low level and input it to the verti- 
cal shift register transfer clock pin of the CCD imager. 

Rectify the output signal of the negative voltage generation driver to obtain two reference voltage 
(negative voltages) for the low-level clamp. These two voltages are provided to compensate the clamp- 
ing loss which may occur from the difference in duty between the 4-phase vertical clock drive sig- 
nals. (When stable low-level clamp reference voltage supply is available with in the equipment, the 
rectifying circuit for the negative voltage is no more required.) 

With the system shown in Fig. 8, the H level voltage of V clock level of the 4-phase vertical clock 
drive signals after the low-level clamp, is kept at V even if Vcc4 is varied. This is because the circuit 
is designed to keep the low-level clamp reference voltage equal to the output voltage amplitude of 
the vertical clock drivers. 

To obtain one of the readout clock pulse signals: The output signal of sensor gate driver 1 is used 
to modulate the output bias voltage of vertical clock driver 1 . 

To obtain the other signal: The output signal of sensor gate driver 2 used to modulate the output 
bias voltage of vertical clock driver 3. 

If no source of high DC voltage is available in the equipment, the output signal for negative voltage 
generation driver can be utilized to generate the CCD imager substrate voltage. (See Fig. 7.) 

Substrate voltage generation circuit 

When maximum DC power supply in the equipment is + 1 5V 



v _n_ 




oTo the CCD imager 
VSUB pin. 



Fig. 7 



438 



SONY® 



CXA1065M 



Performance Curves 

Supply current when the ICX022 equivalent circuit is driven (Refer to the Test Circuit in Fig. 2). 



Supply current at Vcc1 vs. 

Ambient temperature 



4.0 


































3.0 
























2.0 
























I.O 

























-20 20 40 60 80 

Ta — Ambient temperature (°C) 



Supply current at Vcc2 vs. 

Ambient temperature 



8.0 
7 






















6.0 








5.0 
4.0 
3.0 
2.0 
1.0 

n 































































-20 20 40 60 80 

Ta — Ambient temperature (°C) 



Supply current at Vcc3 vs. 

Ambient temperature 



_ 4.0 
< 

E 



3.0 



S 2.0 



1.0 



" • • . 



-20 20 40 60 80 

Ta — Ambient temperature (°C) 



Supply current at Vcc4 vs. 

Ambient temperature 



4.0 






















3.0 
































— •— 


2.0, 


^ 


i ' 








1.0 




































I 



_20 20 40 60 80 

Ta — Ambient temperature (°C) 



439- 



SONY® CXA1065M 

Notes on Application 

• A large current flow through the power supply pin or the GND pin during the transient period of 
the output signal. Therefore, the GND pin must be grounded at a point within 1 cm from the pin. 
In addition, set the by-pass capacitor of the power supply pin within 1 cm from the pin. 

• A conventional CMOS IC suffices as the input signal source of this IC (with an input current of 
Max. 500/iA). To obtain the sharp CCD imager driving signal, minimize the length of the signal line. 

• With an elongated signal line between the output pin of this IC and the input pin of the CCD imager, 
the inductance of the line may cause linking. To avoid this, shorten the line or insert a resistance 
in series to dump the linking. 

• If the signal line between the output pin of this CMOS IC and input pin of this IC is too long, stray 
capacitance is large. In this case input signal of this IC is dull then sharp CCD imager driving signal 
is not obtained. 



440- 



SONY. 



CXD1250M 



Vertical Clock Driver of CCD Imager 



Description 

CXD1250M is a clock driver developed for 
the vertical register drive of ICX026/027. 

Features 

• 4-channel vertical clock driver and 1 channel 
substrate driver are built-in. 

Structure 

CMOS 

Application 

• CCD camera 



Package Outline 



Unit : mm 



20 pin SOP (Plastic) 

, 2.1 5 MAX 



RHRHRRRRRH 



O 

ijiijiy y y y y y 



;.Z7 0.4 5 1 



^s 



1 - .. n 



Absolute Maximum Ratings (Ta = 25°C) 



• Supply voltage 


Vdd 






Vl- 


-0.3 to Vl + 35.0 


V 




Vm 






Vl- 


-0.3 to Vl + 35.0 


V 




Vh 






Vl- 


-0.3 to Vl + 35.0 


V 




Vhh 






Vl- 


-0.3 to Vl + 35.0 


V 


• Input voltage 


Vi 






Vl- 


-0.3 to Vdd + 0.3 


V 


• Output voltage 


MV (J> (pins 


11. 


13) 


Vl- 


-0.3 to Vm + 0.3 


V 


• Output voltage 


HV<|>(pins 


14, 


16) 


Vl- 


-0.3 to Vh + 0.3 


V 


• Output voltage 


HHV<t>(pin 


19) 




Vl- 


-0.3 to Vhh + 0.3 


V 


• Operating temperature 


Topr 








-25 to +85 


°C 


• Storage temperature 


Tstg 








-40 to + 1 25 


°C 


Recommended Operating Conditions 










• Supply voltage 


VrD 

Vm 

Vh 

Vhh 








Vl + 1 5.0 
Vl + 1 0.0 
Vl + 25.0 
Vl + 30.0 


V 
V 
V 
V 


• Operating temperature 


Topr 








-20 to +75 


°c 



p.B*° 



p.05M' 



(STANO OFF) 



o.i5^&8l 



SOP-20P-L021 



I 



80639 -ST 



441 - 



SONY* 



CXD1250M 



Block Diagram and Pin Configuration (Top View) 




ro 


(M 


<!■ 


> 


O 


> 


X 


V) 
X 


X 



Pin Description 



No. 


Symbol 


I/O 


Description 


1 


GND 





GND 


2 


XSub 




Output control (VSub) 


3 


XV2 




Output control (V + 2) 


4 


XV1 




Output control (V*i) 


5 


XSG1 




Output control (V*i) 


6 


XV3 




Output control (V * 3) 


7 


XSG2 




Output control (V * 2) 


8 


XV4 




Output control (V + 4) 


9 


Vdd 





Power supply (5V) 


10 


NC 







11 


NC 







12 


Vh 





Power supply (15V) 


13 


Vm 





Output (2 level : Vm, Vl) 


14 


V*3 





Output (3 level : Vh, Vm, Vl) 


15 


Vm 


— 


Power supply (0V) 


16 


V*i 





Output (3 level : Vh, Vm, Vl) 


17 


V*2 





Output (2 level : Vm, Vl) 


18 


Vl 


— 


Power supply (- 10V) 


19 


VSub 





Output (2 level : Vhh, Vl) 


20 


Vhh 


— 


Power supply (20V) 



442 



SONY. 



CXD1250M 



Truth Table 












Input 


Output 


XVI «3 


XSG1 • 2 


XV2»4 


XSub 


V$ 1 »3 


V<t>2»4 


VSub 


L 


H 


X 


X 


Vm 


X 


X 


H 


H 


X 


X 


Vl 


X 


X 


X 


X 


L 


X 


X 


Vm 


X 


X 


X 


H 


X 


X 


Vl 


X 


X 


X 


X 


L 


X 


X 


Vhh 


X 


X 


X 


H 


X 


X 


Vl 


L 


L 


H 


X 


Vh 


Vl 


X 


H 


L 


X 


X 


z 


X 


X 



X : Don't Care 

Z : High Impedance 



DC Characteristics (Ta = 25°C) 



Item 


Symbol 


Test condition 


Min. 


Typ. 


Max. 


Unit 




Power supply 


"H" level input voltage 


VlH 




Vdd = 5 
Vl = ~10 
Vm = 
Vh=15 
Vhh = 20 


3.5 








V 


"L" level input voltage 


VlL 










1.5 


V 


"L" level output voltage 


V*L 


I ♦ l = 20 u A 





-10 


-9.9 


V 


"M" level output voltage 


V*M 


1 ♦ m = - 20 u A 





0.0 


0.1 


V 


"M" level output voltage 


V*M 


1 ♦ M = 20 u A 


-0.1 


0.0 





V 


"H" level output voltage 


V»H 


1 + h = - 20 U A 


14.9 


15 





V 


"HH" level output voltage 


V +HH 


1 + HH = - 20 u A 


19.9 


20 





V 


Input current 


li 







1.0 





uA 


Power supply current* 


Im 







4.5 


5.0 


mA 


Power supply current* 


Idd 







0.3 


0.5 


mA 


Power supply current* 


Ih 







0.1 


0.2 


mA 


Power supply current* 


Ihh 







0.05 


0.1 


mA 



I 



♦ Supply current at operation (See the Test Circuit) 



-443 



SONY* 



CXD1250M 



Switching Characteristics 

(See the Test Circuit Ta = 25 °C, Vhh = 20V, Vh = 1 5V. Vm = OV. Vl = - 1 0V, Vdd = 5V) 



Item 


Symbol 


Conditions 


Max. 


Min. 


Unit 


Output current 


lL 


V * 1 to 4 = - 9.5V 


-25 




mA 


Output current 


lM1 


V <fr 1 to 4 = - 0.5V 




10 


mA 


Output current 


lM2 


V4> 1, 3 = 0.5V 


-9 




mA 


Output current 


IH 


V<H, 3= 14.5V 




12 


mA 


Output current 


ISL 


VSub = - 9.5V 


-12 




mA 


Output current 


ISH 


VSub = - 19.5V 




7 


mA 


Rise time Vl-»Vm 


Ttlm 


V <J> 1 to 4 = - 0.5V After input transient 


1000 




ns 


Fall time Vm— Vl 


Ttml 


V 4> 1, 3 = -9.5V After input transient 


500 




ns 


Rise time Vm-»Vh 


Ttmh 


V 4> 1, 3= 14V After input transient 


1000 




ns 


Fall time Vh-*Vm 


Tthm 


V $ 1, 3= 1V After input transient 


1000 




ns 


Rise time Vl-»Vhh 


Ttlhh 


VSub = 1 7V After input transient 


200 




ns 


Fall time Vhh-*Vl 


Tthhl 


VSub = - 7V After input transient 


200 




ns 


Coupling amplitude (middle level) 


VCOM 


V <t> 1 to 4 


0.5 




V 


Coupling amplitude (low level) 


VCOL 


V 4> 1 to 4 


0.5 




V 



Input Waveform 

(Repeat Cycle 15.7kHz) 



Output Waveform 




444 



SONY. 



CXD1250M 



Input waveform 



Output waveform 



V01 




Ttmh-«( k- -H («-Tthm 

! i i ! 



r\ 



mm n 



V03 



n 



i 
i 

I Ttlhh I Tthhl 



I 



-445- 



SONY® 



CXD1250M 



Test Circuit 



SOOpF 

in 




r®-©— ©— ©— ®— 4— ®— ®— &— (3h 



Timing generator 
(CXD1156Q) 



8)— (9)— Q0> 




Ri ; 27n 
Rz ; 5n 
Ci ; 1500pF 
C2 ;3300pF 



Application Circuit 



ICX026/027 



V04 Q 
V«3 (2 



V01 © 
V02 ® 



Sub ©- 



1^1/ 35 

— ie- 



CXD1250M 



CXD1156Q 




Refer to the Caution : Rise in power supply 



-446- 



SONY* 



CXD1250M 



Caution : Rise in Power Supply 

When the substrate driver is in use, be careful not to let the CCD imager (ICX026/027) Sub 
(pin 4) turn into negative voltage. 

To this end, raise the - 10V and +20V supplies at the application circuit under the following 
conditions. 




t2 > ti ^ 1 0ms 



I 



447- 



Signal Processing IC 
for Video Camera 




5) Signal Processing IC for Video Camera 



Type 



CXA1310AQ 



CX20053 



CX20055 



CX20056 



CX20151 



CX23039 



CXA1337Q-Z/R 



CXA1338Q-Z/R 



CXA1339Q-Z/R 



CXA1072Q-Z/R 



CXL1503M 
CXL1505M 



CXL1504M 



CXA1270N 



CX20095A 
CX20186 



Application 



Monochrome camera 



Sample hold 



Encoder 



Auto iris, auto white 
balance 



Matrix 



1H delay line x 4 



Sample hold 



Signal processing 



Matrix 



Encoder 



For matrix 1H delay 

line 

Signal Processing 



Luminous 
delay line 



signal 1H 



Vertical outline com- 
pensation 



Video output 



Function 



Single Chip Processing for CCD Mono- 
chrome camera 



CDS, color separation, color mix correc- 
tion, y correction, blanking, white clip, 
pedestal setting ___ 



Aperture correction, blank cleaning, 
white clip, chroma mod, fader, finder, 
switcher, 75Q driver 



Iris drive, RB line seq. signal separation, 
auto white balance, low light alarm 



Color differential, signal forming, 
luminance signal forming, multiplexer 



1H delay line X 4, S/H, delay line driver 



CDS.AGC, Color separation, chroma sup- 
press 



From color compensation (Mg, G, Cy, 
Ye) interleave coding, R, G, B sythetic 
and Y signal processing 



Matrix, white balance, y correction, 
negative/positive inversion 



Aperture, auto-corrier balance, 
negative-positive reverse, fader, chroma 
suppression, BLK cleaning 



1H CMOS-CCD delay line x 4 



1H CMOS-CCD delay line 



Signal generation during, Vertical Out- 
line Compensation 



6dB amp, video driver, bilateral video 
driver 



Page 



451 



465 



484 



503 



521 



546 



559 



577 



598 



616 



640 



648 



656 



664 



450- 



SONY. 



CXA1 31 OAQ 



Single Chip Processing for CCD Monochrome Camera 



Description 

The CXA1310AQ is designed to perform the 
basic signal processing in CCD monochrome 
cameras through a single chip. This bipolar IC 
is most suitable for compact usage and low 
power consumption. 

Features 

• Processing from CCD output to 75 Q video 
output with a single chip 

• Wide variable AGC (4 to 32dB Typ.) 

• Built-in operational amplifier for AGC loop 

• 75 Q line capacitance minimized using sag 
compensation function 

• Variable white clip level realize wide dynamic 
range (MOIRE) 




Structure 

Bipolar silicon monolithic IC 



Applications 

CCD monochrome camera 

Absolute Maximum Ratings (Ta = 25 e C) 

• Supply voltage Vcc 7 V 

• Storage voltage Tstg - 65 to + 1 50 °C 

• Operating temperature Topr - 20 to + 75 *C 

• Allowable power dissipation Pd 500 mW 



Operating Conditions 

Supply voltage 



Vcc 



4.75 to 5.25 



Block Diagram and Pin Configuration 



CLP2 SHP SHOI SH02 AGCMAX AOCCONT AGCOUT 'IN >CLP OPOUT 





RISCLP LINEAR rOOT DRIVER IN WCCONT SETCONT S TNC CLP1 BLK 



E89910-ST 



-451 



SONY® 



CXA1310AQ 



Pin Description 



No. 



Symbol 



SAG 



GND2 



I/O signal 



Inputs VIDEO OUT 
through capacitor 



'GND 



Equivalent circuit 



a 150ft 



ison — f-^^ 



:iok 



:6K 



MOQpA 



777 



m 



Description 



Input pin of sag 
compensation signal 



GND for driver and 
IRIS 



GND1 



GND 



GND for other than 
driver and sample 
hold and IRIS 



SYNC 



inr 



HI : 4.5V and above 
LO : 0.5V and below 
T : 5 us 



20)1 A 




Sync pulse input pin 
(active at LO) 



: GND 



SET CONT 



*2 to 3.5V 



'Vcc 




Set up level 
adjusting pin 



Turns to preset 
mode 1 



Control mode 



Turns to preset 
mode 2 



WC CONT 



= GND 



*2 to 3.5V 



150ft 



0-— A/W 




White clip level 
adjusting pin 



40pA 



Preset mode 



Control mode 



♦External applied voltage 



-452- 



SONY® 



CXA1310AQ 



No. 



Symbol 



I/O signal 



Equivalent circuit 



Description 



DRIVER IN 



Inputs y OUT 
through capacitor or 
LINEAR 




Input pin to driver 



y OUT 



DC 2V 




JfT% 



Gamma 

compensation signal 
output pin. 
Outputs y 1 when 
Pin 9 at OPEN 
outputs y 2 when 
Pin 9 turned to 5V 



LINEAR 



DC 1.8V 



* Vcc 




Linear signal (y-OFF 
signal) output pin 



Pin 8 output signal 
turns to y 2 output 



10 



y CLP 




Capacitor connecting 
pin for gamma input 
clamp 



♦External applied voltage 



453- 



SONY® 



CXA1310AQ 



No. 



Symbol 



11 



y IN 



12 



AGC OUT 



I/O signal 



Input DC permissible 

range 

*DC2 to 3V 



Vpp MAX 1300mV 
Vpp TYP 500mV 
DC 2.55V 



Equivalent circuit 




13 



DET OUT 



MAX 1 500mV 
TYP 500mV 
DC 2V 




700pA 



"© 



frr 



(J) 



320pA 



"© 



14 



AGC MAX 



15 



Vcci 



*DC 



*5V 




20>jA 



Description 



Input pin of the 
gamma 
compensation circuit 



Output pin of signal 
passed through AGC 



Output pin of AGC 
detection signal 



Maximum gain 
setting pin of AGC 
amplifier 



Power supply for 
other than driver 
and IRIS 



♦External applied voltage 



-454 



SONY® 



CXA1310AQ 



No. Symbol 



I/O signal 



Equivalent circuit 



Description 



16 



AGC CONT 



DC 




Gain control pin of 
AGC amplifier 



120jjA 



17 



OP OUT 




<Ki7) 



Output pin of the 
operational amplifier 



777 



18 



OP IN 



@- 



ison 

-Wr- 



ln verted input pin of 
the operational 
amplifier 



20>jA 



rn 



19 



OP IN + 




20pA 



Non inverted input 
pin of the 
operational amplifier 
(AGC detection 
signal input pin) 



I 



♦External applied voltage 



455 



SONY® 



CXA1310AQ 



No. 



Symbol 



I/O signal 



20 



SHD2 



HI : 
LO 

T : 



_n tl 

4.5V and above 
0.5V and below 
15ns and 
above 



21 



SHD1 



22 



DATA 



23 



PG 



HI : 
LO 
T : 



4.5V and above 
0.5V and below 
15ns and 
above 



© 



Equivalent circuit 




150H 



H-MOOjjA 

1? 



777 



©MAX 800m V 
©MAX 800m V 



© 



©MAX 800mV 
©MAX 800mV 




Description 



Input pin of the 
sample hold pulse 
(active at HI) 



Input pin of the 
sample hold pulse 
(active at HI) 



CCD signal input pin 




777 777 



CCD signal input pin 



♦External applied voltage 



456 



SONY® 



CXA1310AQ 



No. Symbol 



I/O signal 



Equivalent circuit 



Description 



24 



SHP 



_n n_ 



HI : 4.5V and above 
LO : 0.5V and below 
T: 15ns 




Input pin of the 
sample hold pulse 
(active at HI) 



25 



CLP2 



_n n_ 



HI : 4.5V and above 
LO : 0.5V and below 
T: 2 us 



50*1 A 



@— ^WV f ^3 



rrr 



rrr 



CLP2 pulse input 

pin 

(active at HI) 



26 



GND3 



= GND 



Sample hold GND 



27 



^ 



IRIS 



DC 1.3V 



(±> 



320>jA 

777 



Output pin of the 
IRIS control signal 



rrr 



28 



i < 



IRIS CLP 




Capacitor connecting 
pin for IRIS output 
clamp 



♦External applied voltage 



457 



SONY® 



CXA1310AQ 



No. 



Symbol 



I/O signal 



Equivalent circuit 



Description 



29 



BLK 



Tl LT 



HI : 4.5V and above 
LO : 0.5V and below 
T : 1 1 us 



150X1 ^J ^, 



BLK pulse input pin 
(active at LO) 



rrr 



rrt 



30 



CLP1 



_n n_ 



HI : 4.5V and above 
LO : 0.5V and below 
T: 2 ms 



'50>jA 



ison 




777 



CLP1 pulse input 

pin 

(active at HI) 



31 



Vcc2 



5V 



Driver and IRIS 
power supply 



32 



VIDEO 




V 



BLK level 
1.5V 




<>-Q32 



777 



VIDEO signal output 
pin 



* External applied voltage 



458 



SONY® 



CXA1310AQ 



Electrical Characteristics (Ta = 25t, Vcc = 5V, See Electrical Characteristics Test Circuit) 



No. 


Item J 


Symbol 


Conditions 


Min. 


Typ. 


Max. 


Unit 


1 


Current consumption 


Ice 


Current value of Vcd and Vcc2 
AGC CONT = 1 .5V 


30 


45 


60 


mA 


2 


Min. value of AGC 
MAX 


MAX 


GAIN between DATA input and AGC OUT 
DATA input = 100mV 
AGC MAX = 4V, AGC CONT = 1 .5V 




18 


20 


dB 


3 


Min. value of AGC 
CONT 


AG1 


GAIN between DATA input and AGC OUT 
DATA input = 500mV, AGC CONT = 5V 




4 


6 


dB 


4 


Max. value of AGC 
CONT 


AG2 


GAIN between DATA input and AGC OUT 
DATA input = 30m V, AGC CONT = 1 .5V 


30 


32 




dB 


5 


AGC CONT 10dB 


AG3 


GAIN between DATA input and AGC OUT 
DATA input = 320mV. AGC CONT = 3.55V 


8 


10 


12 


dB 


6 


AGC OUT DC 


ADC 


DC output level of AGC OUT 


2.25 


2.55 


2.85 


V 


7 


Y 1 output level 


Y1 


Test value of y 1 output level 
Y IN input = 500mV 


530 


630 


730 


mV 


8 


y 2 output level 


Y2 


Test value of y 2 output level 
Y IN input = 500mV, S9 ON 


580 


680 


780 


mV 


9 


LINEAR AMP GAIN 


LG 


GAIN between y IN input and LINEAR 
Y IN input = 500mV 


1.6 


2.6 


3.6 


dB 


10 


DET OUT DC 


DDC 


DC output level of DET OUT 


1.8 


2.0 


2.2 


V 


11 


IRIS AMP GAIN 


IG 


GAIN between DATA input and IRIS 
DATA input = 300mV 


8 


10 


12 


dB 


12 


IRIS OUT DC 


IDC 


DC output level of IRIS 


1.1 


1.3 


1.5 


V 


13 


DRIVER GAIN 


DG 


GAIN between DRIVER IN and VIDEO 
DRIVER IN = 700mV 


5.7 


6.0 


6.3 


dB 


14 


SYNC level 


SY 


SYNC level/DG* of VIDEO output 


270 


293 


316 


mV 


15 


SET UP 1 


SE1 


SET UP level of preset mode 1 
SET UP level/DG* of VIDEO output 


-15 





15 


mV 


16 


SET UP 2 


SE2 


SET UP level of preset mode 2 
SET UP level/DG* of VIDEO output 





20 


40 


mV 


17 


Min. value of SET 
CONT 


SE3 


SET UP level/DG* of VIDEO output 
SET CONT = 2V 




-3 


15 


mV 


18 


Max. value of SET 
CONT 


SE4 


SET UP level/DG* of VIDEO output 
SET CONT = 3.3V 


80 


130 




mV 


19 


W-CLIP level 


WC1 


W-CLIP level/DG* of VIDEO output 
DRIVER IN = 1 500mV, WC CONT = GND 


780 


820 


860 


mV 


20 


Min. value of WC 
CONT 


WC2 


W-CLIP level/DG* of VIDEO output 
DRIVER IN = 1 500mV, WC CONT = 2.2V 




300 


600 


mV 


21 


Max. value of WC 
CONT 


WC3 


W-CLIP level/DG* of VIDEO output 
DRIVER IN = 1 500mV, WC CONT = 3.3V 


1000 


1300 




mV 


22 


OP AMP output D 
range Low level 


OPL 


DC output level of OP OUT 
OP IN + = 2.5V, OP IN - = 4V 




0.8 


1.2 


V 


23 


OP AMP output D 
range High level 


OPH 


DC output level of OP OUT 
OP IN + = 4V, OP IN - = 2.5V 


4.5 


4.8 




V 



I 



♦Characteristics value at DRIVER GAIN item 



-459 



SONY® 



CXA1310AQ 



Electrical Characteristics Test Circuit 



JJJ JJJ JJJ 



^ (jj) (25) CLP2 

^ (26) GND3 



0-5 
£AGCCONT ft 6) ^ffc; fc'SV) 



VCC1 (15) — CA) — | »-£ 
AGCMAX (14) ^k £(OV) 




=H h® ^ VCC2 

^ (32) VIDEO ™ 



Note) 

• mF is the capacitance unit of the capacitor. 

• For Pins 5, 6, 14 and 16, apply voltage in brackets unless otherwise specified in the conditions 
column of the Electrical Characteristics. 

• ® indicates a test pin. (Test AC, DC voltage) 

• For Pins 7, 1 1 and 22, the input signal level is at OmV, unless otherwise specified in the 
conditions column of the Electrical Characteristics. 



460 



SONY® 



CXA1310AQ 



Test Circuit I/O Waveform Diagram 

Input pin 



22. DATA 
11. yIN 



7. DRIVER IN 



4. 57NC 



29. BLK 



30. CLP1 



25. CLP2 



Output pin 

12. AGC OUT 

8. y1.2 OUT 

9. LINEAR 
13. DET OUT 



27. IRIS 



32. VIDEO 



2.4V 



2.5V 



Input waveform 

Input level 

:: 



T 



Input level 



2.7V 



Input level 



5V 
OV 



5 MS 



5V 

OV 
5V 
OV 



15 MS-! 



50 m s 



2 MS 

i- 



5V 
0\T 



IT 



2 MS 



Output waveform 



Test 



Test 



Test 



Test 



Test 



Test 



I 



SYNC level 



461 



SONY® 



CXA1310AQ 



Application Circuit 



12200 



=Hh =HH 



47P 




IRIS 4— 

cont" 



IOjiF 



\1/ 

75ft OUT 



HI— fe 

L47P 



2200- 



X 



2200 
-WS/ 1 



SG 



* 1 . Use a high Ft transistor. 

(2SC3355) 
*2. Use a FET similar to 2SK152 or 

2SK300. 



462- 



SONY® 



CXA1310AQ 



Representative Characteristics (Vcc = 5V, Ta = 25°C) 
AGC control characteristics 















































40 






















































fi 30 






















z 






















S 20 












































10 













































) 1 2 3 4 

AGC CONT (V) 

White clip control characteristics 



1000 

> 

tk 800 

§ 

Si 

Q. 

w 600 



400 



1 
/ 


£ 


r 


Preset / 


T 


t 


f 


i 


z 





1 2 3 

WC CONT (V) 









r 1 1/O characteristics 


































1000 


















































5 

E 




















































> 
2 


























& 500 

3 
O 


















































- 











































































































AGC MAX control characteristics 
















































40 












































Sf 30 

DO 






















z 

< 20 
































































10 













































12 3 4 

AGC MAX (V) 

Set up control characteristics 



100 



50 































I 




















/ 




















/ 




















/ 






































/ 




















/ 






Preset 










/ 












I 

= 


'res< 

4— 


5t 

J 

















1 2 3 

SET CONT (V) 









r 2 I/O characteristics 


































1000 


















































> 

E 




















































> 
Si 


























3 

& 500 
o 


















































Csl 


























































































| 













I 



500 1000 

y IN input level (mV) 



500 1000 

y IN input level (mV) 



-463 



SONY® 



Package Outline Unit : mm 



32 pin QFP (Plastic) 0.2g 



D9.0* - 2 



Em 



EEC 

cm 
Em 



32 



7.0-0.1 



BhhhhhhH 




o 



IT 



1.5-0.15 



ZED 
ZED 

zed 

ZED 
ZED 
ZED 
ZEED9 



mm 

$.8 o.3 - 8:i B 



i 



£ 



nei±o.i2i®i 




0° -10' 



SONY NAME 


QFP-32P-L01 


EIAJ NAME 


•QFP032-P-0707-A 


JEOEC CODE 







464 



SQ1STY. 

Signal Processing for Color Camera 



CX20053 



Description 

CX20053 is a bipolar IC which has been developed as 
a processor of color-difference line alternating color camera 
and it is comprised of correlated double sampling, AGC, 
color separation S/H, color mixing correction, white balance, 
clamping, y correction, blanking, white clipping, pedestal 
setting, etc. circuits. It processes various kinds of signals 
and forms G signal which has been y corrected, and R and 
B lines alternating signals. 

Features 

• It can compose a consistent color camera signal 
processing system, together with the CX20054, 
CX20055 and CX20056. 

• By adopting correlated double sample and hold, 
reduction of noises in low frequency bands and leakage 
of S/H pulses can be achieved. 

Block Diagram 





IN @-L-S/H 



^L^rj 




(26) G Cont 
(zt) R Cont 
(28) B Cont 



(3l) RB T 



-*{29) OCT 



E89661 - ST 



465 



SONY® 



CX20053 



Structure 

Bipolar silicon monolithic IC 

Absolute Maximum Ratings (Ta=25°C) 

• Power supply voltage Vcc to 4 

• Operating temperature Topr 

• Storage temperature Tstg 

• Allowable power dissipation Pd 
Input Pin Maximum Voltage 



10 


V 


-10 to +60 


°C 


-55 to +150 


°C 


833 


mW 



Operation Power Supply Voltage Range 

Vcd, Vcc2 8.5 ± 0.2 V 

Vcc3, Vcc4 5.0 + 0.15 V 

Pulse Input Level 



Pin No. 


Voltage) V) 


Pin No. 


Voltage) V) 


Pin No. 


Voltage(V) 


2 


^Vcd ,2 


20 


^Vcc1,2 


38 


^Vcd ,2 


3 


^Vcd ,2 


21 


^Vcd ,2 


39 


^Vcc3,4 


7 


^Vcd ,2 


22 


^Vcd ,2 


40 


^Vcc3,4 


10 


^Vcd ,2 


23 


^Vcc3,4 


41 


^Vcc3,4 


11 


^Vcc3,4 


24 


^Vcc3,4 


42 


^Vcc3,4 


12 


^Vcc3,4 


25 


^Vcc3,4 


44 


^Vcc3,4 


13 


^Vcc3,4 


26 


^Vcc3,4 


45 


^Vcc3,4 


15 


^ Vcc 1,2 


27 


^Vcc3,4 


47 


^Vcc1,2 


18 


^ Vcc 1,2 


28 


^Vcc3,4 






Output Pin Maximum Applied Voltage 


Pin No. 


Voltage) V) 


Pin No. 


Voltage(V) 


Pin No. 


Voltage(V) 


1 


^Vcd ,2 


16 


^Vcc1,2 


32 


^Vcd ,2 


4 


^Vcd ,2 


17 


^Vcc1,2 


33 


^Vcd ,2 


6 


^Vcd ,2 


29 


^Vcc3,4 


34 


^Vcd ,2 


8 


^Vcd ,2 


30 


^Vcc3,4 


35 


^Vcd ,2 


9 


^Vcd ,2 


31 


^Vcc3,4 


36 


^Vcd ,2 



Pin No. 


Input level 


38 


CMOS level 


39 


CMOS level 


40 


CMOS level 


41 


CMOS level 


42 


CMOS level 


44 


CMOS level 


45 


CMOS level 



CMOS Level 






Min. 


Max. 


Unit 


Vh 4.0 


5.0 


V 


Vl 


0.4 


V 



Allowable value of clamping pulse width 
1 .96 ju.sec ± 1 0% 

Provided that it is APL 10 to 90% by 
using stair step. 



-466- 



SONY® 



CX20053 



Pin Description 



No. 


Symbol 


I/O 


Description 


1 


X2 





Output of input signal which is sampled and hold with SHP pulse (together 
with externally attached capacitor). 


2 


Y2 


I 


Input in order to further sample and hold with SHD pulse (together with 
externally attached capacitor) to be phase matched the output of X2 to that of 
X1. 


3 


Y3 


I 


Another input of input signal which is sampled and hold to be fed to 
differential operation stage. 


4 


X3 





Output of Y2 


5 


Vcc4 




Power supply (5V) for control pins 


6 


X1 





Output which is an input signal that is SHD sampled and hold (together with 
externally attached capacitor). 


7 


Y1 


I 


Another input of input signal which has been sampled and hold together with 
Y3 to be differential operation stage. 


8 


Iris Det 





Output to be fed to CX20056, and it is an input signal which has been 
sampled and hold and whose gain is raised approximately 3 times. 


9 


AGC Det 





Output of AGC which changes its gain in response to input signal and the 
output to be fed to CX20056. 


10 


AGC Cont 


I 


An input of control voltage from CX20056 which corresponds to the input 
signal, and it controls AGC gain. 


11 


Max Gain 


I 


An input which controls maximum gain of control. 


12 


B Gain 


I 


Among the input signals, it controls gain of B signal. 


13 


R Gain 


I 


Among the input signals, it controls gain of R signal. 


14 


Vcd 




Power supply voltage (8.5V) which is supplied to the first half of signals flow; 
namely, input signal, color separation sample and hold signal, etc. 


15 


GY 


I 


Signal input from the GX through coupling capacitor. 


16 


GX 





G component output among input signals which is obtained by color 
separation sample and hold with SP1 pulse from input signal passing through 
AGC circuit. 


17 


RBX 





RB component output among input signals obtained by color separation 
sample and hold with SP2 pulse from input signal passing through AGC 
circuit. 


18 


RBY 


I 


A signal input of RBX passing through coupling capacitor. 


19 


GND2 




Grounding of Vcc2 and Vcc4. 


20 


MIX 


I 


Color mixing channel control pin of imagepicked up element. Color mixing to 
G of RB is controlled by it. 


21 


Rofst 


I 


Offset control pin of clamped R signal, and it performs matching into G 
channels (y). 


22 


Bofst 


I 


Offset control pin of clamped B signal, and it performs matching into G 
channel (y). 


23 


y 


I 


It controls y correction from clamped G and RB signals. 


24 


WC 


I 


It controls WC level from y curves of Gy and RBy. 


25 


PED 


I 


It controls pedestals of y corrected signals. 


26 


G Cont 


I 


It controls gain of G signal which has been color separated and clamped. 



I 



467 



SONY® 



CX20053 



No. 


Symbol 


I/O 


Description 


27 


R Cont 


I 


Control voltage (R channel) input for WB from WB(White Balance) IC. 


28 


B Cont 


I 


Control voltage (B channel) input for WB from WB IC. 


29 


DCy 





DC level output of pedestal. 


30 


Gy 





G component of y corrected signal output. 


31 


RBy 





RB component of y corrected signal output. 


32 


G Det 





G component output for CX20056 in order to maintain WB. 


33 


RB Det 





RB component for CX20056 in order to maintain WB. 


34 


CB 





Output which holds black level of B signal whose gain becomes variable after 
it has been color separated and passed through WB amplifier. 


35 


CR 





Output which holds black level of R signal whose gain becomes variable after 
it has been color separated and passed through WB amplifier. 


36 


CG 





Output which holds black level of G signal whose gain becomes variable after 
it has been color separated and passed through WB amplifier. 


37 


Vcc2 




Power supply voltage (8.5V) which allows the latter half of signal flow against 
Vcd. 


38 


HBLK 


1 


Blanking pulse input. 


39 


ID 


1 


ID pulse input which switches over R signal and B signal. 


40 


CLP 


1 


Clamping pulse input. 


41 


SP1 


1 


Sample and holding pulse input in order to carry out color separation of G 
component. 


42 


SP2 


1 


Sample and holding pulse input in order to carry out color separation of RB 
component. 


43 


GND3 




Grounding of Vcc3. 


44 


SHD 


1 


Another input of sample and hold pulse in order to sample and hold the input 
signal. 


45 


SHP 


1 


Another input of sample and hold pulse in order to sample and hold the input 
signal. 


46 


Vcc3 




Power supply voltage (5.0V) of pulse system (ECL). 


47 


IN 


1 


Input of imager 


48 


GND1 




Grounding of Vcd . 



-468 



SONY® 



CX20053 



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CX20053 



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SONY® 



CX20053 













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471 



SONY® 



CX20053 



Electrical Characteristics Test Circuit 




Tr: 2SC403 

FET: Corresponds to 2SK43 



-472- 



SONY® 



CX20053 



Input and Output Waveform Diagram 



10n 2m 10n 

H ,| U A l « 61 .5m 



2m 



63.5m 



2m 



63.5m- 



10m- 
10n 10n 



P3 (CMOS level) 



P2 (CMOS level) 



P1 (CMOS level) 




10n ion 

-1M 



-2m- 



10n 15n 10n 



■1M 



10n 15n 10n 



-2m- 



P5 (CMOS level) 



P4 (CMOS level) 



I 



473- 



SONY® 



CX20053 



Standard Pin Voltage (DC) (When standard bias is applied) 

Unit: V See the measuring circuit diagram During non-signal 



Pin No. 


Pin voltage 


Pin No. 


Pin voltage 


Pin No. 


Pin voltage 


1 


5.20 


17 


6.97 


33 


4.38 


2 


* 1 (7.1) 


18 


6.07 


34 


5.46 


3 


3.69 


19 


"'(O.GND) 


35 


5.46 


4 


5.19 


20 


* 1 (2.50) 


36 


5.48 


5 


' 1 (5.0, Vcc4) 


21 


* 1 (2.53) 


37 


* 1 (8.5, Vcc2) 


6 


5.20 


22 


* 1 (2.53) 


38 


* 2 (5.0, HBLK) 


7 


3.69 


23 


* 1 (2.39) 


39 


* 2 (5.0, ID) 


8 


4.19 


24 


* 1 (2.43) 


40 


* 2 (5.0, CLP) 


9 


4.20 


25 


* 1 (2.06) 


41 


* 2 (5.0, SP1) 


10 


* 1 (2.68) 


26 


* 1 (2.65) 


42 


* 2 (5.0, SP2) 


11 


* 1 (2.54) 


27 


* 1 (2.44) 


43 


* 1 (0, GND) 


12 


* 1 (2.50) 


28 


* 1 (2.46) 


44 


* 2 (5.0, SHD) 


13 


'^.SO) 


29 


2.32 


45 


* 2 (5.0, SHP) 


14 


* 1 (8.5, Vcd) 


30 


2.37 


46 


* 1 (5.0, Vcc3) 


15 


6.07 


31 


2.37 


47 


* 1 (7.1) 


16 


6.87 


32 


4.37 


48 


* 1 (0, GND) 



*1. Numerals in the parentheses show externally applied values. 

*2. It is a pulse input pin; however, the numerals represent the value externally applied as 
pulse ON. 



-474- 



SONY® 



CX20053 



Application Circuit 




I 



-475 - 



SONY® 



CX20053 



Standard Operating Characteristics (Ta=25°C) and Temperature Characteristics 
Test conditions 



SW condition 


Bias condition 


1 


2 3 


4 


5 


6 


7 


8 


9 


10 


E1 


E2 


E3 


E4 


E5 


E6 


E7 


E8 


E9 


E10 


E11 


E12 


E13 


b 


b | a 


a 


a 


a 


a 


a 


a 


a 





























[1] AGC amplifier output characteristics (Fig. 1) 

When E1 =4V with S=S3=50 mVp-p, adjust E2 so that V5 becomes 300 mVp-p. An output voltage of pin @ 
when E1 1 is varied from to 4V under the above-mentioned condition. 

[2] G control characteristics (Fig. 2) 

An output voltage of pin @ set to S=S3=300 mVp-p, when E1 1 is varied from to 4V. 

[3] B or R control characteristics (Fig. 3) 

An output voltage of pin @ set to S=S3=300 mVp-p, when E1 2 and E1 3 are varied from to 4V. Provided that 
E3 and E4 are fixed to 1V. 

[4] B or R gain characteristics (Fig. 4) 

An output voltage of pin @J set to S=S3=300 mVp-p, when E3 and E4 are varied to to 4V. Provided that 
E12=E13 is fixed to 1 V. 

[5] y and knee characteristics (Fig. 5) 

After the outputs of pins @) and @ become 250 mV set at S=S3, adjust by changing y adjustment terminal 
voltage of pin @ so that R/By and Gy outputs become 500 mV (without including pedestal amount). Then set 
the outputs of pins @) and @) so that they become 750 mV, and adjust WC pin voltage of pin @) so that 
R/By and Gy outputs become 570 mV. Then, measure the y and knee curves. 

[6] Output variation of AGC amplifier due to the power supply voltage fluctuation (Fig. 6) 

Output variation of AGC amplifier due to supply voltage fluctuation when set to S=S3=1 50 mV, and when the E1 
is adjusted so that the output of pin @ becomes 300 mV. 
(Max gain = ST) 

[7] Power supply voltage fluctuation characteristics of y output (Fig. 7) 

Power supply voltage dependability of the output voltage difference between R/By and Gy after adjustment 
similar to that stated in [5] has been performed. (R/By and Gy output = 500 mVp-p) 

[8] Temperature characteristics of AGC amplifier (Fig. 8) 

Temperature variation of GX pin output when set to S=S3= 1 50 mV, and E1 is so adjusted that the output of pin 
© becomes 303 mV (Ta=25°C) (Set that Max G = ST) 

[9] y temperature characteristics (Fig. 9) 

Temperature variation of Gy output after the adjustment similar to that stated in [5] has been performed. 

[10] Pedestal temperature characteristics (Fig. 11) 

Set the outputs of Gy and R/By to 500 mVp-p after the adjustment similar to that stated in [5] has been performed. 
Adjust G pedestal to 25 mV (Ta=25°C) with E1 0. Then adjust B offset and R offset with E7 and E6 so that R and B 
pedestal of pin @ become identical with G pedestal and then observe the temperature variation of R, G and B 
pedestals. 



476- 



SONY® CX20053 



[11]AGC output voltage obtained by parameterizing AGC control voltage and Max gain voltage (Fig. 12) 

The output voltage of AGC DET pin ® is measured by inputting S=S3=50 mV and using AGC control voltage 
and Max gain voltage as a parameter, and thus the gain is calculated. 

[12] Pedestal amount of G and R/By output sections vs Pedestal adjustment voltage (Fig. 13) 

The pedestal amount when E1 is varied by adjusting R and B offsets by adjusting E5 and E6 after the adjustment 
similar to that stated in [5] has been performed. 

[13]R/B offset variable amount vs Offset regulation voltage (Fig. 14) 

After performing similar adjustment as stated in [5], adjust E10 so that the pedestal amount of Gy becomes 
70 mV. Then, the pedestal amount at R/By section is measured with offset which becomes variable by adjusting 
E5 and E6, and thus the difference between the pedestal amount of Gy and that of R/By is obtained. 



-477- 



SONY® 



CX20053 



AGC characteristics 



G control characteristics 

























400 










































300 


































f 








200 
































| 










100 












/ 




















/ 




















*s 























O 20° 



























































































































































(GY=300mVp-p) 











































AGC Cont. Vol (V) 
Fig. 1 



G Cont Vol (V) 
Fig. 2 



B or R Cont characteristics 



B or R gain chracteristics 





(RBY=300mVp-p) 




















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Fig. 4 



y characteristics 






1000 

RB Detx2 or G Detx2 (mVp-p) 
Fig. 5 



AGC amplifier power supply voltage 
fluctuation characteristics 

































































, 


i/l 


Q. 




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Vcc4 = 5.2V 



Vcc4= 5.1V 

/Vcc4 = 5.0V 

■^Vcc4 = 4.9V 



,83 8.4 85 8.6 8.7 

Vcc1 [V] 

Fig. 6 



-478 



SONY® 



CX20053 



y output power supply voltage 
fluctuation characteristics 



AGC temperature characteristics 



1_ J^- 1\* x ycc 4 = 48V 




Vcc4 = 4.9 V 

i 

Vcc4 = 5.0V 

I 

Vcc4 = 5.2V 

Vcc4 = 5.1V 



8.3 8.4 8.5 8.6 87 

Vcc1 [V] 

Fig. 7 

y temperature characteristics 



520 










































510 
















































Q. 
> 500 

a 

490 


















































































480 











































Ambient temperature [°C] (Standard setting) 
Fig. 9 

Total pedestal (G pedestal) temperature characteristics 



ImV) 




320 










































310 

"a 










































> 


































X 

290 










































































































- 


20 





2 





4 





■ f 


.0 





Ambient temperature [°C] (Standard setting) 
Fig. 8 

Maximum allowable dissipation decreaseing curve 





0.8 
0.6 
0.4 
0.2 























? 






























Q 

0- 

c 
g 










































Q. 










V 












i 

o 
a. 










\ 

































3 

I 
o 































































Ambient temperature [°C] 

Fig. 10 

R offset (R pedestal) temperature characteristics 





60 
40 
20 


































































> 






















« 






















o 



































































Ambient temperature [°C1 



Ambient temperature [°C] 



479- 



SONY® 



CX20053 



B offset (B pedestal) temperature characteristics 



AGC control voltage and Max gain voltage 
vs AGC amplifier amplification degree 





' 


v 


















60 




\ 






































> 

E 

— 40 
% 










































O 

m 20 


































































Ambient temperature [°C] 
Fig. 1 1 



























Max G 


ain v 
2.9V 
2 8V 






















/ 




































1 






















V 








1 

?7V 






























| 






























2.6 V 




































1 
2.5V 
2.4V 
2.3V 
2.2V 



























































































































































































































2.4 2.6 2.8 3.0 

AGC control voltage (V) 
Fig. 12 



Pedestal amount of G and R/Br output section 
vs Pedestal adjustable voltage 



R/B offset variable amount vs Offset adjustable voltage 





























200 


















































150 


















































100 


















































50 













































































1.96 2.02 2.08 2.14 220 

Pedestal adjustable voltage (V) 

Fig. 13 




2.48 2.50 2.52 2.54 

Offset adjustable voltage (V) 
Fig. 14 



480 



SONY® 



CX20053 



Pin 


DC [V] 


AC[V] 


Imp. [ft] 


Remark 


1 






<100 


Accept with FET 


2 


6.9 




>100k 




3 


3.7 




>7k 




4 


5.0 




<100 


Accept with FET 


5 


5.0 






Vcc4 


6 


4.6 




<100 


Accept with FET 


7 


3.7 




>7k 




8 


4.2 


0.5 Vp-p 


<200 


nrwrv 

k— 2H— -I 


9 


4.2 


0.85 Vp-p 


<200 


Ton" 

k— 2H-*J 


10 


0.6 




>100k 




11 


2.5 




>100k 




12 


2.8 




>100k 




13 


2.6 




>100k 




14 


8.5 






Vcd 


15 


6.0 


0.8 Vp-p 


>5k 


.M I^L H period 


16 


6.8 


0.8 Vp-p 


<200 


J I— J L h period 


17 


6.8 


0.52 Vp-p 


<200 


yuuJLKA 

k— 2H— »J 


18 


6.0 


0.52 Vp-p 


>5k 


h- — 2H — ►) 


19 









GND 


20 


1.8 




>100k 




21 


2.5 




>100k 




22 


2.5 




>100k 




23 


2.3 




>100k 




24 


2.3 




>100k 




25 


2.0 




>100k 




26 


2.7 




>100k 




27 


•2.7 




>100k 




28 


2.3 




>100k 




29 


2.3 




<100 




30 


2.5 


0.46Vp-p 


<100 


J~\ 1~^\- H period 



■ 



481 



SONY® 



CX20053 



Pin 


DC [V] 


AC [V] 


Imp. [n] 


Remark 


31 


2.5 


0.5 Vp-p 


<100 


ya^N 


32 


4.3 


0.3 Vp-p 


<200 


iPnT 


H period 


33 


4.3 


0.38 Vp-p 


<200 


K— 2H— H 


34 


5.6 


0.44 Vp-p 


<100 




35 


5.6 


0.44 Vp-p 


<100 




36 


5.6 


0.44 Vp-p 


<100 




37 


8.5 






Vcc2 


38 


4.1 


4.8 Vp-p 


>3k 








H period 


39 


2.5 


4.8 Vp-p 


>7k 


UUT 

h»-2H-M 


40 


0.7 


4.8 Vp-p 


>7k 






V period 


1 1 


41 


0.7 


5.4 Vp-p 


>3k 


uu 


3.58 MHz 


42 


0.6 


5.4 Vp-p 


>3k 


ill 


3.58 MHz 


43 









GNO 


44 


1.1 


5.4 Vp-p 


>3k 


AM 


7.16 MHz 


45 






>3k 




46 


5.0 






Vcc3 


47 


6.8 


1 .0 Vp-p 


>50k 


h — 2H— H 


48 









GND 



482- 



SONY® 



CX20053 



Package Outline Unit : mm 

' CX20053 48 pin QFP (Plastic) 0.7g 



37 tn 



D15.3 ±0 - 4 



48 



+ 0.3 
D 12.0 "0.1 



36 



\: 



o 



25 



nxn 



0.8 0.3 



±0.0 6 



nd 24 



+ 0.05 
0.1 5 - 0.0 1 



\D\ 0.1 5 



12 



13 2.1 5 10 - 25 



„ +0.15 ii 
0.1 - 0.0 5 



- lei o.i 2 m\ 



~. ,i 



QFP-48P-L022 



483- 



SONY. 



CX20055 



Color Camera Encoder 



Description 

CX20055 is a bipolar IC designed for color 
camera encoders, compatible both with NTSC and 
PAL systems. It consists of such circuits as an 
aperture, blanking cleaning, pedestal set-up, white 
clip, sync, chroma modulation, phase shifter, fader, 
viewf inder switcher and 75 ohm cable driver. 

Features 

• Integrated color camera signal processing system 
when combined with CX20053, CX20054 (or 
CX200151), and CX20056. 

• Digital phase shifter is incorporated to form the 
carrier's orthogonally-phased components to be 
modulated by the color difference signal. 

• Compatible with NTSC and PAL systems. 

• Luminance and Chroma (Chrominance) signals are 
output independently, as well as composite video 
and viewfinder output signals. 




* The fader circuit is incorporated. 

» A switch and circuit to select the viewfinder signal 

mode -B/W, COLOR, or RETURN VIDEO,- are 

self-contained. 



Block Diagram 




-484 



SONY® 



CX20055 



Absolute Maximum Ratings (Ta = 25°C) 

• Supply voltage Vqc 10 V 

• Operating temperature Topr -10to+60 °C 

• Storage temperature Tstg -55t0+150 °C 

• Allowable power dissipation Pq 833 mW 



• Voltage of Input/Output Pins 



Recommended Operating Conditions 

• Supply voltage VCC1-3 5.0 ±0.15 

• Supply voltage V CC4 8.5 ±0.2 

Pulse Input Voltage CMOS level 

Min. Max. Unit 
V H 4.0 5.0 V 
V L 0.4 V 

When Pin 8 has 1.25 ±0.25Vp-p. 

Output Impedance 

Pin 18 1kfi ±20012 



Pin Description 



Pin 
No. 


Max. voltage 
(V) 


Pin 
No. 


Max. voltage 
(V) 


Pin 
No. 


Max. voltage 
(V) 


1 


gV cc 1~3 


18 


£v cc 1~3 


35 


^^~^~ 


2 


£ V cc 1~3 


19 


__- "~""~ 


36 


^V CC 1~3 


3 


|V CC 1~3 


20 


^V CC 1~3 


37 


gV CG 1~3 


4 


^ V CC 1~3 


21 


^V CC 1~3 


38 


S V cc 1~3 


5 


^ V CC 1~3 


22 


£v cc 1~3 


39 


g V CC 1~3 


6 


gV cc 1~3 


23 


^V CC 1~3 


40 


^V CC 1~3 


7 




24 


g. V CC 1~3 


41 


Max. input 
current 
5O0»iA 


8 


gV cc 1~3j 


25 


^V CC 1~3 


9 




26 


gV cc 1~3 


42 


g V CC 4 


10 


gV cc 1~3 


27 


gV GC 1~3 


43 




11 


g V CC 1~3 


28 


^V CC 1~3 


44 


^ V CC 1~3 


12 


gv cc 1~3 


29 


g V CC 1~3 


45 


§V CC 4 


13 


^V cc 1~3 


30 


gV cc 1~3 


46 


gV CC 1~3 


14 


g V CC 1~3 


31 


gV cc 1~3 


47 


g V cc 1~3 


15 


g V cc 1~3 


32 


^V CC 1~3 


48 




16 


^V CC 1~3 


33 


gV cc 1~3 






17 


Sv cc 1~3 


34 


^V cc 1~3 







Allowable clamp pulse width 
2.24Msec±10% 
When APL is 10 to 90% using a stair step signal. 



No. 


Symbol 


I/O 


Description 


No. 


Symbol 


I/O 


Description 


1 


LALT 


I 


Phase inverting control for the subcarrier's 
90 component. Ground pin terminal 1 
for NTSC system. 


25 


CB90 


1 


Carrier balance adjustment of the 90° 
phase component 


26 


CB0 


1 


Carrier balance adjustment of the 0° phase 
component 


2 


BFP 


I 


Burst flag pulse input 


3 


SYNC 


I 


Sync pulse input 


27 


BG 


1 


Burst amplitude adjustment 


4 


CLP 


I 


Clamp pulse input 


28 


HUE 


1 


Burst phase adjustment 


5 


BLK 


I 


Blanking pulse input 


29 


YG 


1 


Luminance level adjustment 


6 


CHROMA 


o 


Modulated chroma signal output with 
burst 


30 


PED 


1 


Set-up level adjustment 


31 


WC 


1 


White clip level adjustment 


7 


v C ci 




5V power supply for digital phase shifter 


3? 


SYNCL 


1 


Sync level adjustment 


8 


4FSC 


I 


Quadruple subcarrier inspect 


33 


FD0 


1 


Fader circuit gain adjustment 


9 


VCC2 




5V power supply for luminance and 
chroma signal processing circuits 


34 


FDL 


1 


Fader signal input 


10 


FBPF 


I 


Modulated chroma signal input through 
bandpass filter 


35 


V C C4 




8.5V power supply for 75 ohm driver 
circuit 


11 


TBPF 





Modulated chroma signal output before 
bandpass filter 


36 


WC1 


O 


White clip processing signal output 


37 


WC2 


1 


Luminance fader circuit input 


12 


APC 




Decoupling for aperture signal 


38 


VFCC 




Decoupling of the viewfinder color mode 
signal 


13 


R-Y 


I 


R-Y color difference input 


14 


BY 


I 


B-Y color difference input 


39 


BW 


O 


B & W signal output with sync signal 


15 


DUMMY 




Dummy clamp capacitor terminal 


40 


RVS 


1 


Return video signal input 


16 


Y|_-Y H 


I 


Y|_-Y|-| luminance component input 


41 


RVSW 


1 


Return video mode switcher 


17 


CLPDC 


o 


Clamp voltage output 


42 


NTSCOUT 





75 ohm composite signal input 


18 


DL1 


o 


Yh signal output to the delay line for 
aperture 


43 


GND2 




Ground 


44 


OUT 


o 


500mVp-p composite signal output 


19 


GND1 




Ground 


45 


IN 


1 


75 ohm driver input 


20 


DL2 




Yh signal input from the delay line for 
aperture 


46 


VSW 


1 


B/W-color mode switch of the viewfinder 
output signal 


21 


APL 




Aperture signal amplitude control 


47 


VF 


o 


Viewfinder signal output 


22 


Y H 




Y(-| luminance component input 


48 


V C C3 




5V power supply for viewfinder block 


23 


APS 




Aperture signal slicer circuit control 










24 







Phase adjustment of the modulated 
chroma signal's 90° phase component 



-485 



SONY® 



Electrical Characteristics (Ta = 25°C) 



































































Item 


Symbol 


^r 


SW conditions 


VR condition, 




Conditions 


Min. Typ. Max. Unit 




1 


2 


3 5 


8 


10 1 


2.3 


4 2 


22 


23 




74 


41 45 


46 


VR25 


k/R26 VR27 


VR28 


vH^y 


VR30 


VR31 




5V circuit supply 


it 


n 


• 


a 


■ 


» 


» 


< 


b 


b 


b 


• 


■ 




■ 


' 


' 


2.5V 


2.5V 


2.3V 


2.5V 


Note 
ST 


ST 


3.0V 


3 signals are input: SIG Y-l 400mVp-p. 
SIG BY-1 20GYnVp-p, SIG RY-1 
200m Vp-p 


27.0 39 51.7 


,A 




8 5V circuit supply 


12 


12 


a 


a 


a 


a 


b 


c 


b 


b 


b 


. 


. 




• 


■ 


3 


2.5V 


2.5V 


2.3V 


2.5V 


ST 


ST 


3.0V 


Ditto 


63 


2.5 


9.3 


mA 




Pir, 11 71 potential 


PI 7 


M17 


„ 


a 


„ 


b 


a 


, 


a 


, 


a 


, 


, 


b a 


T7 


a 


. 


2.5V 


2.5V 


2.3V 


25V 


ST 


ST 


3.0V 


DC potential measuring 


3 2 


.65 


A.2 


V 






P24 


M24 


a 


a 


s 


7* 


a 


, 


, 


, 


a 


a 


a 


b a 


a 


a 


. 


2.5V 


25V 


2.3V 


2.5V 


ST 


ST 


3.0V 


Ditto 


2.3 


2.7 




V 






APLH 


M12 


a 


„ 


b 


„ 


v 


,■ 


, 


a 


b 


a 


a 


b a 


a 


a 


a 


25V 


2.5V 


2.3V 


2.5V 


ST 


ST 


3.0V 


Input potential SIG Y-2 2MHz, 300mVp-p 


405 






mV 




Mm aperture level 


APLL 


M12 


a 


B 


b 


b 


a 


, 


a 


a 


b 


a 


a 


b 


• 


• 


a 


25V 


25V 


2.3V 


2.5V 


ST 


ST 


3.0V 


Ditto 







11 


mV 




A pe,„ 


APR 


M12 


" 




" 


* 




8 




■ 


bb 


' 


• 


" 


' 


• 


■ 


25V 

2 5V 
2.5V 


25V 

2.5V 
2.5V 


2.3V 


2.5V 


ST 


ST 


3.0V 


Measurement of the output V[ when 
lOOmVp-p sine wave of StG Y-2 - 2MHz is 
input and the output V, when lOOmVp-p 
s.ne wave of SIG Y-2 = 0.5MHz is input 
Rating 20 x log IV,/Vjl 


15.0 


18.0 


21.0 


dB 






ST 


3.0 V 


Measurement of the V, when 300mVp-p 
sine wave of SIG Y-2 = 2MHz is input and 
the Vj when 600mVp-p s.ne wave of SIG 
Y-2 = 2MHi is input. 
Rating V, (2V, ) 


0.68 


0.88 


1 10 


- 






WD 


*,2 


" 


> 


2.3V 


2.5V 










ST 


VR 


3.0V 


amounts serto^maximum with VR30. 


239 


310 


396 


mV 




YBLK,e,e, 


BLKL 


M36 


■ 


b 


b 


• 


aja 


2.3V | 2.5V 




M ,,,e,.up 


M36 


• 


> 


* 


j • 




" 




> 




2 5V 


2.5V 


2.3V ! 2.5V 


ST 


3.0V 


3.0V 
3.0V 
3.0V 
3.0V 


Measure the set-up Pm 36 output 

is indicated by the 

OTpoJnwT ,eC ' BLK period 


-5.5 





5.5 


mV 




v 9 „„o,,se, 


i YGO 
i APSO 

[vol 


h" 

M36 a 


b 


- 


a aja 
_i— (-. 




; 


1 


■ 


» 




■ 


' 


2.5V 


25V 
25V 


2.3V 1 2.5V 
2.3V 2.5V 
2.3V : 2.5V 


3.0V 
2.0V 

ST 


Adjust VR30 so the set-up output becomes 
200mV when VR29 is 3.0V Then, set 
VR29 to 2.0V and measure the set-up 

Rating V, -200mV 








66 


mV 




-ft 

M36 ! a 1 b 


r 


Adjust VR30 so the set-up output becomes 
200mV when S23 is a. then measure the 
set-up amount after S23 is set to b. 
Rating V, -200mV 








88 


nw 




Aperture shce offset 

Sync level 
NTSC output 

Sync level 
Sync level 
Sync level 

NTSC output 

NTSC output 

Chroma dynamic rang 
NTSC output 


b 




a aj. 




M36 ..jbjj. 1 . a|. . 


jin; 


-4i 

a a j a' a 
-i ' 


2 5VJ25V 


3 0V VR 

- -4— 

2 0V VR 


Adiust VR30 so the output set-up becomes 
50mV Measure the output (excluding the 
set-up) when SIG Y=1 = 360mVp-p is 


4,4 


500 


605 


m v 




M36 a i b i b ; a : a a 

- M ! ; : p 


r 


,':»!. 


t | 


4 .. p- . ... 

2.5V 1 2.5V ! 2.3V | 2.5V 


Ditto, with the input signal level of SIG 
Y-1 -'l00mVp-p 


23 


45 


88 


mV 




d.!. 


T--" 


a a i a | a 2 5V 2 5V j 2 3V : 2.5V 
a a a a ! 2.5V 2 5V 2 3V ; 2 5V 
a a a a 2 5V 2.5V 2 3V ! 2.5V 
a a ; a . a 2 5V 2 5V 2 3V ■ 2 5V 


1 -j 
ST j VR 

3.0V j 2.5V 


30V 
1 ) S" 


Adjust VR30 so the output set-up becomes 
50mV. Calculate as in Note 2 using the 
M36 Y output component when SIG Y-1 


° 


2.6 


4.4 


% 




WC ! M36 . ajb'ba.aia 




black level when SIG Y-1 = 500mVp-p 


405 


490 


605 


mV 




APSOFF 

SNT 
SVF 

YVFC 


M36 ! a b ; b ; a | a ' a 
M36 a ! b : b a i a j a 


\ f- 

ST VR 


3.0V 


Adiust VR30 so the output set-up becomes 
200mV Input 2MHz SIG (APL = 

50mVp-p) and measure the output 

Ditto 


234 



300 


374 


mV 




ST ! VR 3 OV 





55 


mV 




a a ' a ! a 2.5V 2.5V : 2.3V ^ 2 5V I ST ST 3.0V 


Measure sync, eye, 


513 


595 


682 


mV 




ba b a' a' a a'a a a'a aba'aa a 2.5V ; 2 5V ' 2.3V j 2.5V ST: ST : 3.0V 
M39 '. ! b' a'b'. '.'.'.'.I.!. '.!.ib'.:. ! >:.'j.5v'2.5v|23V,25V| ST ST j 3.0V 


Ditto 


239 


280 


325 


mV 






248 


290 


336 


m v 




M47 a . t> a b aiig.i a ' a ', a aab b b a a 2 5V ! 2 5V 
M42 a,b a c a!, la . a ; a ' a : a ; a , c ' a a ! a ' a ! 2 5V ; 2 5V 


2.3V 2.5V; ST 


| ST 


I 3.0V 


fc:g , „ e .,rr, n pu: GRV ' 300mVpp 


239 


282 


325 


"7 




! 2.3V 2.5V ST 


i ST 


3.0\ 


Y signal output when SIG WC = 450mVp-p 


1.2 


M 


1.60 




i M3 9 a"b a c a., , a a^lai.'a^ia 1 ,;.:. 25V:25V|23V 25V, ST i ST 


3 0V 


554 


660 


754 


mV 




I U4; ,'b a c a a'a a a « : a .a ] a' c j a a a a 2 Sv ', 2 ,5V ' 2 3V ! 2 5V ST ST 3 0\ 
g c a ag a a aaa^acaa'ab 2 5V 2 5V ! 2 3V ! 2 5V ST ST 3 


i 


572 


680 


776 


mV 






527 


660 


759 


mV 




; abacaaaaaaaa'aibbbaa 2.5V: 2.5V : 2.3V 2 5V ST j ST 3.0 

1 YHNT ' M42 abacaaaaaaaaacaaaa 2.5V . 2.5V . 2.3V | 2.5V ST ST 3.0 

] YDBw! M39 a b a c , a a a a a , a'a c a a , a 2 5V 2.5V 23V|2 5v! ST, ST | 3.0 

YDVFB M4 7 a b a c a a 3 a a a a a a c a a a'a 25V 2.5V 2.3V ; 2.5V, ST ST : 3.0 

YDVFC M4 7 abacaa.ia.aaaalac.aaab 2.5V; 2.5V [ 2.3V ' 2.5V. ST : ST j 3.0 

CONT M42 a bbba b a a a a a a | a : b ; a a a a 2.5V ! 2.5V 2.3V 2.5V ST ST ' 3.0 

'cDCHRl M6 a b b b a b a a a a a a,„ b'a a a a : 2.5V j 2 5V j 2 3V | 2.5V ST ST ! 3 


i\ SIG RV - 1 Vp-p (Y input = 700mV) is 


585 


662 


742 


- 




, ; Calculate (Note 2) using the input when 
J i the SIG WC - 500mVp-p Y signal is input 





05 


2 


% 




„, 


» 


1.25 




% 




/ Ditto 


o 


2 


12 


% 






° 


2 


,3 


* 




1 Measure the output V L when 200m Vp-p 
V of SIG BPF = 4MHz s.ne wave and the 


1 ° 

! 


1.0 
0.2 


22 


» 




* 


% 




1 CLVF 


R M6 abbbabaaiaa^aa^blaa'a b i 2 5V 2 5V 2 3V 2 5V ST! S T ; 3 


y! JS^i™Sr^" 






5 


12 


% 




■= KJ5 




" 


b' 


b 


b 


» 




•i 


:■ 


1 


■i 


•1 




' 


•' 


b|25 
I 


V| 2, 


V|2 


3V 2. 


v| s 

1 


t 
T j S 


r|,.o 


" 5 


18 


% 



486- 



SONY® 



CX20055 



H-. 


*™« 




SW conditions 


VR conditions 


Conditions 


«.. 


Typ. 


Max. 


U.K 




2 


3 


5 


8 


10 


12 


13 


14 


21 


22 


23 


34 




40 




45 




VR25 




VR27 


VR28 


VR29 


VR30 


VR31 


~ 


' 


M42 




b 


b 


• 


• 


■ 


• 


• 


■ 


■ 


b 


■ 


■ 


• 


■ 


' 


• 


" 


2.5V 


2.5V 


2.3V 


2.5V 


ST 


VR 


3.0V 


Input SIG Y-2 - lOOmVp-p at 0.5MHz 
and 4MHz. Adjust VR30 so the output 
is not distorted when 0.5MHi is input, 
then measure its output V, and the V, 

Rating 20 x log IV, /V, ) 


-6 5 


-3.5 


-,.. 


dB 


MM . M . 


VSWBC 


M47 




» 


• 


■ 




b 


• 


■ 


• 


• 


• 


• 


• 


b 


• 


• 


• 


• 


2.5V 


25V 


2.3V 


2 6V 


ST 


VR 


3.0V 


Measure the output amplitude at 0.5MHz 
when 300mVp-p with SIG BPF ■ 0.5MHz 





7 


17 


m v 


*»«*»», 2 


VSWCB 


*47 




» 


■ 


< 




■ 


• 


• 


■ 


• 


• 


• 


• 


< 


• 


• 


■ 


b 


2.5V 


2.5V 


2.3 V 


2.5V 


ST 


VR 


3.0V 


Measure Y output when SIG WC - 
450mVp-p is input, with Pin 38 open. 





• 


17 


mV 


Switcher test 3 


RVSWB 


M47 




•> 


• 


« 




• 


• 


• 


• 


• 


■ 


■ 


■ 


■ 


" 


b 


> 


' 


2.5V 


2.5V 


2.3V 


2.6V 


ST 


VR 


3.0V 


Input SIG R VAPL - 1 Vp-p and SIG 
WCAPL - 450mVp-p and measure the 








" 


mv 


— « 


RVSWC 


M47 




» 


. 


< 




b 


• 


■ 


• 


• 


• 


• 


a 


c 


b 


b 


• 


b 


2.5V 


2.5V 


2.3V 


2.5V 


ST 


VR 


3.0V 


Measure as above with the input signal and 
SIG BPF - 200mVp-p input. 


° 





17 


m v 


V fader 


YFD 


M42 




b 


- 


< 




■ 


' 


• 


• 


■ 


■ 


■ 


- 


' 


■ 


• 


• 


■ 


2.5V 


2.5V 


2.3V 


2.5V 


ST 


VR 


3.0 V 


Adjust V34 to M42 Y output becomes 
100m Vp-p when SIG WC - 450m Vp-p is 
input and measure the V34 voltage. 


„ 


1.35 


,., 


v 


Burst OFF 


BFPH 


M42 




b 


b 


c 


b 


c 


• 


• 


• 


• 


a 


• 


• 


b 


• 


• 


• 


• 


2.5V 


2.5V 


2.3V 


2.5V 


ST 


VR 


3.0V 


Measure the 3.58MHz output amplitude. 








" 


m v 


Carrier 
Bal . NTSC 


CBNT 


M42 




• 


- 


• 


• 


■ 


• 


■ 


• 


• 


• 


■ 


' 


b 


• 


• 


" 


' 


3} 
Cal 


3) 
Cal 


3) 
Cal 


3) 
Cal 


ST 


VR 


3.0V 


Atign the split bursts on the veciorscope 
using VR28 with S, set at b, and set to 
75% burst using VR27. Adjust the 
carrier balance with V25 and V26. With 
S, set at a, measure the leakage of the 


37 


« 


- 


dB 


Carrier 
Bal. PAL 


CBPAL 


M42 


« 


■ 


b 


• 


> 


« 


• 


■ 


■ 


■ 


' 


• 


" 


> 


' 


' 


' 


' 


Cal 


Cal 


Cal 


Cal 


ST 


VR 


3.0V 


Measure the carrier leakage 


n 


35 


- 


dB 


Carrier's orthogonal 
degree 1 


ODEC 


V "oS'" 


" 


■ 


" 


• 


> 


< 


• 


> 


b. 


• 


■ 


• 


' 


■> 


' 


■ 


' 


• 


Cal 


Cal 


c- 


Cal 


ST 


VR 


3.0 V 


B-Y axis and the burst when SIG BY-2 and 
SIG RY-2 - 100m Vp-p are input. 


-11 





" 


deg 


Carrier's orthogonal 
degree 2 


90OEC 


w" 


" 


■ 


* 


• 


- 


« 


• 


b 


» 


• 


• 


« 


• 


- 


■ 


• 


' 


' 


Cal 


Cal 


Cal 


Cal 


ST 


VR 


3.0 V 


Measure the phase difference between the 
burst and WT (R-Y) axis with the above 


-„ 


• 


" 


dag 


degree 3 


-90DEC 


w" 


" 


■ 


" 


■ 


b 


« 


' 




" 


■ 


• 


• 


• 


- 


• 


' 


a 


• 


Cal 


Cal 


Cal 


Cal 


ST 


VR 


3.0V 


Measure the phase difference between the 


-„ 


• 


" 


-■ 


Chrome 
BLK offset 


CBUK 


M„ 


■ 


• 


«■ 


. 


» 


c 


• 


• 


• 


• 


• 


■ 


• 


b 


■ 


• 


■ 


• 


Cal 


Cal 


Cal 


Cal 


ST 


VR 


3.0V 


Measure BLK pulse amplitude with 
Mil. 





o 


72 


m v 


Max. 
Burst gain 


BGH 


M42 


■ 


• 


» 


• 


» 


< 


• 


• 


• 


■ 


» 


■ 


> 


» 


• 


• 


" 


• 


Cal 


Cal 


3.0 V 


Cal 


ST 


VR 


3.0V 


M«» •»..«*..«• 


1, 


1.5 


22 


v 


Mm. 


BGL 


M42 


• 


• 


- 


■ 


«• 


« 


■ 


■ 


« 


• 


• 


• 


» 


b 


" 


• 


' 


■ 


Cal 


Cal 


2.0V 


Cal 


ST 


VR 


3.0V 


Ditto 


81 


150 


360 


m v 


*™ 


HUEH 


M42 


• 


• 


- 


• 


» 


« 


■ 


• 


' 


• 


■ 


• 


» 


> 


a 


' 


' 


• 


Cal 


Cal 


VR 


Cal 
3.0V 


ST 


VR 


3.0V 


VR28 is varied from Cal to 3.0V 
(Level is adjusted with VR27) 


" 


60 


83 


dig. 




BY 


M42 


• 


■ 


» 


• 


* 


< 


• 


• 


b 


• 


■ 


■ 


• 


b 


» 


• 


• 


a 


Cal 


Cal 


Cal 


Cal 


ST 


VR 


3.0 V 


Measure 3.58MHz output amplitude when 
SIG BY-2- lOOmVp-p 


0.65 


0.91 


1.10 


V 


H-Vta* 


RV 


M42 


. 


. 


b 


a 


b 


c 


a 


b 


a 


. 


• 


a 


• 


b 


• 


• 


" 


• 


Cal 


c, 


Cal 


Cal 


ST 


VR 


3.0 V 


Measure 3.58MHz output amplitude when 
SIG RY-2- lOOmVp-p. 


0.9 


1.3 


1.5 


V 


BY dynamic range 


BYD 


M42 


■ 


• 


■> 


• 


b 


« 


• 


- 


b 


• 


• 


' 


' 


» 


■ 


" 


> 


' 


Cal 


Cal 


Cal 


Cal 


ST 


VR 


3.0V 


Measure the outputs V, and V, when 
SIG BY-2 - lOOmVp-p and 200mVp-p are 





2 


' 


* 


H-YdynemKrang. 


RYD 


M42 


• 


• 


» 


a 


b 


c 


» 


b 


a 


> 


• 


a 


« 


b 


■ 


a 


» 


a 


Cal 


Cal 


Cal 


Cal 


ST 


VR 


3.0V 


Ditto.butwith the input signal S.G RY-2 





5 


12.7 


% 


C fader 


CFD 


*«2 


• 


" 


" 


■ 


' 


< 


• 


> 


» 


• 


' 


" 


- 


» 


' 


» 


' 


" 


Cal 


Cal 


Cal 


c, 


ST 


ST 


3.0V 


Adjust V34 so M42 3 58MHz chroma 
output becomes lOOmVp-p when SIG 
RY-2 = lOOmVp-p ,s input, then measure 
V34 voltage. 


1.35 


'■' 


" 


DG output amplifier 


DG 


M42 


• 


- 


> 


> 


■ 


c 


■ 


' 


' 


• 


" 


■ 


> 


» 


' 


' 


" 


' 


Cal 


Cal 


Cal 


Cal 


ST 


ST 


3.0 V 


Input DG and DP measuring signals with 
SIG IN - 500mVp-p (DC 4.25V and APL 
50%) and measure DG. 


- 


1.5 


3 


% 


dynamic range 


OAD 


M42 


• 


■> 


" 


" 


■ 


' 


• 


• 


' 


• 


■ 


' 


' 


<■ 


' 


a 


- 


a 


Cal 


Cal 


Cal 


Cal 


ST 


ST 


3.0V 


SIG IN = 3.6VDC + 6Vp-p (100kHz) sine 


«- 


5.8 


7.2 


V 


(Motel) The ST in VH co 
(Note 21 Calculation (Not 

Calculate 100X 
(Note 3) TheCal in VR c 
(Note 4} Measure 3.58MH 


e 2)<sasf 


>dicates a V 
Je V, of the 


r c 

h o 


V 


*25 


gn 
-2 


8v 


.1 


TO 


ag< 

'.I 

75 


s V 

%i 


R2 


9 = 


2.4 


10 


J. v 

of 


R3 


0- 


2. 


25 
e2 


Vand 
x log 


of the 


2.771 


Carrier 


the IC 
Bal N 


TSC). 


-» 


n the VR midpoint. 











I 



487- 



SONY® 



CX20055 



Electrical Characteristic Test Circuit 



T 5V aA Tb .$TT 

/y\Mil\ S * 6 \s45 



75 



39K Mil 10K? 



1? v sloV 



J SIG RV 

j b SIG RVAPL 



50K b 3, *l'*^t~fe 



2SC403C 




SIG BPF a 

4MHz 200mV,400mV 
0.5MHz 300m Vp-p 10n ^ 
Sine «vave ^ 

SIG APC 

2MHz 50mVp-p 
Sine 



SIG BY1-2 SIG RY-1~2 



VR32 and VR33 indicate a VR condition when VR32 - 2. 189V and VR33 - 2. 412V with the IC remoued and < 



-488- 



SONY® 



Synchronized Signal Waveform 



20 30 40 50 60 70 

H 1 1 1 1 1- 



80 

—\ »- T (/usee) 



3V 
SIG LALT ~0V |_ 



-1 cycle (63.5fisec)- 



3V 
SIB BPF 0V 

3V 



SIG SYNC OV 



IS 



IT 



3V 
SIG CLP QV P I 



SIG BLK 3V 

~ov 



JT 



Input Signal Waveform 



SIG BY-1 



SIG BY-2 
SIG RY-1 



SIG RY-2 



SIG Y-1 



SIG Y-2 



SIG WC 
(Y signal) 



10 
H- 



SIG WCAPL is a waveform (APL 10% 
waveform) with the SIG WC waveform 
output once every 5H and blanked 
for4H. 



SIG RVAPL 



J 



30 
-+- 



60 

-f- 



i_r 



(Note) SIG RVAPL waveform only is synchronized with SIG WC 
waveform peak in a RVAPL Sync period (waveform: 
APL 90%). 



80 

H »- T (jjsec) 




Levels and cycles of used 
waveforms 



200m Vp-p 

(color bar B-Y signal) 



100m Vp-p, 200m Vp-p 



200mVp-p 

bar R-Y signal) 



100m Vp-p, 200m Vp-p 



100m Vp-p, 360m Vp-p 
400mVp-p, 500mVp-p 

0.5MHz 100m Vp-p 

2MHz 100mVp-p, 
300m Vp-p 600mVp-p 

450mVp-p, 500mVp-p 



I 



700m V 
300m V 



489 



SONY® 



Signal Waveform Generation Circuit Diagram 



SO 



" a 




m M m 



$■ y Um Mr-$ 




-490 



SONY® 



CX20055 



Reference Pin Voltage DC Characteristics (Ta = 25C Vcd ~3 = 5V,Vcc4=8.5V) 
Refer to Electrical Characteristic Test Circuit 



Pin No. 


Pin voltage (V) 


Pin No. 


Pin voltage (V) 


6 


3.17 


22 


3.57 


8 


3.16 


24 


2.75 


10 


2.23 


32 


2.49 


11 


3.24 


36 


2.60 


12 


2.54 


37 


2.12 


13 


3.57 


38 


2.29 


14 


3.57 


39 


2.88 


15 


3.57 


40 


3.97 


16 


3.57 


42 


5.90 


17 


3.62 


44 


3.04 


20 


2.92 


47 


2.65 



Test Conditions 



S1 


S2 


S3 


S5 


S8 


S10 


S12 


S13 


S14 


S21 


S23 


S34 


S37 


S40 


S41 


S45 


S46 


a 


b 


b 


b 


a 


a 


a 


a 


a 


a 


a 


a 


b 


a 


a 


a 


a 



VR25 


VR26 


VR27 


VR28 


VR29 


VR30 


VR31 


VR33 


V34 


2.5V 


2.5V 


2.5V 


2.5V 


2.5V 


3V 


3V 


2.5V 


3V 



Pin 32 is open. 



I 



-491 



SONY® 



Application Circuit (NTSC Mode) 



SYNC PULSE IN 



CLP PULSE IN 



CHROMA OUT 



L | BPF | - 



H>^ 



X 



NTSC 

Composite 



* in 






A B*W Signal 
^ IK 



'48 47 46 



43 42 41 40 39 38 37 



15 16 17 18 



20 21 22 23 24 



XT* 



_nnr> i f 



YH Input Signal 



86V 

H»-fe 



>-y/tf <l FADE SIG IN 



— -Ml 
— -Hi 

— * M F 

30 J — f 

— -Hi 

29 J— 

— -Hi 

27 /— ' 

— -Hi 



References for Circuit Design 

(1) NTSC and PAL systems 

• NTSC system 

Ground LALT (Pin 1) terminal. 

• PAL system 

Input a phase inverting signal every 1 H to LALT (Pin 1 ) terminal. 

CPAL = U sinart + Vcosart LALT = "L" 

U sincot - Vcoscot LALT = "H" 

(2) Fader Signal (CMOS Level) 




-492 



SONY® 



CX20055 



With the fader signal, the composite video (Pin 42), B & W (Pin 39), CHROMA (Pin 6) and viewfinder (Pin 47, when 

viewf inder output signal has a color mode) output signals are faded in or out. 

(Refer to Y, CHROMA FADE-IN/OUT CHARACTERISTICS on page 14 as well as the above diagram). 

With the above diagram, the fader-out voltage is determined by VR. 



Fader signal 


Mode 


"L" level 


Fade-in 


"H" level 


Fade-out 



(3) Viewfinder switch (i) 

The viewfinder switching systems are available; video switch (VSW) and return video switch (RVSW). 



Return Video 
Signal 



Video Switcher 



Return Video 
Switcher 




Return Video Switch 



VSW 


RVSW 


VF 


"L" 


"L" 


B & W mode 


"H" 


"L" 


Color mode 


"L"or"H" 


"H" 


Return video mode 



The switcher input is as shown in the diagram below. 
Video switcher input Return video switcher input 



T46J W" 



& 



■ 



Video switcher has "H" level = 3 ~ 5V, return video switcher has ("H" level) with 10K and 39K external resistors. 



493- 



SONY® 



CX20055 



(4) Viewfinder switch (ii) 

When using a color mode, modify the circuit as in the diagram below. In this case, adjust the output level using VR38 
(see below). 



33n 

Return Video Signal O — ;H (- 

:75 



10K 
A/\A- 



ik * 33 " i 



2SC403C 



20K 



CX20055 46 




2K 

VR38 



51 K 'J- 33>i 



I 



(5) Caution in burst adjustment (Refer to EXAMPLE OF APPLICATION CIRCUIT) 

Burst is a composite signal of the carrier's 0° component sino; set and 90° component coscj set as in the following 
equation. 

Burst = A [sincosct + Bcoswsct] 

where A is a gain determined by VR27 and B by VR28. 

Hence, the burst amplitude varies when the hue is varied with VR28. Therefore, adjust the burst amplitude with 

VR27 (BG) only after VR28 (HUE) is adjusted. 

(6) Adjustment of luminance and chroma signals (Refer to EXAMPLE OF APPLICATION CIRCUIT) 

• Adjust VR29 so Pin 36 output becomes 450mVp-p. 

• Adjust the luminance level of Pin 42 output with VR33. 

• Adjust the chroma level of Pin 42 output with the input level variation of Pin 13 and Pin 14. 



-494- 



SONY® 



CX20055 



Control Characteristics YG Control Characteristics 



























































































500 



































































































































1.0 2.0 3.0 

YG (V) (DC Potential of Pin 29) 
YH = 400mV Stayer Step 
Measuring item < YGMAX > condition 
Measure Y signal level of Pin 36 excluding setup 
with SIGY-1 = 400mV and VR29 made variable. 
Fig. 1 







White Clip Level Characteristics 












































/ 


s 














































> 






















o 






















S 


























































































2.5 



3.0 



WC (V) (DC Potential of Pin 31 ) 

Measure the clipped Y signal level of Pin 36 when 

VR31 is varied with measuring item in < WOcondi- 

ti0n - Fig. 3 



Y-fader Amp Characteristics in Fade-in Mode 




FDO (V) (DC Potential of Pin 33) 
WC2 = -450mV stayer step input 
Measure the Y output level of Pin 42 when VR33 is 
varied with measuring item in < YFD > condition. 

Fig. 5 









Set 


-up 


Characteristics 








































































300 


























































































































V 






















N 


* 







2.5 



2.6 



2.7 



2.8 



2.9 



PED (V) (DC Potential of Pin 30) 
Measure the clipped Y signal level of Pin 36 when 
VR30 is varied, with measuring item in (BKL> 
condition. 

Fig. 2 







s> 


nc Level Adjustment Range 

































































































































































































































SYNC L (V) (DC Potential of Pin 32) 

Measure the SYNC output level of Pin 42 when VR32 

is varied with measuring item in SYNCNT condition. 

Fig. 4 

Chroma Fader Amp Characteristics 
in Fade-in Mode 




FDO (V) (DC Potential of Pin 33) 
(BY) or (R-Y) = 100mV input 
Measure the chroma output level of Pin 42 when 
V R33 is varied with measuring item in < CFD > condi- 
tion. 

Fig. 6 



-495- 



SONY® 



Fade-in/Face-out Characteristics 
of Y-fader Circuit 



Fade-in/Fade-out Characteristics of 
Chroma Fader Circuit 




FDL (V) (DC Potential of Pin 34) 
WC2 = -450mV stayer step input 
FDO = 2.45V 
Measure Y output level of Pin 42 when V34 is varied 
with measuring item in< YFD> condition. 
Fig. 7 
Carrier Balance Characteristics of B-Y chroma 
Modulator 



1.0 






















0.5 

































































































































-1.0 

































































2.0 



3.0 



CBO (V) (DC Potential of Pin 26) 
CB90 = Cal 
Measure chroma level Pin 42 when VR26 is varied 
with measuring item in ( CB > condition. 
Fig. 9 



2.0 







Burst Ga 


in Characteristics 















































































































































































































2.0 3.I 

BG (V) (DC Potential of Pin 27) 
HUE = Cal 
Measure the burst level of Pin 42 output when VR27 
is varied with measuring item in < BGH > condition. 

Fig. 11 




FDL (V) (DC Potential of Pin 34) 
(BY) or (R-Y) = 100mV input 
Measure the chroma output level of Pin 42 when 
V34 is varied with measuring item in < CFD > condi- 
tion. _. _ 
Fig. 8 

Carrier Balance Characteristics of R-Y Chroma 
Modulator 




CB90 (V) (DC Potential of Pin 25) 
CBO = Cal 
Measure chroma level of Pin 42 when VR25 is varied 
with measuring item in < CB > condition. 
Fig. 10 
HUE Control Characteristics 



















/ 


/ 


















A 


/ 


















i 


/ 




















/ 




















J 


t 




















/ 






















f 
























































-50 























2.0 3.0 

HUE (V) (DC Potential of Pin 28) 
Measure the output of Pin 42 using a vectorscope 
with measuring item in < HUEH > condition. 

Fig. 12 



-496- 



SONY® 



CX20055 



VCC1 ~ 3 5V Power Supply Characteristics 

Measuring point: Pin 42 output 
VCC4 = 8.5V constant 
Y Output Power Supply Variation Characteristics 




4.75 5.00 5.25 

VCC1 ~ 3 Power Supply Voltage (V) 

Fig. 13 



SYNC Output Voltage Variation Characteristics 




4.75 5.00 5.25 

VCC1 ~ 3 Power Supply Voltage (VI 

Fig. 14 



Burst Output Power Supply Voltage Variation 
Characteristics 



CHROMA Output Power Supply Voltage Variation 
Characteristics 



10 





































































































































































































10% 























4.75 5.00 

VCC1 ~ 3 Power Supply Voltage (V) 
Fig. 15 




5.00 



VCC1 ~ 3 Power Supply Voltage (VI 
Fig. 16 



VCC4 8.5V Power Supply Voltage Characteristics 
(Measuring Output of Pin 42) 

(Refer to item "Output Amp D Range" of 
ELECTRICAL CHARACTERISTICS) 



7 


f 


L 


7 


/ 


~/_ 


/ 


2_ 


/ 





VCC4 (VI 

Fig. 17 



-497- 



SONY® 



CX20055 



Test Method of VCC4 8.5V Power Supply Voltage Variations 




iooom 



Vectorscope 



CX20055 is connected as shown above, with connecting terminals other than Pins 35, 42, 43 and 45 being open or in 

< DG> condition of electrical characteristics. 

As signal sources, DG and DP measuring signals (APL: 50%) are used. 

(1 ) Adjust the signal source output so the DC voltage of Pin 45, being set at 4.05V, becomes 1 Vp-p signal sigh the 75 ohm 
termination of Pin 42 output (VCC4 = 8.5V). 

(2) Set VCC4 at a measuring power supply voltage changing from 8.5V. 

(3) Measure the DC voltage of Pin 45 when sync level decreases by 5% compared with that of (2) (VDC1 ). At this time, 
adjust VR so the DC voltage of Pin 45 decreases. 

(4) Adjust VR so the DC voltage of Pin 45 increases and measure its voltage when DG is 2% (VDC2). 
Fig. 17 is a diagram with the range VDC1 to VDC2 (VDC2-VDC1) defined as an input bias allowance. 



-498- 



SONY® 



Temperature Characteristics (Pin 42 Output) 

Y Output Temperature Characteristics 




Y/SYNC Temperatt 


re Characteristics 













































































































































































































Ambient Temperature i°C) 

Fig. 18 



Ambient Temperature (°CI 
Fig. 19 



Burst Output Temperature Characteristics 











































































































































































































CHROMA (Red)/Burst Temperature Characteristics 



Ambient Temperature (°C) 
Fig. 20 




Ambient Temperature (°C) 
Fig. 21 



Maximum Allowable Power Dissipation Decrement Curve 















































N 






\ 






















































































\ 




















\ 






















\ 




















v 


s 











White Clip 

ST:WC1 White clip c. 


Characteristics 


l„.IOf 


40Om V 


500 










































































_ 






















E 








/ 














Q. 








/ 














S 






















100 
































|,ST, 

































Ambient Temperature Ta (°C) 
Fig. 22 



019 0.58 0.96 135 1.73 

ST ST ST ST ST 

Input Level 
Fig. 23 



499- 



SONY® 



CX20055 



Terminal Reference Value 








(When using a device ICX016K) 


Pin 


DC [V] 


AC [V] 


Imp [12] 


Remark 


1 







>7k 




2 


3.9 


4.0Vp-p 


>7k 


| | 


H cycle 


3 


3.8 


4.0Vp-p 


>7k 




H cycle 


^T 


4 


0.1 


4.0Vp-p 


>7k 


I I 


H cycle 




5 


3.0 


3.7Vp-p 


>10k 




H cycle 


M~1I 


6 






<200 




7 


5.0 






VCC3 


8 


2.5 


5.4Vp-p 


>7k 


wm 


14.32MHz 


9 


5.0 






VCC2 




10 


2.2 


0.4Vp-p 


>7k 




11 


3.2 


1.05Vp-p 


<200 




12 


2.5 




>2k 




13 


3.6 


0.27Vp-p 


>100k 




14 


3.6 


0.34Vp-p 


>100k 




15 


3.6 




>100k 




16 


3.6 




>100k 




17 


3.6 




<50 




18 


3.1 


0.5Vp-p 


=^ 1k 


rvr 


H cycle 


19 









GND 




20 


3.1 


0.5Vp-p 


>50k 


r\r 


H cycle 


21 


2.4 




>100k 




22 


3.8 


0.5Vp-p 


> 100k 


pkt- 


H cycle 


23 


2.1 




>100k 






24 


2.5 




>9k 





500 



SONY® 



CX20055 



Pin 


DC [V] 


AC [V] 


Imp [ft] 


Remark 


25 


2.5 




>100k 




26 


2.5 




>100k 




27 


2.3 




>100k 




28 


2.4 




>100k 




29 


2.3 




>100k 




30 


2.7 




>100k 




31 


2.8 




>100k 




32 


2.3 




>7k 




33 


2.4 




>100k 




34 


0.1 




>100k 




35 


8.5 






vcci 


36 


2.1 


0.7Vp-p 


<100 


Lr-\T L-i. h cycle 


37 


2.1 


0.7Vp-p 


>7k 


^J ^ H cycle 


38 


2.3 




>7k 




39 






<200 




40 


1.5 




>6k 




41 









DC not apply more than 0.5V direct. 


42 


5.7 


1.3Vp-p 


<5 


Iv^Kr^ H cycle 


43 









GND 


44 


3.0 




<200 




45 


4.1 


0.7Vp-p 


>100k 


|T mJ%l * H cycle 


46 


2.6 


1.5Vp-p 


>7k 


l^**^ 1 H cycle 


47 


2.6 


1 .5Vp-p 


<5 


^^ 


48 


5.0 






V C C4 



-501 



SONY® 



CX20055 



Package Outline Unit : mm 



48pin QFP(Plastic) 0.7g 



D15.3 ±(W 




\Q\ 0.1 5 I 



13 ,,.-±0.25 



' — ®TaTi 



QFP-48P-L022 



502 



SONY. 


CX20056 


Automatic Iris 


and Automatic White Balance 



Description 

CX20056 is a bipolar IC which has been developed for 
Automatic White Balance control, AGC control and automatic 
iris driving for color camera, and it has functions of signal 
amplifying, clamping, R/B line sequential signal separation, 
pedestal setting, window extraction, A.W.B. peak detection 
and comparison, AGC amplifier controlling, iris driving, low 
light alarm indication (LED drive), etc. 

Features 

• It can be composed as a consistent color camera signal 
processing system, together with CX20053, CX20054, 
CX20055, etc. 

• Automatic white balance is standardized to the color 
difference line sequential signal; however, it is 
respective input pins of R, G and B, and it can available 
for various kinds of image pick-up systems. 

• A comparator with active load is incorporated within it, 
and therefore high precision white balance can be 
obtained. 

• Time constant and detection system of the AGC and 
automatic iris can be set arbitrarily with the external 
circuit. 

• Operational amplifier which can drive the iris coil 
directly is incorporated. 

• LED drive output pin for low light alarm indication. 




Block Diagram 



IRIS input (11) 



AGC input (12Y 




{35) R-G COMP output 



{36) B-G COMP output 



LED DRIVE 
{16) AGC output 



33) IRIS DRIVE 



I 



E89663 - ST 



503 



SONY® 



CX20056 



Absolute Maximum Ratings (Ta=25°C) 

• Supply voltage Vcd to 4 

• Operating temperature Topr 

• Storage temperature Tstg 

• Allowable power dissipation Pd 



10 


V 


-10 to +60 


°C 


-55 to +150 


°C 


833 


mW 



Input Pin 


Maximum Voltage 








No. 


Voltage(V) 


No. 


Voltage(V) 


No. 


Voltage(V) 


1 


^Vcc2 to 4 


18 


^Vcd 


40 


^Vcc2 to 4 


6 


^Vcc2 to 4 


20 


^Vcd 


41 


^Vcc2 to 4 


7 


^Vcc2 to 4 


30 


^Vcd 


46 


^Vcc2 to 4 


8 


^Vcc2 to 4 


31 


^Vcd 


47 


^Vcc2 to 4 


11 


^Vcc2 to 4 


37 


^Vcc2 to 4 


48 


^Vcc2 to 4 


12 


^Vcc2 to 4 


38 


^Vcc2 to 4 






13 


^Vcc2 to 4 


39 


^Vcc2 to 4 







Recommended Operating Conditions 

• Supply voltage Vcd 8.5 ± 0.2 V 

Vcc2 to 4 5.0 ±0.15 V 



Maximum Output Current 



No. 


Currentf mA) 


16 


10 


33 


100* 


34 


20 



* Care should be exercised 
so that Pd does not exceed 
the maximum rating. 

Recommended Input Pulse level 



No. 


Input level 


1 


CMOS level 


13 


CMOS level 


46 


CMOS level 


47 


CMOS level 


48 


CMOS level 



CMOS level 





Min. 


Max. 


Unit 


Vh 


4.0 


5.0 


V 


Vl 





0.4 


V 



504- 



SONY® 



CX20056 



Pin Description 



No. 


Symbol 


I/O 


Description 


1 


CLP 


I 


Pulse input which clamps the input signals (white balance, AGC and IRIS) 


2 


Vcc2 




A partial power source (5V) of the white balance section. 


3 


CLP Cg 





Output which has been clamped by G signal. 


4 


CLP Cb 





Output which has been clamped by B signal. 


5 


CLP Cr 





Output which has been clamped by R signal. 


6 


G input 


I 


Input of G signal from CX20053. 


7 


B input 


I 


Input of R/B signal from CX20053 which corresponds to B signal. 


8 


R input 


I 


Input of R/B signal from CX20053 which corresponds to B signal. 


9 


CLP Ci 





Output which has been clamped by IRIS signal. 


10 


CLP Ca 





Output which has been clamped by AGC signal. 


11 


IRIS input 


I 


Input of IRIS signal from CX20053. 


12 


AGC input 


I 


Input of AGC signal from CX20053. 


13 


BLK 


I 


Blanking pulse input 


14 


AGC DET input 





Output of the signal to which pedestal is attached after it has been input to 
pin @ and clamped. An externally attached detecting circuit is 
connected to this pin. 


15 


IRIS DET input 





Output of the signal to which pedestal is attached after it has been input to 
pin © . An externally attached detecting circuit is connected to this pin. 


16 


AGC output 





Output of the AGC operational amplifier, and it controls the AGC gain of 
CX20053. 


17 


Vcc3 




Power source (5V) of the AGC and IRIS sections. 


18 


AGC DET output 


I 


Negative input of the AGC operation amplifier. 


19 


GND3 




Ground of the AGC and IRIS sections. 


20 


AGC REF 


I 


Positive input of the AGC operation amplifier. 


21 


AGC BIAS output 





Reference voltage output to be fed to pin @ . It is possible to be 
controlled by pin @ . 


22 


GND1 




Ground of the operational amplifier and low light comparator. 


23 


PHASE COMP C1 


I 


AGC operation amplifier for phase correction. 


24 


PHASE COMP C2 


I 


AGC operation amplifier for phase correction. 


25 


Vcd 




Power source (8.5V) of the operational amplifier and comparator sections. 


26 


PHASE COMP C3 


I 


IRIS operational amplifier for phase correction. 


27 


PHASE COMP C4 


I 


IRIS operation amplifier for phase correction. 


28 


Vcc4 




Power source (5V) of a portion of the white balance system and the bias 
circuit section. 


29 


IRIS BIAS output 





Reference voltage output to be input to pin @ . It is possible to be 
controlled by pin @ . 


30 


IRIS DET output 


I 


Negative input of the IRIS operational amplifier. 


31 


IRIS BRAKE 


I 


Positive input of the IRIS operational amplifier. 


32 


GND4 




Ground of a portion of the white balance system and the bias circuit. 


33 


IRIS DRIVE 





Output of the IRIS operational amplifier. 


34 


LED DRIVE 





Output to drive the externally attached LED by comparing the output of the 
AGC operational amplifier with the voltage of pin @ . 



I 



-505 



SONY® 



CX20056 



No. 


Symbol 


I/O 


Description 


35 


R-G COMP output 





Output comparing the level of R signal with that of G signal. Input into 
white balance IC (CX-7938). 


36 


B-G- COMP output 





Output comparing the level of B signal with that of G signal. Input into 
white balance IC (CX-7938). 


37 


IRIS SET 




Input which adjusts the output voltage of pin @ . 


38 


AGC SET 




Input which adjusts the output voltage of pin @ . 


39 


LLL SET 




Input which determines the voltage to light the LED. 


40 


R OFFSET 




Input in order to match R signal with G signal. 


41 


B OFFSET 




Input in order to match B signal with G signal. 


42 


DET Cr 





Output of peak detect voltage of R signal. 


43 


GND2 




Ground a portion of the white balance section. 


44 


DET Cb 





Output of peak detect voltage of B signal. 


45 


DET Cg 





Output of peak detect voltage of G signal. 


46 


XVD 


I 


Input of pulse to reset peak detection circuit. 


47 


ID 


I 


Input of pulse to separate the R/B line sequential signal. 


48 


WINDOW 


I 


Input of pulse which extracts 1/9 portion (1/3 in H-direction and 1/3 in V- 
direction) of signal from the entire image. 



-506- 



SONY® 



CX20056 



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509- 



SONY® 



CX20056 




510 



SONY® 



CX20056 



Input Waveform and Input Pulse 



SG1 



SG2 




"AAAAAAAAAAAAAfflU 



PG1 



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2ms 



PG2 

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PG4 



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1VD = 16.7mr 



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4.2V 



I Variable 

I (200 to 800mVp-p) 



300mVp-p 
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100mVp-p 
Frequency variable 



-511 



SONY® 



CX20056 








it) 
2 o 

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512- 



SONY® 



CX20056 



Reference Pin Voltage (DC) 



See Test Circuit 

During non-signal 

Ta=25°C, Vcd =8.5V, Vcc2 to 4=5.0V 



No. 


Voltage(V) 


No. 


Voltage(V) 


No. 


Voltage) V) 


1 


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17 


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33 


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36 


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37 


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6 


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38 


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46 


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31 


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47 


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16 


2.00 


32 


(0 GND)*1 


48 


(5.0 WIND0W)*2 



*1) The pin voltage in parentheses is applied externally. 

*2) The pin voltage in parentheses is an input pin; however, DC is applied to it. 

*3) The pin voltage in parentheses is in non-signal state to which DC is applied. 

*4) The voltage when the output voltage of pin 33 is so adjusted that it becomes 3(V). 

*5) The voltage when the output voltage of pin 16 is so adjusted that it becomes 2(V). 



I 



513 



SONY® 



CX20056 



*" — vyr— " 



XVD FROM CX-7938> 



ID FROM CX-7967> 



WINDOW 

FROM CX-7938 




-514 



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515 - 



SONY® 



CX20056 





AGC 


OUT vs 


. AGC 


SET 






































































1 


' 






































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SET 





































































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G DET 



AGC SET voltage (V) 
Fig. 1 

1)DET vs. b)OFF SET 




IRIS SET voltage (V) 
Fig. 2 

DET peak voltage vs. G/R/B IN 






R/B OFFSET voltage (V) 
Fig. 3 

AGC\ „■««» «..,- AGCn _,„, 
IR.S ) B ' AS ° UT VS - IR.S^ SET 





































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AGC (IRIS) SET voltage (V) 
Fig. 5 



Input signal amplitude (mV) 
Fig. 4 

(DET Cg) - (DET Cr ( b)) 

vs. Supply voltage 




4.9 5.0 5, 

Supply voltage (V) 
Fig. 6 



516 



SONY® 



CX20056 



AGC (IRIS) DET IN peak voltage 

vs. Supply voltage 





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3.7 
3.6 
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Fig. 7 



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(R-G) 































































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Ambient temperature (°C) 
Fig. 8 



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20 40 60 80 100 120 140 160 

R {a) 
Fig. 10 



-517 



SONY® 



CX20056 



No. 


DC [V] 


AC [V] 


Impedance [n] 


Remarks 


1 


0.1 


4.0 Vp-p 


>100k 






H period 








2 


5.0 






Vcc2 


3 


2.9 




<50 




4 


3.0 




<50 




5 


2.9 




<50 




6 


4.2 


0.32 Vp-p 


>100k 


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7 


4.2 


0.38 Vp-p 


>100k 




8 


4.2 


0.38 Vp-p 


>100k 


k— 2H — < 


9 


2.6 




<50 




10 


2.7 




<50 




11 


4.0 


0.1 6 Vp-p 


>100k 


Q-ZK 1 


12 


4.0 


0.36 Vp-p 


>100k 


cs^ 


13 


3.0 


3.7 Vp-p 


>10k 




u 


H period 


14 


2.8 


1.8 Vp-p 


<200 


K— 2H — •* 


15 


2.7 


1 .0 Vp-p 


<200 




16 


7.4 




<10 




17 


5.0 






Vcc3 


18 


3.4 




>100k 




19 









GND 


20 


1.7 




>100k 




21 


1.2 




<200 




22 









GND 


23 


3.0 




>100k 


Indicates AC impedance 


24 


8.1 




>100k 


Indicates AC impedance 


25 


8.5 






Vcd 


26 


3.6 




>100k 


Indicates AC impedance 


27 


4.3 




>100k 


Indicates AC impedance 


28 


5.0 






Vcc4 


29 


2.5 




<200 




30 


3.1 




>100k 




31 


3.0 




>100k 




32 









GND 



-518- 



SONY® 



CX20056 



No. 


DC [V] 


AC [V] 


Impedance [O] 


Remarks 


33 


4.8 




<10 




34 


0.1 






Open collector 


35 


0.1 




>7k 




36 


0.1 




>7k 




37 


2.4 




>100k 




38 


2.5 




>100k 




39 


5.2 




>100k 




40 


2.5 




>100k 




41 


2.5 




>100k 




42 


1.7 




>1k 




43 











44 


1.7 




>1k 




45 


1.7 




>3k 




46 


0.1 


4.8 Vp-p 


>30k 






H period 




47 


2.0 


4.8 Vp-p 


>100k 


•- — 2H — H 


48 


4.7 




>6k 





I 



519 



SONY® 



CX20056 



Package Outline Unit : mm 

CX20056 48 pin QFP (Plastic) 0.7g 



D15.3 ±0 - 4 



+ 0.0 5 

0.1 5 - o.o i 




QFP-48P-L022 



520- 



SONY, 



CX20151 



Matrix for Color Camera 



Description 

CX20151 is a bipolar IC which has been developed to 
obtain Ya and Yl-Yh luminance signal outputs and R-Y and 
B-Y chroma signal outputs by inputting G signal and R/ 
B signals, and connecting to 1 H DL, for the G vertical striped 
R/B line sequential type color camera. Composed of circuits 
such as clamp, sampling hold for waveform shaping, DC 
bias adjustment of 1H DL input, 1H DL gain adjustment, 
multiplexer, color-difference (R-Y and BY) signal forming, 
color-difference (R-Y and BY) signal mixing, luminance low 
band width (Yl) signal forming, luminance high band width 
(Yh) signal forming, luminance (Yl-Yh) signal forming, V 
aperture control, switchover sample hold, color-difference 
signal blanking, ECL conversion, etc. 



48 pin QFP (Plastic) 




Features 

Together with CX20053, CX20055 and CX20056, it is 
possible to compose a consistent color camera signal 
processing system. 

Structure 

Bipolar silicon monolithic IC 

Block Diagram 







o 

4 


< 
z 




D 




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2 

3 




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RinA Jlp]_^_ _jj 




. MPX DC AJ 



B-Y DC OFFSET 



R-Y DC OFFSET 



E89664 - ST 



521 



SONY® 



CX20151 



Absolute Maximum Ratings (Ta=25°C) 

• Power supply voltage Vcc1 to 3 

• Operating temperature Topr 

• Storage temperature Tstg 

• Allowable power dissipation 

Pd 

Recommended Pulse Input Level 



Pin No. 


Input level 


15 


CMOS level 


16 


CMOS' level 


17 


CMOS level 


18 


CMOS level 


20 


CMOS level 



CMOS Level 



Vh 


Min. 


Max. 


Unit 


4.0 


5.0 


V 


Vl 





0.4 


V 



17 


V 


-20 to +75 


°C 


-55 to +150 


°C 



850 mW 

Input Pin Maximum Voltage 



Pin No. 


Voltagef V) 


Pin No. 


Voltage(V) 


Pin No. 


Voltage(V) 


1 


^Vcd 


24 


^Vcc2,3 


32 


^Vcd 


2 


^Vcd 


25 


^Vcc2,3 


33 


^Vcd 


3 


^Vcc2,3 


26 


^Vcc2,3 


42 


^Vcc2.3 


11 


^Vcd 


27 


^Vcc2,3 


44 


^Vcc2,3 


12 


^Vcc2,3 


28 


^Vcd 


45 


^Vcc2,3 


13 


^Vcc2,3 


29 


^Vcc2,3 


46 


^Vcc2,3 


22 


^Vcd 


30 


^Vcc2,3 


48 


^Vcc2,3 


23 


^Vcc2,3 


31 


^Vcd 


^-^ 





Recommended Operating Conditions (Ta=25°C) 

• Vcd 8.5 ± 0.4 V 

• Vcc2 5.0 ± 0.2 V 

• Vcc3 5.0 ± 0.2 V 



Pin Configuration 




Y L -Y H OUT 

G-B OUT 

G-R OUT 

B-Y GAIN ADJ 

REFERENCE 

R-Y GAIN ADJ 

B-Y DC OFFSET 

R-Y DC OFFSET 

Y H OFFSET 

MPX DC ADJ 

R2/B2 GAIN ADJ 

G2 GAIN ADJ 



!i U w O u> > 



Fig. 1 



-> ± o 



O O - - 



522- 



SONY® 



CX20151 



Pin Description 



No. 



10 



11 



12 



13 



14 



15 



16 



17 



18 



19 



Symbol 



R-Y MIX C. 



B-Y MIX C. 



APERTURE C. 



CLP DC 



RO/BO OUT 



R1/B1 OUT 



R2/B2 OUT 



G2 OUT 



G1 OUT 



GO OUT 



COM IN 



RO/BO y IN 



GO y IN 



BLK pulse 



ID pulse 



CLP pulse 



SH1 



GND1 



I/O 



Description 



Pin to mix R-Y signal to B-Y signal output of pin @ by applying DC 
potential (2.0 to 3.0V). Positive/Negative adjustment; 2.5V center. In 
case of open state, biased approximately 1.8V internally and mixing 
cannot be performed. 



Pin to mix B-Y signal to R-Y signal output of pin ® by applying DC 
potential (2.0 to 3.0V). Positive/Negative adjustment; 2.5V center. In 
case of open state, biased approximately 1.8V internally and mixing 
cannot be performed. 



Adjust V direction aperture level which is applied to — Yl signal output of 
pin @ by applying DC potential (2.0 to 3.0V). Aperture is turned off at 
2.0V. 



Output DC of internal clamping circuit. 
Connect to ground through a capacitor. 



Signal input from pin © is sampled by sample and hold pulse of pin 
@ , and is output after DC adjusted by pin @ . __ 



Signal input from pin @ is gain controlled by pin @ , and is output 
after DC adjusted by pin @ . 



Signal input from pin © is gain controlled by pin @ and then is 
output. 



Signal input from pin @ is gain controlled by pin @ and then is 
output. • 



Signal input from pin @ is gain controlled by pin 
after DC adjusted by pin @ . 



and is output 



Signal input from pin © is sampled by sample and hold pulse of pin 
@ , and is output after DC adjusted by pin @ . 



Signal input pin to compare with DC which has been input to pin (22) 
ex. When GO (pin @ ) is connected, GO output DC potential wil 
become equal to input DC of pin <£? • 



Input R/B line sequential signal of 0.35 Vp-p through a clamping 
capacitor. ^^ 



Input G signal of 0.35 Vp-p through a clamping capacitor. 



Capacitor pin for holding comparator output to compare pin © input 
with DC potential of pin @ input. Normally, a capacitor is inserted 
between it and the power supply. 



Input BLK pulse when application of color-difference blanking is desired. 
When unnecessary, connect to 5V. 



I 



Input pulse: L; R signal H; B signal. 



CLP pulse input to clamp the input signals of pins © , @ , ® , 

® , ® . @ and @ . The comparison between pin © input 

and pin @ input is also performed with this pulse. 



Input sample and hold pulse for sampling of input signal of pin © and 
also for switchover sample and hold. 

Ground 



-523- 



SONY® 



CX20151 



No. 


Symbol 


I/O 


Description 


20 


SH2 


I 


Input sample and hold pulse for input signal of pin @ for sampling use 
and also for switchover of sample and hold use. 


21 


Vcc3 




5.0V power supply for ECL conversion and also for pulse section input. 


22 


DC ADJ for DL 




Adjust the DC of output signals of pins © , © , ® and @ by 
applying DC potential (3.0 to 6.0V). (Output by clamping the potential 
applied to this pin.) 


23 


G1 GAIN ADJ 




Adjust the gain of pin ® output signal by applying DC potential (2.0 to 
3.0V). 


24 


R1/B1 GAIN ADJ 




Adjust the gain of pin © output signal by applying DC potential (2.0 to 
3.0V). 


25 


G2 GAIN ADJ 




Adjust the gain of pin ® output signal by applying DC potential (2.0 to 
3.0V). 


26 


R2/B2 GAIN ADJ 




Adjust the gain of pin © output signal by applying DC potential (2.0 to 
3.0V). 


27 


MPX DC ADJ 




Eliminate the DC offset at the multiplexer circuit section by applying DC 
potential (2.0 to 3.0V). 


28 


Yh OFFSET 




Eliminate the DC offset of Yh switchover sample and hold circuit section 

by applying DC potential (4.0 to 5.0V). 

Normally, it is permissible in the open state (biased internally). 


29 


R-Y DC OFFSET 




Eliminate the DC offset of R-Y signal at BLK term by applying DC 
potential (2.0 to 3.0V). In case of NO BLK, it is permissible in the open 
state (biased internally).- 


30 


B-Y DC 




Eliminate the DC offset of B-Y signal at BLK term by applying DC 
potential (2.0 to 3.0V). In case of NO BLK, it is permissible in the open 
state (biased internally). 


31 


R-Y GAIN ADJ 




Adjust the gain of R-Y signal output of pin ® by applying DC potential 
(2.0 to 3.0V). 


32 


REFERENCE 




When fade-in and fade-out are desired of the chroma (R-Y and B-Y) 
signal, input fader signal. If fade-in and fade-out do not function, it is 
permissible in the open state (biased internally). 
Note) When performing fading, R-Y and B-Y signals mixed with pin © 
and pin © , then do not perform fade-in and fade-out operations. 


33 


B-Y GAIN ADJ 


I 


Adjust the gain of B-Y signal output of pin @> by applying DC potential 
(2.0 to 3.0V). 


34 


G-R OUT 





Output G-R color-difference signal synchronized by the multiplexer 
circuit. 


35 


G-B OUT 





Output G-B color-difference signal synchronized by the multiplexer 
circuit. 


36 


Yl-Yh OUT 





Output Yl-Yh signal. 


37 


Yh OUT 





Output Yh signal which has been switchovered and sampled and held. 
[Yh=0.25(GO+G1 +R0/B0+R1/B1 )] 


38 


-Yl OUT 





Output YL signal by negative polarity. 
[Yl=-0.3(G-R)-0.1 (G-B) + G1 +A(-G0-G2+G1 )] 
A: Adjust with pin © . 



524- 



SONY® 



CX20151 



No. 


Symbol 


I/O 


Description 


39 


B-Y OUT 





Adjust gain with pin © and output B-Y signal in which the mixed 
volume of R-Y has been adjusted by pin (T) . 
[B-Y=0.3(G-R)-0.9(G-B)±A[0.1(G-B)-0.7(G-R)] 
A: Adjust with pin (?) . 


40 


R-Y OUT 





Adjust gain with pin @ and output R-Y signal in which the mixed 
volume of B-Y has been adjusted by pin @ . 
[R-Y=0.1(G-B)-0.7(G-R)±[0.3(G-R)-0.9(G-B)] 
A: Adjust with pin © . 


41 


Vcd 




8.5V power supply 


42 


R2/B2 IN 


1 


Input R/B linesequentialsignal delayed 2H through a clamping 
capacitor. 


43 


GND2 




Ground 


44 


G2 IN 


1 


Input G signal delayed 2H through a clamping capacitor. 


45 


Dummy DC 


1 


DC input corresponding to pins @ , @ , @ , @ , @ and @ , 
connect to power supply or GND through a capacitor. 


46 


R1/B1 IN 


1 


Input R/B linesequentialsignal delayed 1 H through a clamping capacitor. 


47 


Vcc2 




5.0V power supply signal processing system. 


48 


G1 IN 


1 


Input G signal delayed 1 H through a clamping capacitor. 



I 



-525 



SONY® 



CX20151 



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-527- 



SONY® 



CX20151 



Electrical Characteristics 






(Ta=25°C, Vcd=8.5V, Vcc2 


=Vcc3= 


5.0V, S 


ee Fig. 2) 


Symbol 


Item 


Measuring 
point 


Condition 


Min. 


Typ- 


Max. 


Unit 


DC1 


DC check 


V1 


DC potential of pin 1 


1.5 


1.8 


2.1 


V 


DC2 


DC check 


V2 


DC potential of pin 2 


1.5 


1.8 


2.1 


V 


DC3 


DC check 


V4 


DC potential of pin 4 


2.4 


2.7 


3.0 


V 


DC4 


DC check 


V28 


DC potential of pin 28 


3.9 


4.3 


4.7 


V 


DC5 


DC check 


V29 


DC potential of pin 29 


2.2 


2.5 


2.8 


V 


DC6 


DC check 


V30 


DC potential of pin 30 


2.2 


2.5 


2.8 


V 


DC7 


DC check 


V32 


DC potential of pin 32 


2.2 


2.5 


2.8 


V 


11 


Circuit current 
(5.0V) 


A1 


Circuit current of 5.0V group 


18.1 


25.0 


32.6 


mA 


12 


Circuit current 
(8.5V) 


A2 


Circuit current of 8.5V group 


11.4 


15.0 


18.9 


mA 


G1 


GO gain 


V10 


Pin 10 0UT/S1 


1.0 


1.2 


1.4 




G2 


RO/BO gain 


V5 


Pin 5 0UT/S2 


1.0 


1.2 


1.4 




DC8 


GO output DC 
range 


V10 


DC potential of pin 10 OUT 
when E1 is set to 3.5V and 
6.0V 


3.33 


3.5 


3.68 


V 


DC9 




1 


5.68 


6.01 


6.34 


V 


DC10 


RO/BO output DC 
range 


V5 


DC potential of pin 5 OUT 
when E1 is set to 3.5V and 
6.0V 


3.26 


3.53 


3.82 


V 


DC11 


1 


1 


5.60 


6.02 


6.46 


V 


DC12 


G1 output DC 
range 


V9 


DC potential of pin 9 OUT 
when E1 is set to 3.5V and 
6.0V 


3.28 


3.56 


3.85 


V 


DC13 


I 


5.61 


6.03 


6.49 


V 


DC14 


R1/B1 output DC 
range 


V6 


DC potential of pin 6 OUT 
when E1 is set to 3.5V and 
6.0V 


3.28 


3.56 


3.85 


V 


DC15 






5.59 


6.01 


6.45 


V 


DC16 


Dispersion among 
4 channels 




1 


DC10-DC8, DC12-DC8, 
DC14-DC8 


-85 


50 


210 


mV 


G3 


G1 gain 
control range 


V9 


Pin 9 PUT/S1 







0.16 


mV 


G4 


1 




1.48 


1.68 


1.89 




G5 


R1/B1 gain 
control range 


V6 


Pin 6 0UT/S3 







0.16 




G6 






1.48 


1.68 


1.89 




G7 


G2 gain 
control range 


V8 


Pin 8 0UT/S1 







0.16 




G8 


1 




1.48 


1.68 


1.89 




G9 


R2/B2 gain 
control range 


V7 


Pin 7 0UT/S2 







0.16 




G10 


i 


1.48 


1.68 


1.89 




G11 


G-R amplifier gain 


V34 


Pin 34 0UT/S1 


0.95 


1.20 


1.47 




R1 


Color-difference 
composition ratio 


V35 


Pin 34 OUT/ 

Pin 35 OUT of G1 1 


1.78 


1.98 


2.21 




R2 


1 




1.78 


1.98 


2.21 




DC17 


MPX variable 
range 


' 




A (See p. 16) 


-76 


-160 


-252 


mV 


DC18 


' 




+86 


+ 170 


+263 


mV 


G12 


R-Y amplifier gain 


V40 


Pin 40 0UT/S1 


0.31 


0.48 


. 0.66 




G13 


1 


1.14 


1.43 


1.71 





528- 



SONY® 



CX20151 



Symbol 


Item 


Measuring 
point 


Condition 


Min. 


Typ. 


Max. 


Unit 


R3 


R-Y composition 
ratio 


■' 


Pin 40 out/ 

Pin 40 OUT of G13 


5.8 


6.7 


7.6 




DC19 


R-Y DC offset 


V40 


B (See p.16) 


48 


100 


158 


mV 


DC20 


■ 




-173 


-115 


-63 


mV 


G14 


B-Y MIX gain 


" 


Pin 40 OUT/S1 
Note) Output during 
E14=22V is negative 
polarity. 


0.19 


0.28 


0.40 




G15 




1 


0.28 


0.37 


0.48 




G16 


B-Y amplifier gain 


V39 


Pin 39 0UT/S1 


0.4 


0.5 


0.6 




G17 






1.3 


1.6 


1.9 




R4 


B-Y composition 
ratio 




< 


Pin 39 OUT/ 

Pin 39 OUT of G17 


2.61 


3.0 


3.41 




DC21 


B-Y DC offset 




■ 


C (See p.16) 


43 


95 


152 


mV 


DC22 


' 




-163 


-105 


-52 


mV 


G18 


R-Y MIX gain 


V39 


Pin 39 OUT/S1 
Note) Output during 
E13=2.8V is negative 
polarity 


0.18 


0.26 


0.35 




G19 




' 


0.27 


0.34 


0.42 




G20 


— Yl amplifier gain 


V38 


Pin 38 OUT/S1 


1.0 


1.3 


1.6 




R5 


— Yl composition 
ratio 


■ 


1 


Pin 38 OUT/ 

Pin 38 OUT of G20 


8.6 


10.5 


12.6 




R6 




' 


2.9 


3.3 


3.8 




G21 


V aperture 
control gain 




• 


Measure pin 38 OUT during 
E15= 2.0V and 3.0V, and 
caluculate (output during 
3.0V — output during 
2.0V)/2 












1 


170 


255 


340 


mV 


G22 


Yh amplifier gain 


V37 


Pin 37 OUT/S1 


1.9 


•2.45 


3.0 






Yh composition 
ratio 




1 


Set pin 37 OUT to a 

Set pin 37 OUT to b and 

obtain b/a 

Set pin 37 OUT to c and 

obtain c/a 

Set pin 37 OUT to d and 

obtain d/a 










R7 




' 


0.5 


1.0 


1.5 




R8 




1 


0.5 


1.0 


1.5 




R9 




' 


0.5 


1.0 


1.5 




DC23 


Yh DC offset 




■ 


D (See p.16) 







105 


mV 


DC24 


Yh DC variable 
range 






E (See p.16) 


323 


620 


945 


mV 


DC25 




1 


494 


810 


1155 


mV 


G23 


Yl-Yh gain 


V36 


Pin 36 OUT/S1 


0.34 


0.45 


0.57 




DR1 


GO D.R 


V10 


Pin 10 OUT/S4 


1.05 


1.18 


1.32 




DR2 


RO/BO D.R 


V5 


Pin 5 OUT/S5 


1.05 


1.18 


1.32 




DR3 


G1 D.R 


V9 


Pin 9 OUT/S4 


1.40 


1.57 


1.75 




DR4 


R1/B1 D.R 


V6 


Pin 6 OUT/S6 


1.40 


1.57 


1.75 





529- 



SONY® 



CX20151 



Symbol 


Item 


Measuring 
point 


Condition 


Min. 


Typ. 


Max. 


Unit 


DR5 


G2 D.R 


V8 


Pin 8 0UT/S4 


1.40 


1.57 


1.75 




DR6 


R2/B2 D r R 


V7 


Pin 7 0UT/S5 


1.40 


1.57 


1.75 




DR7 


R-Y D.R 


V40 


Pin 40 0UT/S4 


1.3 


1.7 


2.1 




DR8 


B-Y D.R 


V39 


Pin 39 0UT/S4 


1.57 


1.85 


2.15 




DR9 


-Yl D.R 


V38 


Pin 38 0UT/S4 


1.10 


1.26 


1.43 




DR10 


Yh D.R 


V37 


Pin 37 0UT/S4 


1.9 


2.28 


2.69 




DR11 


Yl-Yh D.R 


V36 


Pin 36 0UT/S4 


0.38 


0.465 


0.56 




DR12 


line DR ratio 


V10.5 


DR2/DR1 


0.8 


1.0 


1.2 




DR13 


1 line DR ratio 


V9.6 


DR4/DR3 


0.8 


1.0 


1.2 




DR14 


2 line DR ratio 


V8.7 


DR6/DR5 


0.8 


1.0 


1.2 





-530 



SONY® 



CX20151 





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w 



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CO °- 



CJ <» 

■E £ & 

co en <|> 

o ^ ° 

S E ■= 

O c CO 

0. CO UJ 



531 - 



SONY® 



CX20151 



Electrical Characteristics Test Circuit 



A t- ft fr fr A A A A IT *T ?T 

SW13 SW12 



E3 




SW15 

--©-^sws f y f 

. I " ' tT1* ' CM ' IT 

5.0V° 



4 ii • * 



O— 1| 1 

b *- 
SW2 o-(s; 



Fig. 2 



-532 



SONY® 



CX20151 



Bias Condition Definition 



(1) ST2: E2 potential in which the output p-p of pin 9 becomes equivalent to output p-p of pin 10. 

(2) ST3: E3 potential in which the output p-p of pin 6 becomes equivalent to output p-p of pin 5. 

(3) ST4: E4 potential in which the output p-p of pin 8 becomes equivalent to output p-p of pin 10. 

(4) ST5: E5 potential in which the output p-p of pin 7 becomes equivalent to output p-p of pin 5. 

(5) ST10: E10 potential in which the output p-p of pin 40 becomes 400 mV. 

(6) ST12: E12 potential in which the output p-p of pin 39 becomes 400 mV. 



Condition A 



Constant (V) 



^ 



Vp-p = V1 - V 



Waveform similar to P2 is output to pin 35 as shown in above figure. DC is constant when P2 is H. Measuring of V1 has 
been performed when E6 is set to 2.0V and 3.0V, and the Vp-p has been calculated. 



Condition B and C 



-r 



M 



Constant (V) 



GND 



Vp-p = V1 - V 



(V1) 



Waveform similar to P1 is output to pins 40 and 39 as shown in above figure. Measuring of V1 has been performed 
when E8 and E9 are set to 2.0V and 3.0V, and the Vp-p has been calculated. 

Condition D and E 



UUUUUUUII 



Vp-p 



Signal of 4.77 MHz is output to pin 37 as shown in the above figure. D measures this Vp-p. E varies the DC of pin 28 
with E7, and measuring is carried out on Vp-p of pin 37 output. 

(When the DC of pin 28 is varied, the Vp-p of pin 37 output fluctuates. In this case, confirm that there is a point of Vp-p=0 mV 
between E7=4.0V and 5.0V.) 



-533- 



SONY® 



CX20151 






t o 

O o 




_i 



" O ? </3 n? w 



a. ^ Q. — 



534 



SONY® 



CX20151 



Standard Circuit Design Materials 



(Ta=25°C, Vcc=8.5V, Vcc2=Vcc3=SV) 



No. 



Symbol 



Equivalent circuit 



DC 
potential 



R-Y Mix C. 



B-Y Mix C. 




1.8V 



APERTURE C. 



®c 



6ND i 



i)aop*. 



CI.P DC 



©o- 



w^ 



?® 



f 0K Q) 

[20QM<[ J 



11C-JJA 



2.7V 



10 
36 



37 
38 



39 
40 



RO/BO OUT 
R1/B1 OUT 
C1 OUT 
CO OUT 
Yl-Yh OUT 
Yh OUT 
-Yl OUT 
B-Y OUT 
R-Y OUT 
R2/B2 OUT 
C2 OUT 



V 



40OJ1A 



4 



V 



© 



i 



400yA 



-535 - 



SONY® 



No. 



Symbol 



Equivalent circuit 



DC 
potential 



11 



22 



COM. MM 



DC ADJ for DL 



8 X ^ 
(So , r ^1 c 


[ &° " k^. . ^A c 


1 

i i (T) 500uA J ^ 
GND—" A 



© 



12 



13 



42 



44 



45 



46 



48 



RO/BO r IN 



CO r IN 



R2/B2 In 



C2 IN 



Dummy DC 



R1/B1 IN 



C1 IN 




lJ110uA 



14 




15 



17 



BLK PULSE 



CLP PULSE 





16 



18 



20 



19 
21 



ID PULSE 



SH2 PULSE 



SH1 PULSE 



GND 1 
Vcc 3 




(T)110jjA 



5.0V 



- 536 



SONY® 



CX20151 



No. 



Symbol 



Equivalent circuit 



DC 
potential 



23 



24 



25 



26 



27 



G1 GAIN ADJ 



R1/B1 GAIN ADJ 



G2 GAIN ADJ 



R2/B2 GAIN ADJ 



MPX DC ADJ 




jjHOuA 




|)140uA 



28 



Yh OFFSET 




X)140iiA 



4.25V 



29 



30 



R-Y OFFSET 



B-Y DC OFFSET 




2.5V 



31 



33 



R-Y GAIN ADJ 



B-Y GAIN ADJ 




32 



REFERENCE 




2.5V 



-537- 



SONY® 



CX20151 



No. 


Symbol 


Equivalent circuit 


DC 
potential 


34 


G-R OUT 


Vcc2 










35 


G-B OUT 


;; 




~p35K 










® 

GND 


;: 


400.H 






41 


Vcc 1 




8.5V 


43 


GND 2 






47 


Vcc 2 




5.0V 



538 



SONY® 



CX20151 



Application Circuit 



8.5V 
O-f- 



10 it 
16V' 




-=E 






ojE 



).TTb, 



m 



ML 



Ol 



(TO LPF) 



io-)H 

16V 



r 



CX 20151 



13 14 15 16 17 18 19 20 21 22 23 24 



^13 14 1 

Jo.i J0.1J0.1 



^h 



r 48 47 46 45 44 43 42 41 40 39 38 37,^ 

1 o 



-iHh 



"atio - 



5.0V 

-o 



S; 10 

JJ*16V 



3.0V 
10 
16V 



10 
16V 



2.0V 
Q 



_/J^=-ii 



| aMt-> 



(i W-2hi 




_ _ AAA 

(FROM CX20053) (FROM CX23047A) 



Decoupling is performed to 0.1mF capacitors 28, 29, 30 and 31 (Can do without decoupling). 



Fig. 4 



539- 



SONY® 



CX20151 



G1. R1/B1, G2. R2/B2 
gain control characteristics 




Measuring has been carried out bv 
fluctuating tha bias of G2 to 65 within 
tha ranga of 2.0V to 3.0V, under tha SW 
condition of G3 of tha aforementioned 
Electrical Characteristics. 



G1. R1/B1, G2, R2/B2 «,„„., «, 
gain adjustment voltage (V) 



~ GO, R0/B0, G1, R1/B1 output 
£ DC control characteristics 



o 
a 

8« 






























































3 

a 

3 50 
O 










































-,.o 










































,_" 3.0 

O 










































S 2.0 























Measuring ha* bean carried out by 
fluctuating tha bias of El within tha 
ranga of 2.0V to 7.0V, under the SW 
condition of OC8 of the aforementioned 
Electrical Characteristics. 



v <c.w j.w "».w o.V b.W r-O 

o DC adjustment voltage for DL (V) 



MPX DC adjustment characteristics 



Yh offset characteristics 



^> 200 
> 

E 





























































































y 















































































































Measuring has been carried out by 
fluctuating bias of E6 within the range 
of 2.0V to 3.0V, under the SW condition 
of DC17 of the aforementioned Electri- 
cal Char acteristics. 




Measuring has been carried Out by 
fluctuating bias of E7 within the range 
of 3.8V to 4.8V, under the SW condition 
of OC24 of the aforementioned Electri- 
cal Characteristics. 



MPX DC adjustment voltage (V) 



YH offset adjustment voltage (V) 



R-Y DC offset characteristics 



BY DC offset characteristics 



Measuring has been carried out by 
fluctuating bias E8 within the range 
of 2.0V to 3.0V, under the SW condition 
of DC19 of the aforementioned Electri- 
cal Characteristics. 



Measuring has 
fluctuating bias 
2.0V to 3.0V, i 
of DC21 of the 
cal Character istti 



E9 within the range of 
inder the SW condition 
aforementioned Electri- 



R-Y DC offset adjustment voltage (V) 



BY DC offset adjustment voltage (V) 



540 



SONY® 



GX20151 



R-Y gain control characteristics 



BY gain control characteristics 



Measuring has bttn carried out by <j) 

fluctuating bias E10 within the range of £ 

2.0V to 3.0V, under the SW condition *^ 

of G12 of tha aforementioned Electrical ., 

Characteristic!. O 




Measuring has baan carried out by 
fluctuating bias E12 within tha range of 
2.0V to 3.0V, undar tha SW condition 
of G16of the aforementioned Electrical 
Characteristics. 



R-Y gain adjustment voltage (V) 



B-Y Mix control voltage (V) 



R-Y mix gain control characteristics 



BY mix gain control characteristics 



Measuring has bean carried out by 
fluctuating bias E13 within the range of 
2.0V to 3.0V, under the SW condition 
of G18of the aforementioned Electrical 



Measuring has baan carried out by 
fluctuating bias E14 within the range of 
2.0V to 3.0V, under the SW condition 
of G14of the aforementioned Electrical 
Characteristics. 



R-Y Mix adjustment voltage (V) 



B-Y Mix adjustment voltage (V) 



V aperture control gain control characteristics 

9. 





































































































/ 
















s 


y 





















































































Measuring has been carried out by 
fluctuating bias E1S within the range of 
2.0V to 3.0V, undar the G21 method of 
the aforementioned Electrical Charac- 



V aperture control adjustment voltage (V) 



-541 - 



SONY® 



GO, RO/BO OUT temperature characteristics 



G1, R1/B1 OUT temperature characteristics 



10 












































9 






















c 






















CO 

2 o 
3 


















































,c 






















O 



































































Ambient temperature (t) 



Ambient temperature (°C) 



G2, R2/B2 OUT temperature characteristics 



Auto bias temperature characteristics for DL 



CO 


> 


^ 


00 






■3 


< ) 


•*- 


o 


o 


»j 


O 





Ambient temperature CC) 



Ambient temperature (°C) 



G-R OUT temperature characteristics 



G-B OUT temperature characteristics 



Ambient temperature (°C) 



Ambient temperature (°C) 



-542 



SONY® 



CX20151 



R-Y OUT temperature characteristics 



B-Y OUT temperature characteristics 




Ambient temperature CC) 



Ambient temperature (°C) 



R-Y mix temperature characteristics (at BY OUT) 



BY mix temperature characteristics (at R-Y OUT) 



-20 20 40 60 60 

Ambient temperature (°C) 




Ambient temperature (°C) 



Yh OUT temperature characteristics 



Yl-Yh OUT temperature characteristics 



I 



Ambient temperature (°C) 



Ambient temperature (°C) 



543 



SONY® 



CX20151 



Yl OUT temperature characteristics 



V aperture control volume temperature characteristics 



Ambient temperature CC) 



Ambient temperature (°C) 



-544 



SONY® 



CX20151 



Package Outline Unit : mm 

CX20151 48 pin QFP (Plastic) 0.7g 



37 



48 



V 



o 



D15.3 10 - 4 




24 



13 



+ CU5 
0.8 0.3-0.1 



s 



12 



+ 0.1 
0.15 -0.0 5 



HZ71 o.i5 



22-0.15 



+ 0.2 

0.1- o.i 



™. I 



QFP-48P-L04 



-545 



SONY. 



CX23039 



1 H X 4 CCD Delay line IC 



Description 

The CX23039 is a CMOS CCD signal processor which 
has been developed for the CCD camera. 

The IC contains four 1 H delay lines, clock drivers, the 
autobias circuit, and the pedestal clamp circuit etc. 

Features 

• Low power consumption (Typ. 210mW) 

• On Chip peripheral circuits 



Package Outline 



Unit: mm 



28 Pin MFP 



19.2 MAX 



27 MAX 



3 H H B fl B B B B fl B B B (T 


, 


- 


28 15 
lO 14 


x"2 
< ° 


n 

01 


yyyyyyyyyyyyyii 




0.45 -41* -4-« 


1-1.27 




J 13x1.27 = 16.51 


0.15 




+ 0.05 

- 0.03 in 



-4i*-r$1 ± °- 12 



Absolute Maximum Ratings (Ta=25°C) 



• Power supply voltage 




Vdd 
Vcl 




11 
6 




V 
V 






■ Operating temperature 

• Storage temperature 

. Allowable power dissipation 


Topr 
Tstg 
Pd 


-10 
-55 


~ +60 °C 
~ +150 °C 
500 mW 






Recomended Power Supply Conditions 

• Power supply voltage 1 Vod 

• Power supply voltage 2 Vcl 


8.75 
4.75 


~ 


9.25 
5.25 


V 
V 






Recomended Clock Conditions 


Min 








Typ. 


Max. 




• Clock voltage Low 
> Clock voltage High 

• Clock frequency 


Vl 
Vh 

fCL 


Vcl— 


1.0 







4.77 


0.4 


V 
V 
MHz 



50169-ST 



-546- 



SONY® 



CX23039 



Block Diagram 



CLP 




VDD v ss SUB 



547 



SONY® 



CX23039 



Pin Configuration 



CLP 


O o 


GO 


SUB 


SH2 


CO 


GO 


XDL2 


PLOUT 


CO 


GO 


vss 


PLIN 


CO 


(tti) 


NC 


V D D 


CO 


GO 


NC 


OUTA 


CO 


GO 


INA 


OUTB 





GO 


INB 


OUTD 


CO 


© 


IND 


OUTC 


CO 


GO 


INC 


v S s 


no) 


GO 


NC 


V C L 


00 


GO 


AIN 


A OUT 


© 


GO 


NC 


SH1 


Ms) 


GO 


VDD 


V G G 


GO 


GO 


XDL1 



(Top View) 



548 



SONY® 



CX23039 



Pin Description 



Pin No. 


Symbol 


I/O 


Description 


Impedance [fl] 


1 


CLP 


I 


Clamp pulse input 


>100K 


2 


SH2 


I 


Sampling pulse input 2 


>100K 


3 


PLOUT 





DC feedback output 


50 K 


4 


PLIN 


I 


DC feedback input 


>100K 


5 


Vdd 




Power supply 1 




6 


OUTA 





Signal output A 


1.2K 


7 


OUTB 





Signal output B 


1.2K 


8 


OUTD 





Signal output D 


1.2K 


9 


OUTC 





Signal output C 


1.2K 


10 


Vss 




GND 




11 


Vcl 




Power supply 2 




12 


AOUT 





Autobias circuit output 


20K 


13 


SH1 


1 


Sampling pulse input 1 


>100K 


14 


Vgg 


1 


Output circuit bias 


>100K 


15 


XDL1 


1 


Clock pulse input 1 


>100K 


16 


Vdd 




Power supply 1 




17 


NC 








18 


AIN 


1 


Autobias circuit input 


>100K 


19 


NC 








20 


INC 


1 


Signal input C 


>100K 


21 


IND 


1 


Signal input D 


>100K 


22 


INB 


1 


Signal input B 


>100K 


23 


INA 


1 


Signal input A 


>100K 


24 


NC 








25 


NC 








26 


Vss 




GND 




27 


XDL2 


1 


Clock pulse input 2 


>100K 


28 


SUB 




GND 





549- 



SONY® 



CX23039 



■—■r 






— r 














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cc 

!E 
a 
a 
U 


a 
« 

o 
> 


u 

c 

CD 

u. 


3: 

CD 
CD 

c 
_ 1 


CD 
CD 

C 
_l 


cc 

CD 

c 


o 

c 
i 
O 


CO 

E 

c 

CO 
C5 


.1 

CD 
CD 

c 
_l 


.| 

CO 
CD 

C 
_1 


1 

CD 
CD 

C 
_l 


Q c 

a s 

3 OJ 

O -Q 



550- 



SONY® 



CX23039 



Note 1 Measuring method of L1 , L2 and L3 

In the measurement of L1 , set input bias E1 to Vab+0.65V first, and then set it to Vab +0.85V and Vab 
+0.45V by shifting ±200mV from the first value respectively. Then input the sine wave of Sin=1 MHz and 
200mVp-p, and compare the three output amplitudes. 



El 

Input signal 



V AB + °-65V 
-200mV +200mV 




600mV 



Define the maximum output amplitude as SouTmax, and minimum output amplitude as SouTmin, and output 
amplitude on E1=Vab+0.65V as SouTm and define L1 as follows: 

U = S0UTm,» — SoUTmin y 1 qq^ 
SOUTm 

Similarly, define L2 and L3 by changing E1. 

Accordingly, measurement is performed at nine points by changing the input bias level at each delay 

line. 



Measuring point 



V AB V A B + 0-2V V AB +0.3V V AB + 0.65V 
— O o— — O O 



Input bias E1 



L2 
L3 



O K> "O 

200mV 200mV 



o o o 
o o o 



I 



551 - 



SONY® 



CX23039 



Note 2 The voltage gain of A channel is defined as follows: 

G(A)=20 log Q ^ 

Similary, voltage gains of channels B. C and D are defined as G(B). G(C) and G(D) respectively. 
The gain mismatch (AG) is defined as follows: 



AG = 



10 



10 



Gmax 
20 

10 +10 



X 200 [%] 



where Gmax is the maximum value of G(A), G(B), G(C) and G(D), and Gmin is the minimum value of G(A), 
G(B), G(C) and G(D). 

Note 3 Define the linearity 1 values of channels A, B. C and D as L1 (A), L1 (B), L1 (C) and L1 (D). Define the maximum 
value of L1(A), L1(B), L1(C) and L1(D) as Umax and minimum value of those as L1 min. The linearity 
mismatch 1(AL1) is defined as follows: 

AL1 = L1 max — L1 min [%] 
Similarly, define the maximum values of the 4 channels A, B, C and D of linearity 2 and linearity 3 as L2 max 
and L3 max respectively and define minimum values of those as L2min and L3min respectively. 
The linearity mismatch 2(Al_2) and the linearity mismatch 3(AL3) are defined as follows: 

AL2 = L2max - L2min [%] 

AL3 = L3max — L3min [%] 

Note 4 Set input bias to E1 =Vab+0.3V. Define output DC voltage of cannels A. B. C and D as Vdc(A). Vdc(B), 
Vdc(C) and Vdc(D) respectively. The output DC voltage difference between channels (AVdc).s defined as 

AVDC = VDCmax — VDCmin 

where VDCmax is the maximum value of Vdc(A), Vdc(B), Voc(C) and Vdc(D) and Vocmin is the minimum value 
of Vdc(A), Vdc(B), Vdc(C) and Vdc(D). 



-552- 



SONY® 



CX23039 



=A 



* 
u. 

0. 



10 
IO CM A 




HV\NH|— fe 




I 



-553- 



SONY® 



CX23039 



Clock Waveform and Timing Diagram 



175nS<T<210nS 



XDL1 



XDL2 



10nS 



90% 



70nS < t1 < 90nS 



1 T 3 70nS < t1 < 90nS 

H »H H 



50% 



I t4 40nS < t2 < 50nS 



t4 40nS < t2 < 50nS 



nS 10nS 

.! F 



90% 



90% 



50% 



5V 



10% 



t3 = 
t4 = 



2 

t1 -t2 



554- 



SONY® 



CX23039 



Clamp Pulse Waveform and Timing Diagram 




600mVp-p 













Frequency charact 


ens 


tie 


:s 





































































































-1 






























m 
■o 






























c 
to 






























O 






























-3 
























I 




































































I 



100K 
Signal frequency [Hz] 



-555 



SONY® 



CX23039 



Voltage gain vs Vdd 



Frequency response vs Vdd 



2 
























































































c 






















8> 






















o *' 

> 






















-2 










































- s 




































































ffi 






















o 






















§ " 2 
Q. 






















i 3 






















3 






















LL 



































































9.0 
V DD <V) 



9.0 
V DD (V) 



Linearity vs Vdd 



Output DC voltage vs Vdd 





























































































L3 




















L2 




















L1 







































































9.0 
V DD (V) 



4.3 














































































































4.0 
























































































3.S 























9.0 

v D d (v) 



556 



SONY® 



CX23039 



Voltage gain vs Vcl 



Frequency response vs Vcl 



2 


































































CO 

"O - 






















— o 

c 

& 






















I , 






















o 

> 

























































































5.0 

v C l (v) 
















































m 






















1 2 






















1 






















& 




















3 

u. 
































































-5 





















5.0 

v C l <v) 



Linearity vs Vcl 



Output DC voltage vs Vcl 


















































































































5 




L3 




















L2 






























L1 








































































4.S 














































































































4.0 
























































































S B 























5.0 

v C L (v) 



5.5 



5.0 

v C l <v) 



557 



SONY® 



CX23039 



Voltage gain vs Ambient temperature 



Frequency response vs 

Ambient temperature 





2 
1 


-1 
-2 

-3 


































































m 

T) 






















C 

a 






















a 
a 






















o 
> 

























































































s 

a 
» 
c -2 

o 
a 

w 

0) 

>• 
o 

o -3 

3 

-4 



20 40 60 

Ambient temperature (°C) 



20 40 60 

Ambient temperature (°C) 



Autobias voltage vs 

Ambient temperature 



Output DC voltage vs Ambient temperature 



5.S 






































































































































































































4ft 



































































> 4.0 










































1 






















O 
O 






















3 

a 






















O 






















3.5 













































20 40 60 

Ambient temperature (°C) 



20 40 60 

Ambient temperature (°C) 



-558 



SONY® 



CXA1337Q-Z/R 



Processing system of a CCD Video Cameras 



Description 

CXA1 337Q-Z/R is designed to extract signals 
from the CCD output of stripe CCD cameras 
during signal processing. 
This bipolar IC executes correlated double 
sampling, AGC and color separation. 

Features 

• Through the double sampling function it can 
inhibit low band noise in CCD signals. 

• A wide coverage AGC amplifier enhances the 
camera sensitivity. 

• Has output effective for image making such 
as Iris adjustment output and High 
brightness detection output. 

Structure 

Bipolar silicon monolithic IC 

Absolute Maximum Ratings (Ta = 25°C) 



• Supply voltage 


Vcc 


10 


V 


• Operating 


Topr 


-20 to +75 


°C 


temperature 








• Storage 


Tstg 


-55 to +150 


°C 


temperature 








• Allowable power 


Pd 


600 


mW 


dissipation 






(QFP) 






950* 


mW 
(VQFP) 






•When mounted on the 






glass epoxy 


board 






40 mm x 40 


mm 






t = 0.8 mm 





Recommended Operating Conditions 

• Supply voltage Vcc 4.75 to 5.25 



V 



Package Outline 



Unit: mm 



CXA1337Q-Z 48 pin QFP (Plastic) 



ai5.3 llM 




0.8 0.3 -<U. 



ZML 



QFP-48P-L04 



CXA1 337R 48 pin VQFP (Plastic) 

9.0"^ 



»07.0 1(u 



fiuuiurijn 



o 



mnnfflT 




W\ Q.1Q I 



%4 



Detailed diagram of A. 

Note) Dimension with * mark shows the status 



without residual resin. 



VQFP-48P-L04 



80502-YA 



559 



SONY® 



CXA1337Q-Z/R 



Pin Description 



(/I -1 

01 V) 



O c\j <\j 10 ro Crt 



G2IPBLK) (38} 



G1 (WINDOW) (39> 



DET.CLP.F (41) 



DET LEVEL (42)- 



GND(A) (43) 



Vg OUT (44} 



OP 10 (46) 



0P1© (47 



0P2© (48 




<24) CS SLICE 



<23) CS OUT 



(22) Vcc(D) 



<21> SP3 



(19) GNO(O) 



(15) CLPO 



13) DATA IN 



-560 



SONY® 



CXA1337Q-Z/R 



Pin Description and Equivalent Circuit (Vcc = 5V) 



No. 



Symbol 



Standard DC 



Equivalent Circuit 



Description 



OP2 



0.7 to 3.5V 




Inverted operational, 
amplifier input. 



OP2 OUT 



1 to 4V 



200yA(T; 



-© 



m 



Operational amplifier 
output. 



N.C. 



AGC IN 



1.8 V 



T)800jjA 



W 



"0 



Color separation input 



Vcc (A) 



5V 



Power supply for ana- 
log signal processing. 



561 



SONY® 



CXA1337Q-Z/R 



No. 



10 



Symbol 



AGC OUT 



AGC.CLP.F 



AGC. MAX 



AGC CONT 



Standard DC 



1.8V 



2.3V 



2 to 4V 



2to4V 



Equivalent Circuit 



AGC SEL 



Oto 5V 




(T)-^< 1 a £ I 



777 



m 



© O 



777 




© CD- 



1O0k5 



;;-S 



777 




200jja(0 CD 200pA 



Description 



AGC amplifier output 



Connecting pin for the 
AGC clamping 
capacitor. 



Maximum gain control 
pin for AGC amplifier. 



Gain control pin 
for AGC amplifier. 




\) 0.1 to 1 mA 



Gain control range 
shifting pin for 
the AGC amplifier 
H: 4V or more, 

high gain mode 
L: 1V or less, 
low gain mode 



562- 



SONY® 



CXA1337Q-Z/R 



No. 



Symbol 



Standard DC 



11 



PG.CLP.F 



3.3V 



12 



CLP3 



13 



DATA IN 



14 



PG IN 



15 



CLPO 



3.3V 



3.3V 



Equivalent Circuit 




m 




nioo«A 



i^ — i — 



3 



200 u A (7) QjSOOjiA 



W 



Same as pin 13 (DATA IN) 



77T 




nioouA 



Description 



Pin connecting the 
CLP 3 clamping circuit 
capacitor. 



CLP 3 pulse input 

(active H) 
H: 3V or more 
L: 2V or less 



CCD signal input 



CCD signal input 



CLP pulse input 

(active H) 
H: 3V or more 
L: 2V or less 



I 



563 



SONY® 



CXA1337Q-Z/R 



No. 



Symbol 



Standard DC 



Equivalent Circuit 



16 



SHP 



17 



SHD 



18 



SP1 



@— i-a 




Same as pin 16 (SHP) 



19 



GND(D) 



20 



SP2 



GND 




f)400uA 



Same as pin 18 (SPI) 



Description 



SHP pulse input 

(active H) 
H: 3V or more 
L: 2V or less 



SP1 pulse input 

(active H) 
H: 3V or more 
L: 2V or less 



SP 1 pulse input 

(active H) 
H: 3V or more 
L: 2V or less 



Ground for digital 
(pulse) block 



SP2 pulse input 

(active H) 
H: 3V or more 
L: 2V or less 



-564 



SONY® 



CXA1337Q-Z/R 



No. 



Symbol 



Standard DC 



Equivalent Circuit 



Description 



21 



SP3 



Same as pin 18 (SPI) 



SP3 pulse input 

(active H) 
H: 3V or more 
L: 2V or less 



22 



Vcc(D) 



5V 



Power supply for digital 
(pulse) block. 



23 



CS.OUT 



J $600 

— ■* — r 



2.1V 



J WV 1 ~-(23\ 



Dt)t 



$ 



High brightness detec- 
tion output. 



24 



CS.SLICE 



1.8 to 3.3V 




Level adjustment pin 
for high brightness 
detection. 



25 



CS.GAIN 



2 to 4V 




100uA(4) (Ijiooija 



Output level adjustment 
pin for high brightness 
detection. 



-565 



SONY® 



CXA1337Q-Z/R 



No. 



Symbol 



26 



f 3 CLP.F 



27 



f 3 OUT 



28 



f 2 CLP.F 



29 



f 2 OUT 



30 



DC OUT 



Standard DC 



1.4V 



1.9V 



1.4V 



1.9V 



1.9V 



Equivalent Circuit 



Same as pin 7 (AGC.CLP.F) 



^600^- 

-t; « 

— © 



cb « 



Same as pin 7 (AGC.CLP.F) 



Same as pin 27 (f 3 OUT) 



Same as pin 27 (f 3 OUT) 



Description 



Pin connecting the f 3 
output clamping 
capacitor. 



f 3 output (signal out- 
put from AGC output, 
sample-hold and color 
separated at SP3.) 



Pin connecting the f 2 
output clamping 
capacitor. 



f 2 output (signal out- 
put from AGC output, 
sample-hold and color 
separated at SP2.) 



Black level DC output 
of fi, f2 and fa outputs. 



566- 



SONY® 



CXA1337Q-Z/R 



No. 



Symbol 



Standard DC 



Equivalent Circuit 



Description 



31 



f t CLP.F 



1.4V 



Same as pin 7 (AGC.CLP.F) 



32 



f, OUT 



1.9V 



Same as pin 27 (f 3 OUT) 



33 IRIS.CLP.F 



3.3V 



34 



35 



IRIS.LEVEL 



IRIS SEL 



1 to 3V 



Oto 5V 





(35) ' — CZH 



W 




Pin connecting the fi 
output clamping 
capacitor. 



fi output (signal out- 
put from AGC output, 
sample-hold and color 
separated at SP1.) 



Pin connecting the iris 
output clamping 
capacitor. 



Iris output gain control 
pin (effective only 
when Gi (pin 39) is 
L level.) 



Gain control range 
shifting pin for iris 
output. 
H: 4 V or more, 

High gain mode 
L : 1 V or less. 
Low gain mode 



-567- 



SONY® 



CXA1337Q-Z/R 



No. Symbol Standard DC 



Equivalent Circuit 



36 



37 



38 



IRIS OUT 



CLP1 



G2 



1.9V 



Same as pin 27 (f 3 OUT) 



Same as pin 12 (CLP3) 



39 



40 



G1 



DET OUT 



1.9V 



77T Q)lOOuA 



777 (T)100uA 



IJIOOpA j[ 



Description 



Iris output (iris control 
signal output) 



CLP pulse input 

(active H) 

H: 3V or more 
L: 2V or less 



Blanking pulse input 
(active L) 

H: 3V or more 

L: 2V or less 



Window pulse input 

(active L) 

H: 3V or more 
L: 2V or less 



Detection signal out- 
put for AGC loop for- 
mation (DET output) 



568 



SONY® 



CXA1337Q-Z/R 



No. 



Symbol 



41 



DET.CLP.F 



42 



DET LEVEL 



43 



GND(A) 



Standard DC 



3.3V 



1 to 3V 



GND 



Equivalent Circuit 




777 



Same as pin 34 (IRIS LEVEL) 



44 



Vg OUT 



45 



OP1 OUT 



3V 



1 to 4V 



Description 





Pin connecting the de- 
tection input clamping 
capacitor. 



Detection output gain 
control pin (effective 
only when G1 (pin 39) 
is L level.) 



Ground for analog sig- 
nal processing. 



Regulator output 
Output current: 

+ 1 mA (outgoing 
direction) 

-80/iA (incoming 
direction) 



I 



Operational amplifier 
output 



-569 



SONY® 



CXA1337Q-Z/R 



No. 


Symbol 


Standard DC 


Equivalent Circuit 


Description 


46 


CP1 


0.7 to 3.5V 


Same as pin 1 (OP2 ©) 


Inverted operational 
amplifier input. 


47 


0P1 © 


0.7 to 3.5V 


Refer to pin 1 . 


Non-inverted opera- 
tional amplifier input 


48 


0P2 © 


0.7 to 3.5V 


Refer to pin 1 . 


Non-inverted operation 
amplifier input. 



570 



SONY® 



CXA1337Q-Z/R 



Electrical Characteristics 






Vcc = 


5V, Ta 


= 25°C 


Item 


Rate value 


Test condition 


Min. 


Typ. 


Max. 


Unit 


Power consumption 


ID 




45 


60 


75 


mA 


AGC amplifier 




AGC OUT/DATA IN 

AGC CONT = 2V, AGC.MAX = 4V, 
AGC SEL = 4V 












Gain control 


ACONT Min. 


0.5 


2 


3.5 


dB 


ACONT Max. 


AGC C0NT = 4V, AGC.MAX = 4V, 
AGC SEL = 4V 


28 


30 


32 


dB 


Maximum gain 
control 


AMAX Min. 


AGC CONT = 4V, AGC.MAX = 2V, 
AGCSEL = 4V 


13.5 


15.5 


17.5 


dB 


Low gain mode 


AG LOW 


AGC CONT = 3V, AGC.MAX = 4V, 
AGCSEL = 2V 


10.7 


12.7 


14.7 


dB 


Fixed gain mode 


ACONT F 


AGC CONT = 0V, AGC.MAX = 4V, 
AGC SEL = 4V 


4.5 


6.5 


8.5 


dB 


Fixed maximum 
gain mode 


AMAX F 


AGC CONT = 4V, AGC.MAX = OV, 
AGCSEL = 4V 


19.5 


21.5 


23.5 


dB 


C 


olor separator 




f1 output/AGC output 












f1 channel gain 


f1 G 


-1.8 


-1 


-0.2 


dB 


Matching between 
channels 


Af 


f2 output/f1 output and f3 output/ 
f1 output 


-0.6 





+ 0.6 


dB 


DC OUT 


DC 


Output voltage at DC OUTPUT 
(30-pin) 


1.8 


1.9 


2.0 


V 


Ir 


is amplifier 




Iris output/DATA IN 

IRIS LEVEL = 1V, G1=0V, G2 = 5V, 
IRIS SEL = 4V 












Window control 


IR Min. 






-30 


dB 


IR Max. 


IRIS LEVEL = 4V, G1 =0V, G2 = 5V, 
IRIS SEL = 4V 


4 


5.5 


7.0 


dB 


Low gain mode 


IR LOW 


IRIS LEVEL = 4V, G1 =0V, G2 = 5V, 
IRIS SEL=1V 


-0.7 


0.3 


1.3 


dB 


Clamp voltage 


IR DC 




1.8 


1.9 


2.0 


V 


Maximum output 
level 


IR MAX 




1.5 






V 



571 - 



SONY® 



CXA1337Q-Z/R 



Item 


Rate value 


Test condition 


Min. 


Typ. 


Max. 


Unit 


Detection amplifier 




Detection output/AGC output 
DET LEVEL = 1V, G1=0V, G2 = 5V 












Window control 


DET Min 






-30 


dB 


DET Max 


DET LEVEL = 4V, G1=0V, G2 = 5V 


-1.5 





+ 1.5 


dB 


Clamp voltage 


DET DC 




1.8 


1.9 


2.0 


V 


Maximum output 
level 


DET Max. 




1.4 






V 


C 


S amplifier 




CS output/AGC output 

CS GAIN = 2V, CS SLICE=1V 












Gain control 


C CONT Min. 


-5 


-3.5 


-2 


dB 


C CONT Max. 


CS GAIN = 4V, CS SLICE=1V 


5.5 


7.5 


9.5 


dB 


High brightness 
detection level 
(slice control) 


SLICE 


Detection level calculated as AGC 
output with 2.5 V CS slice.* 


410 


570 


730 


mV 





perational amplifier 




Maximum output with no load, 
OP1 © - OP1 s 10 mV 












OP1 


high level 


0P1 H 


4.1 






V 


low level 


0P1 L 


Minimum output with no load, 
OP1 © - OP1 © £ -10mV 


0.9 


1.0 


1.1 


V 


OP2 


high level 


0P2 H 


Maximum output with no load, 
OP2 © - OP2 © s 10 mV 


4 






V 


low level 


0P2 L 


Minimum output with no load, 
OP2 © - OP2 s - 10 mV 






1.1 


V 


Vg OUT 


VG 


Regulator output with no load 


2.9 


3.0 


3.1 


V 


AVg 


AVG 


Regulator output variation when Vcc 
varies from 5V to 4.5V with no load. 


-60 


-30 





mV 



*Note) Voltage between the black level of the AGC output (main line signal) and the high brightness 
level determined by the voltage at CS SLICE pin. 




AGC output 



T 



L\. 



Input signal of CS amplifier 



*\ High brightness level determined at CS SLICE 
Value in Specifications 



-572- 



SONY® 



CXA1337Q-Z/R 



Electrical Characteristics Test Circuit 




-DAT4 IN II (™)— 6 DATA ,N 



? 



3 5 i 


i 


<J 


(L !j 


< <j ! 


' § < 


£ 


1 






i 


I 






I 


6 °" -> 


r J 


7, 


f 0.1 X 

[ ¥ 



(4V) (OV) <4V) 



*Note) 1 . The capacitor unit value is fiF. 

2. Voltages in parentheses are those not specified in "Test condition" of the Electrical 
Characteristics. 

3. (y) indicates a test pin. (Test of AC and DC voltages) 



573 



SONY® 



CXA1337Q-Z/R 



I/O Waveform for the Electrical Characteristics Test Circuit 



40/iS ►)"*- 20jts -*i 



DATA IN Input level 



CLP1 



CLP3 



CLPO 



5V_ 
OV — I 



OV 
5V 



OV- 



5V 



OV. 



AGC OUT Test 

i 



fi, h, h 
OUT 



IRIS OUT Test 



DET OUT Test 

J. 



CS OUT Test] 
1.4V 



In In 2ft 



ri 



n 



n. 



\l 



Pulses should 
, not be overlapped 
when DATA IN is 
at H level. 




-574- 



SONY® 



CXA1337Q-Z/R 



ACG Amplifier gain control characteristics 



AGC Amplifier maximum gain control 
characteristics 

























40 








V 


'cc 


= 5V 


f.J 


a = 25° 


C 












































30 


























20 


































AGC MAX 


10 














1 |= 4V 
pnr cci 


















= 4V 






V 



























) 1 2 3 4 1 

AGC CONT voltage <V) 

Detection amplifier window control 
characteristics 



00 
O 

u 

O -10 

< 

0-15 























Vc 


c = 


5V, 


Ta = 


= 25 


°C 
























































/ 




















/ 




















/ 




























G1 
G2 


=0\ 
= 5 


/ 
V 






/ 































12 3 4 5 

Detection level voltage (V) 
CS amplifier gain control characteristics 























V 


cc = 


= 5V 


r , Tj 


i = 2 


5° 


























































































































C 


S S 


LICE 


















= V 


V 













































40 








Vcc 


= 5V, Ta = 


25° 


C 






















30 










































20 
























\ 










AC 


JC C 

\- = 
5C J 


<1V 


1 


10 














AC 


>EL 


















~ 


4V 

























1 2 3 4 5 

AGC amp. maximum gain control voltage (V) 

Iris amplifier window control characteristics 
(low gain mode) 



< -10 
Q 

° -15 

CO 

CC 























Vc< 


: = B 


V, 


Ta = 


25 


°C. 


















/j 




















/ 


















/ 


/ 


















/ 




















/ 






G1 = 0V 






/| 








IRIS 


SEL 






/ 












= 


V 






/ 

















12 3 4 5 

IRIS level voltage (V) 

CS Amplifier slice control characteristics 
(high brightness detection level) 



Calculated as the 
level obtained 
from the black 
level at AGC 
output 
Detection level 

Vs 
AGC OUT 



> 1.8 

> 1.6 
1.4 
1.2 




0.8 
0.6 
0.4 
0.2 























V 


tec 


= | 


>v. 


Ta 


= 2 


.5°( 









































































































































































12 3 4 

CS gain voltage (V) 



1.6 1.8 2.0 22 2.4 2.6 2.8 30 3.2 3.4 

CS slice voltage (V) 



-575 



SONY® 



CXA1337Q-Z/R 



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-576 



SONY. 



CXA1338Q-Z/R 



CCD Camera Matrix 



Description 

CXA1338Q-Z and CXA1338R are matrix ICs for 
CCD cameras and are used for the system with 
complementary color checkers coding imager 
ICX026AK. They perform the vertical correlation 
process by using 1HDL and outputs the RGB signal 
from the magenta, green, yellow, and cyan input 
signals. 

Features 

• Excellent color reproduction as a result of the 
primary color separation system. 

• Two modes are provided for the matrix factor ; 
PRESET and CONTROL. 

• The aperture signal in the V direction is output. 

• The chroma suppress signal is output. 

• The Yh and Yl-Yh signals are output. 

Structure 

Bipolar silicon monolithic IC 

Application 

• Complementary color checkers CCD color camera 



Package Outline 



Unit : mm 



Absolute Maximum Ratings (Ta = 25°C) 

• Supply voltage 

• Storage temperature 

• Operating temperature 

• Allowable power dissipation 



Recommended Operating Condition 

• Supply voltage 



CXA1338Q-Z 48 pin QFP (Plastic) 

15,3*° 




..s O 



0FP-4BP- 104 



CXA1338R 48 pin VQFP (Plastic) 

9.0*°-' 




Detailed diagram of A 



Note) Dimensions marked with * 

does not include residual resin. 



v F P - d 8 P - 1 l 



Vcc 


7 


V 


Tstg 


-55 to +150 


°C 


Topr 


-20 to +75 


°C 


Pd 


600 


mW 


on 

Vcc 


4.75 to 5.25 


V 



-577- 



SONY® 



CXA1338Q-Z/R 



Block Diagram and Pin Configuration 




-578- 



SONY® 



CXA1338Q-Z/R 



Pin Description 



No. Symbol 



Voltage 



Equivalent circuit 



Description 



Y GAIN 



3.0V 




Gain control pin for the signal 
input to Yy 1IN. 

1.8V (Min.) to 5.0V (Max.) 



Yl IN 



3.4V 




Yl input, which is clamped by the 
input connected to the capacitor. 

250mV (Typ.) 



AGC MIX 



3.0V 




Ym factor (Yl/Yh ratio) control. 
3.0V (Yl) to 4.0V (Yh) 



Yl-Yh OUT 



2.9V 




Yl-Yh signal and V aperture signal 
output pin. Black level 3V. If the 
47 pin OFFSET pin is set to GND 
in test mode, Ym signal (that has 
mixed Yl and Yh) is output. 



Yh OUT 



2.2V 




Yh output. 

1000mV (Typ.), 1300mV (Max.) 
Black level 2.4V 



AP GAIN 



3V 




V aperture gain control. 
1.8V (Max.) to 5.00V (OFF) 



-579 



SONY® 



CXA1338Q-Z/R 



No. 



Symbol 



Voltage 



Equivalent circuit 



Description 



AP SLICE 



3V 




V aperture slice level control. 
1.8V (Min.) to 5.0V (Max.) 



AP-C 



3.7V 



:i« 



'30 I s 



Pin that connects the V aperture 
signal capacitor CLP capacitor. 



VCS GAIN 



3V 




Chroma suppress signal level 
control with V aperture. 

1.8V (Min.) to 5.0V (Max.) 
GND : OFF 



10 



CSY OUT 



2.1V 




Chroma suppress signal output. 



11 



CS GAIN 



3V 




Chroma suppress signal level 
control with Y signal. 

1.8V (Min.) to 5.0V (Max.) 
GND : OFF 



12 
13 
15 



B OUT 
G OUT 
R OUT 



1.9V 
1.9V 
1.9V 




R, G, B output pin. Black level 
1.9V. If the 21 -pin B MTX pin is 
set to GND in test mode, each pin 
outputs a signal as shown below. 
R OUT — Cr signal 
B OUT ••• Cb signal 
G OUT - Y signal 
The Cr, Cb, and Y signal are 
provided before the matrix. 



-580- 



SONY® 



CXA1338Q-Z/R 



No. 



Symbol 



Voltage 



Equivalent circuit 



Description 



14 



DC OUT 



1.9V 




DC output of 1 . 9V that is 
equivalent to R, G, B OUT black 
level. 



16 
17 
18 



R-C 
G-C 
B-C 



3.2V 
3.3V 
3.3V 



«:i 




Pin that is connected to the R, G, 
B OUT clamping capacitor. 



19 



20 



21 
22 



23 
24 



25 



GND 



ID 



B MTX 
R MTX 



Mi-C 
MoC 



APCUT 



0V 



3V 
0V 



3.0V 
3.0V 



3.95V 



~-l 



::IK 



V 



GND 



«■: 



130 [y\ 





Inverted pulse is input every 1H. 
The Cl signal is output to B OUT 
for HI. 

The Cl signal is output to R OUT 
for LOW. 

Vth = 2.5V 



Matrix factor control for B and R. 
1.8V (Max.) to 3.9V (Min.) 
In test mode : 

B MTX : Cr/Cb mode with GND 
R MTX : MTX preset mode with 
GND 



M1-C : Connects the 1H line 

chroma signal clamping 

capacitor. 
MoC : Connects the 0H/2H line 

chroma signal clamping 

capacitor. 



Controls the level that suppresses 
the V aperture signal. Internally 
biased to 3.95V in preset mode. 



581 



SONY® 



CXA1338Q-Z/R 



No. Symbol 



26 



27 
32 
37 



28 
29 



Yi-C 



C2- GAIN 
Ci- GAIN 
Yi- GAIN 



Yi OUT 
Yo OUT 



30 
31 



33 
34 



35 
36 



Ci OUT 
Co OUT 



DLC2 IN 
DLCi IN 



DLY 2 IN 
DLYi IN 



38 
39 



Si IN 
S2 IN 



Voltage 



3.0V 



3V 
3V 
3V 



2.6V 
2.6V 



2.6V 
2.6V 



2.9V 
2.9V 



2.9V 
2.9V 



3.3V 
3.3V 



Equivalent circuit 










Description 



Pin that connects the 1H line Y 
signal clamping capacitor. 



C1, C2, Yi signal gain control. 
1.8V (Min.) to 5.0V (Max.) 



1H/0H line Y signal output. 
Inverted output 200mV (Typ.) 



1H/0H line chroma signal output. 
Inverted output ± lOOmV (Typ.) 



2H/1H line chroma signal input. 
Positive phase input ± 75mV (Typ.) 



2H/1H line Y signal input. 
Positive phase input 150mV (Typ.) 



S1/S2 signal input. 

500mV (Typ.) 1500mV (Max.) 



582- 



SONY® 



CXA1338Q-Z/R 



No. 



Symbol 



Voltage 



Equivalent circuit 



Description 



40 



Vcc 



5V 



Vcc 



41 
42 



CLPO 
CLP2 



5V 
0V 

5V 
0V 



_n_ 



::<K 



^ 



40*iA 
GNO 



Clamp pulse input 
Vth = 2.5V 



43 



GND 



0V 



°^ 



GND 



44 



Y IN 



2.7V 




Y signal input. 

220mV (Typ.) 660mV (Max.) 



45 



OV 




: r 62K 



y curve control. 

1.8V to 5.0V 
GND : Preset 



46 



Yyo OUT 



3.0V 




Y y signal output. 
Inverted output 

400mV (Typ.) 520mV (Max.) 



47 



OFFSET 



1.8V 




y offset control. 

1.8V to 5.0V 

If the pin is set to OPEN, bias to 

1.8V is internally performed. 

If the pin is set to GND in test 

mode, the Ym signal is output 

from the 4 pin, Yl-Yh OUT pin. 



48 



Yyi IN 



2.9V 




1 H line Y y signal output. 
150mV (Typ.) 



-583 



SONY, 



CXA1338Q-Z/R 



Electrical Characteristics 



Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Supply current 


Ice 


Vcc = 5V 


20 


33 


45 


mA 


Si, S 2 LPF 


FS1. S2 


4.77MHz gain for ® Si IN-*® Y OUT 
300kHz 


-28 


-20 


-11 


dB 


S1-Y0 gain 


GS1-Y0 


@ S1IN-* ® YoOUT gain 


-14.2 


-13.0 


-11.8 


dB 


Gain difference 
between Si -Yo 
and S2-Y0 


AGyo 


Gain difference between @ Si IN-*® YoOUT 
and ® S2IN-* ® YoOUT 


-0.7 





0.7 


dB 


Si-Co gain 


Gsi-so 


@ SilN^® CoOUT gain 


-3.2 


-1.9 


-0.8 


dB 


Gain difference 
between S1-C0 
and S2-C0 


A Geo 


Gain difference between ® S1IN-* 
© CoOUT and ® S2IN-*® CoOUT 


-0.7 





0.7 


dB 


Y1 gain Min. 


GyiMin. 


® DLY1 IN-*® Y1 OUT gain 
® YiGAIN = 1.8V 


- 


-2.5 


-1.3 


dB 


Y1 gain Max. 


Gyi Max. 


® DLY1 IN-*® Y1 OUT gain 
@ Y1 GAIN = 5V 


8.8 


12.0 


- 


dB 


C1 gain Min. 


Gci Min. 


® DLC1 IN—® C1OUT gain 
© C1 GAIN = 1.8V 


- 


-2.5 


-1.3 


dB 


C1 gain Max. 


Gci Max. 


@ DLC1 IN-® C1 OUT gain 
@ CiGAIN = 5V 


8.8 


12.0 


- 


dB 


C2 gain Min. 


Gc2Min. 


@ DLC1IN— © ROUT 

GAIN that is twice as much as ® DLC2IN 

— © ROUT,® BMTX=GND, @ ID = GND, 

© C2 GAIN = 1.8V for © BMTX = GND, 

ID = 5V@ 


- 


-2.8 


-1.3 


dB 


C2 gain Max. 


Gc2Max. 


® DLC1IN-© ROUT 

Gain that is twice as much as ® DLC2IN 
— © ROUT.® BMTX = GND, ® ID = GND, 
@ C2GAIN=1.8V for © BMTX = GND, 
© ID = 5V 


8.8 


12.0 


- 


dB 


Y2 gain Min. 


Gy2Min. 


Ratio of the output of ® DLY2IN. 
(200mV) -@ Yl-YhOUT, ® Yi GAIN = 1.8V 
to the output of ® DLY1 IN (100mV) — 
© Yl-YhOUT, © Y1 GAIN = 1.8V 


-1.4 





1.4 


dB 


Y2 gain HI 


GY2Max. 


Ratio of the output of ® DLY2 IN 
(100mV) -@ Yl-YhOUT,® Yi GAIN = 1.8V 
to the output of ® DLY1 IN (50mV) — 
© Yl-YhOUT,® Y GAIN = 3.9V 


-1.4 





1.4 


dB 


Co LPF 


Fco 


4.77MHz gain for ® DLC2IN-© ROUT, 
@ ID = GND, 300kHz 


-28 


-18 


-8 


dB 


C1 LPF 


Fci 


4.77MHz gain for ® DLC2IN-© ROUT, 
© ID = 5V, 300kHz 


-28 


-18 


-8 


dB 



584- 



SONY® 



CXA1338Q-Z/R 



Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


Yi LPF 


Fyi 


4.77MHz gain for ® DLY1 IN-© GOUT, 
300kHz 


-28 


-18 


-8 


dB 


V apperture 
LPF 


Fap 


4.77MHz gain for ® DLYi IN-* 
@ Yl-YhOUT, 300kHz 


-28 


-18 


-8 


dB 


DLYi -Yl-Yh 
gain 


Gdlyi 


® DLY1 IN (100mV) — ® Yl-YhOUT gain 
© APGAIN= 3.25V 


6 


8.3 


11 


dB 


V aperture 
level Max. 


GApMax. 


® DLYi IN (30mV) -*@ Yl-YhOUT 
Output level ratio for © APGAIN= 3.25V 
to 1.5V 


8 


11 


- 


dB 


V aperture 
slice Mid. 


Vaps Mid. 


® DLYi IN (100mV) -*® Yl-Yh OUT 
Output level difference between ® 
APSLICE=2V and 3V 


85 


120 


155 


mV 


V aperture 
cutting input 
level 


Vapcut 


® DLY1 IN input level when the ® 
Yl-Yh OUT output is cut 
© APGAIN = 1.5V 


225 


260 


295 


mV 


Chroma 
suppress Y 
output level 
Max. 


Vcsy Max. 


® DLY1 IN (350mV) -*® CSYOUT 
® VCSGAIN=GND.® CSGAIN = 1.8V 


400 


760 


- 


mV 


Chroma 
suppress Y 
gain Min. 


Gcsy Min. 


® DLY1 IN (350mV) -® CSYOUT 
(D VCSGAIN = GND 

Output level ratio for © CSGAIN = 5V 
to 1.8V 


-14.2 


-12.0 


-10.8 


dB 


Chroma 
suppress VAP 
level Max. 


Vcsvap 
Max. 


® DLY1 IN (50mV) — © CSYOUT 
© CSGAIN=GND.@ VCSGAIN = 5V 


740 


920 


- 


mV 


Chroma 
suppress VAP 
gain Min. 


GcSVAPM 

Min. 


® DLY1 IN (50mV) -® CSYOUT 
® CSGAIN=GND 

Output level ratio for ® VCSGAIN = 5V 
to 1.8V 


-14.2 


-12.0 


-9.3 


dB 


Cr gain 


Gcr 


® DLCilN-*© ROUT gain 
® RMTX=GND 


3.6 


5.3 


7.0 


dB 


RMTX Y 

factor 

presetting 


Kry 


® DLCilN (100mV) -*© ROUT,® ID=5V 
@ RMTX = GND output level set to Vl 
® DLY IN (220mV) -*© ROUT,® ID=5V 
© RMTX=GND output level set to V2 
(V2/V1) X1/8 is calculated. 


0.094 


0.12 


0.131 


V/V 


Cb gain 


Gcb 


® DLC1IN-*© BOUT gain 
@ ID = GND, @ RMTX=GND 


3.6 


5.3 


7.0 


dB 


BMTX Y 

factor 

presetting 


Kby 


® DLCilN (100mV) -© BOUT, 

® ID = GND 

@ RMTX=GND output level set to V1 

® DLYi IN (220mV) -© BOUT,® !D = GND 

® RMTX=GND output level set to V2 

(V2/V1) X1/8 is calculated. 


0.173 


0.20 


0.222 


V/V 



-585 - 



SONY® 



CXA1338Q-Z/R 



Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


BMTX C R 
factor 


Kbcr 


@ DLC1IN (100mV) -© BOUT,® ID=GND 
© RMTX=GND output level set to V1 
® DLC1IN (100mV) ->•© BOUT,® ID=5V 
© RMTX=GND output level set to V2 
V2/V1 


0.173 


0.20 


0.222 


V/V 


Yi gain 


Gyi 


® DLY1IN-*® GOUT gain 
® ID=5V,® RMTX=GND 


6.6 


8.3 


10.0 


dB 


GMTX Cr 
factor 


Kgcr 


® DLY1IN (220mV) -*© GOUT,® ID=5V 
® RMTX=GND output level set to V1 
® DLC1IN (100mV) -*© GOUT,® ID=5V 
® RMTX=GND output level set to V2 
V2/V1X8 


0.78 


1.0 


1.22 


V/V 


GMTX C B 
factor 


Kgcb 


® DLY1IN (220mV) -*© GOUT,® ID=5V 
® RMTX=GND output level set to Vl 
® DLC1IN (100mV) -*© GOUT, @ ID=GND 
© RMTX=GND output level set to V2 
V2/V1 X8 


0.78 


1.0 


1.22 


V/V 


RMTX Y 
factor HI 


Krymi 


<8> DLC1IN (100mV) -© ROUT,® ID=5V 
© RMTX=GND output level set to V1 
® DLY1 IN (220mV) © ROUT, ® ID=5V 
© RMTX=1.8V output level set to V2 
(V2/V1) X1/8 is calculated. 


0.192 


0.225 


0.253 


V/V 


BMTX Y 
factor LOW 


Krylo 


® DLC1IN (100mV) -*® ROUT,® ID = 5V 
© RMTX=GND output level set to V1 
® DLY1IN (220mV) -*® ROUT,® ID=5V 
© RMTX=3.9V output level set to V2 
(V2/V1) X1/8 is calculated. 


0.042 


0.056 


0.070 


V/V 


BMTX Y 
factor HI 


Kbymi 


<8> DLC1IN (100mV) -*® BOUT,® ID=GMD 
© RMTX=GND output level set to Vl 
® DLY1 IN (220mV) -*© BOUT, @ ID=GND 
© BMTX = 1.8V output level set to V2 
(V2/V1) X1/8 is calculated. 


0.337 


0.380 


0.413 


V/V 


RMTX Y 
factor LOW 


Kbylo 


® DLC1IN (100mV) -M© BOUT,® ID=GND 
© RMTX=GND output level set to V1 
® DLY1 IN (220mV) -© BOUT ® ID=GND 
© BMTX = 3.9V output level set to V2 
(V2/VD X1/8 is calculated. 


0.068 


0.09 


0.117 


V/V 


DC OUT DC 


Vcc 


® DCOUT pin voltage 


1.73 


1.85 


1.97 


V 


R, G, B OUT 
offset 


Vrgbo 


Potential difference between ® ROUT/ 
© GOUT, © BOUT and ® DCOUT 


-10 





10 


mV 


y preset 
standard level 


Vy PRE 


® YIN (220mV) -® Y y OUT 


365 


410 


455 


mV 



586 



SONY® 



CXA1338Q-Z/R 



Item 


Symbol 


Condition 


Min. 


Typ. 


Max. 


Unit 


y preset curve 


GyPPE 


Ratio of ® YIN (55mV) -*® Y Y OUT 
output level to © YIN (220mV) -* 
® Y y OUT output level 


-8.2 


-7.0 


-5.8 


dB 


YhOUT DC 


Vy HOUT 


(D YhOUT pin voltage 


2.0 


2.3 


2.6 


V 


Yh gain Min. 
(YhOUT) 


GYHMinl 


® YyilN-KD YhOUT gain 

© YGAIN = 1.8V 

® AGCMIX=4V ® OFFSET=GND 


- 


10 


12.2 


dB 


Yh gain Max. 
(YhOUT) 


GYHMaxI 


® YyllN-KD YhOUT gain 

© YGAIN=5V 

® AGCMIX=4V ® OFFSET=GND 


20.8 


23.0 


- 


dB 


Yl -YhOUT DC 


VylOUT 


Yl-Yh pin voltage 


2.6 


2.9 


3.2 


V 


Yh gain Min. 
(Yl-YhOUT) 


GvHMin2 


@ Y yilN— ® Yl-Yh OUT gain 

© YGAIN = 1.8V 

® AGCMIX=4V ® OFFSET=GND 


- 


2.1 


4.2 


dB 


Yh gain Max. 
(Yl -YhOUT) 


GYHMax2 


® YyilN-*® Yl-Yh OUT gain 

© YGAIN=5V 

® AGCMIX=4V ® OFFSET=GND 


12.8 


15.0 


- 


dB 


Yl gain 


Gyl 


(D YlIN^-® Yl-Yh OUT gain 
(D AGCMIX=3V 


4.3 


6.0 


7.7 


dB 



I 



-587- 



SONY. 



CXA1338Q-Z/R 



Electrical Characteristics Test Circuit 
Standard setting conditions 




Note) 

1. Conditions only that are different from standard setting conditions are described. 

Adjust Vci, Vc2, and Vyi so that the signal levels will be equivalent between DLC1IN and 

C1OUT, DLC2IN and between DLY1IN and YiOUT. 

Signal sources other than ID, CLPO, and CLP2 are not input in standard setting but set to 

GND. 

If measurement conditions specify ID = 5V and ID = GND, measure at the ID = 5V timing and 

ID = GND timing. 



2. 



3. 



588 



SONY® 



CXA1338Q-Z/R 



Input Signal Timing Chart 



Pin 



Input signal 



10 20 30 40 50 60 10 20 30 40 50 60 //SeC 



41 CLPO 



42 CLP2 



20 ID 



38 Si IN 



39 S2IN 



36 DLY1IN 



35 DLY2IN 



34 DLC1IN 



33 DLC2IN 



44 YIN 



48 Y Y 1 IN 



;_n 



:_ri 



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MWIAA/WIAAA/I 



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iWUWMMM/U 

1_ 

MAAMAA/WWU 

l_ 



AAAAAMM/WWU 

1_ 



HJMAJWWWm 



AAAIMAAJWim 



L_ 

AA/l/lAAA/WJWl- 



L 

AA/Wl/WWl/l/WU 



1_ 



1_ 



Note) 1. The signal level and frequency are listed in another table. 

2. The sine wave intermittent signal is used for measurement of 
LPF characteristics . 



-589 



SONY® 



CXA1338Q-Z/R 



Delay line gain control amplifier characteristics R MTX control characteristics (Y factor) 




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37, 32, 27 pins Yi, Ci, C2GAIN pins (Y) 



22 pin RMTX (V) 



B MTX control characteristics (Y factor) 



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X 



AP GAIN control characteristics 



























































































































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21 pin BMTX (V) 



6 pin AP GAIN (V) 



AP SLICE control characteristics 



CSY GAIN control characteristics 





































































300 




















































200 










































100 

































































7 pin AP SLICE (V) 
6 pin AP GAIN = 3.25V 
Input pin 36 DLY1IN 100mV 







































































































































300 
200 
100 



















































































11 pin CS GAIN (V) 

(Input pin 36 DLYilN = 350mV) 



-590- 



SONY® 



CXA1338Q-Z/R 



CSY VAP control characteristics 



control characteristics 



500 






















400 
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9 pin VCS GAIN pin (V) r) 
(Input pin 36 DLYilN = 50mV) 

y OFFSET control characteristics ( y = 1 .8V) 



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100 































































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44 pin YIN input level (mV) 















































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44 pin YIN input level (mV) 
Yh GAIN control characteristics 




1 pin Y GAIN pin (V) 



Ym GAIN control characteristics 








Yl 


MIX 


control characteristics 




300 
200 
100 












































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1 pin Y GAIN pin (V) 



3 pin AGC MIX (V) 



591 



SONY® 



CXA1338Q-Z/R 



Si, S2, Y-R, G, B GAIN Vcc characteristics 



YIN-Yh GAIN Vcc characteristics 



=3 "2 





























































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Vcc-Supply voltage (V) 



Vcc-Supply voltage (V) 



YIN-Yl-Yh GAIN Vcc characteristics 



YIN-Yl GAIN Vcc characteristics 



3? 













































































































































































































Vcc-Supply voltage (V) 



Vcc-Supply voltage (V) 





CSY 


SAIN 


Vcc 


characteristics 
























8 










































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3 






















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S GAIN Vcc 


characteristics 
























9 










































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Vcc-Supply voltage (V) 
(Input pin 36 DLYllN = 350mV) 



Vcc-Supply voltage (V) 
(Input pin 36 DLYilN = 50mV) 



592- 



SONY® 



CXA1338Q-Z/R 



Si. S2 IN - Co. Yo OUT Gain 
temperature characteristics 



Ta-Ambient temperature CO 

DLCi IN - R, B OUT gain 
temperature characteristics 



Ta-Ambient temperature CO 

Y y 1 IN -* Yh OUT gain 
temperature characteristics 



DLY1, DLCi IN - Y1, Cl OUT gain 
temperature characteristics (OdB) 



Ta-Ambient temperature CO 

Y IN (220mV) - Y y OUT gain 
temperature characteristics 




Ta-Ambient temperature CO 

DLYi IN -* Yl - Yh OUT aperture gain 
temperature characteristics 

























tion (%) 
3 
























































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| 






















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2 

< -10 























































































Ta-Ambient temperature CO 



Ta-Ambient temperature CO 



-593 



SONY® 



CXA1338Q-Z/R 



DLYi IN (350mV) -* Yl - Yh OUT CSY 
temperature characteristics. 




DLYi IN (50mV) - Yl - Yh OUT CSY VAP 
temperature characteristics. 




Ta-Ambient temperature CO 



Ta-Ambient temperature (°C) 



Operation 

CXA1151 is an IC that outputs RGB, Yl - Yh, Yh, and CSY from the signal that sampled and 
held the complementary color checker coding imager. . 

1. Si and S2 input -* RGB OUT 



J-IjHDQl jj 'HDL ^ 



Table-1 Imager cod 



Mg 
Ye 


G 

Cy 


Mg 
Ye 


G 
Cy 


G 
Ye 


Mg 
Cy 


G 
Ye 


Mg 
Cy 


Mg 
Ye 


G 
Cy 


Mg 
Ye 


G 
Cy 






Table-2 


Chroma 


signal 




OH (Co) 


1H(C) 


2H(C 2 ) 


C 


2R-G 


-(2B-G) 


2R-G 



Table-3 S1 and S2 signals 



S, 



S, 





OH 


1H 


2H 


s, 


G+Cy 


Mg+Cy 


G+Cy 


s 2 


Mg+Ye 


G+Ye 


Mg+Ye 



1) Imager 

The coding imager shown in Tab!e-1 is used. 

2) Si and S2 inputs 

The signals that sampled and held the imager output are input. By using the imager shown 
in Table-1, field reading is performed to obtain signals shown in Table-3. G + Cy and G + Ye, 
or Mg + Ye and Mg + Cy are alternately input to Si and S2 every hour. 



594- 



SONY® 



CXA1338Q-Z/R 



3) Chroma signal 

The chroma signal (C) is acquired from S2 - Si. As shown in Table-2, a signal that 
alternates 2R-G and 2B-G is obtained. 

4) C02 and C1 signals 

To make the RGB signal in the matrix circuit, 2R-G and 2B-G are required at the same 
time. By using 1HDL, signal C1 that 1 hour behind and signal C2 that is 2 hours behind 
are created. By averaging Co and C2 with the same period as 2B-G of C1, 2R-G is created. 

5) Multiplexing 

2R-G and 2B-G are alternately sent every hour to C1 and Co2, so 2R-G (Cr) and 2B-G (Cb) 
are separated by the ID pulse that inverts "L" to "H" . or vice versa every 1 hour. 

6) Matrix 

RGB is made from Cr, Cb, and Y. The theoretical formulae shown below are applied. 

R = Cr+0.12Y 

B=-Cb+0.20 (Y-Cr) 

G = Y-Cr+Cb 
Coefficients, 0.12 and 0.20, are adjustable. (RMTX and BMTX Pins) 

7) RGB output 

The RGB output is a clamped output. The clamped DC is output to the DC pin. From the 
R OUT, B OUT, and G OUT pins, the Cr, Cb, and Y signals to be fed to the matrix can 
be output. 

2. Y IN, Yl IN -» Yl - Yh OUT 

As Yl that is output from Yl - Yh OUT, © Yl signal and @ Y IN signal can be linearly 
switched with (D AGC MIX pin of the MIX amplifier. 



1) Y IN signal 

Y = Mg + G + Ye + Cy ((f 3 ) out of CXA1337), as the AGC output, is input. 

2) y 

The y^curve is adjustable, and presetting is available. 

3) OFFSET 

It is used in the negative mode. If GND is set, the output of the MIX amplifier comes 
out of Yl - Yh OUT. (For adjustment) 

4) Yl - Yh OUT 

By controlling the AGC MIX Pin, a (Yl IN - Y IN) (0 ^ « ^ 1) is output. The aperture 
signal is added and output. 



3. V aperture signal 



Y0+Y2 



-Yi 



The V aperture signal is synthesized from « 

The signal is made at a ratio of 1 : 1 between plus and minus. 



J 



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~l_ 



f — y 



595 - 



SONY® 



CXA1338Q-Z/R 



After aperture signal VAP is synthesized, the signal whose level around noise is sliced and 
controlled by the aperture slicing circuit is added to the Yl - Yh signal. 
The aperture signal is not output when the Y signal exceeds a reference level. 
That reference level has been preset but it can be adjusted with © AP CUT Pin. 
If ® AP CUT is set to GND, the aperture signal is not output at all. 

4. Chroma suppressing Y signal 

Depending on the Y signal level, a signal that suppresses the chroma signal is output. 
The chroma suppressing Y (CSY) signal is made by mixing the following two signals : 

1) The amount of the Y signal exceeding a reference level (1.2 times of the reference signal) 
is output. 

The sliced amount is fixed. After slicing, the signal is gain-controlled and output. 

2) The absolute value of the aperture signal is output as the CSY signal. 




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— r^n - icLPi - 



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CS GAIN 
(9) VCSGAIN 



-596 



SONY® 



CXA1338Q-Z/R 



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597- 



SONY. 



CCD Camera Processor 



CXA1339Q-Z/R 



Description 

CXA1339Q-Z and CXA1339R are processor 
ICs for CCD color cameras. These execute 
color coding, white balance, y compensation, 
HUE control and other signal processing to 
color separated input signals, y compensated 
R-Y, B-Y and YH, YL-YH signals are also 
shaped. 

Features 

. The built-in color coding circuit makes it 
compatible with both types of CCD color 
filters, complementary color or primary color. 

. Realizes high resolution through the adoption 
of YL-YH, and YH's Y signal processing. 

• Compatible with negative/positive inversion. 

. White balance is compatible with both 
automatic and one push button. 

. Control pins have preset function. 

Absolute Maximum Ratings (Ta=25°C) 

. Supply voltage Vcc 7 

. Operating temperature Topr -20 to + 75 
. Storage temperature Tstg -65 to +150 
. Allowable power Pd 600 

dissipation 

Recommended Operating Condition 

. Supply voltage Vcc 5+0.25 



Package Outline 



Unit: mm 



CXA1339Q-Z 48 pin QFP (Plastic) 

15.3'" 



V 

°c 
°c 

mW 





*-mt0.12 



2! Hi 



QFP-48P-L04 



CXA1339R 48 pin VQFP (Plastic) 

D7.0*°-' 



l aaamiaiaiinR 



rnnnnif. 



Detailed diagram 



of A n~ 



^ 




VQFP-48P-L01 

Note) Dimensions marked with* 

does not include residual resin. 



80706-ST 



598 



SONY® 



CXA1339Q-Z/R 



Block Diagram 



MAT GAIN 2 (4 l> 



CLP C S3 (44> 



CLP C 52 (45> 



CLP C SI fa6> 



COOING (48h 




I OFFSET CONT 



U8) CLP C R-G 



I?) CLP C B-G 



16) R-V GAIN 



141 R-Y OUT 



13) R-Y HUE 



-599 



SONY® 



CXA1339Q-Z/R 



Pin Description 



No. 



Symbol 



GATE 1 
GATE 2 
GATE 3 



CLP 



Y PED 



6 YH OUT 



YL MIX 



Equivalent circuit 




8 'YL-YH OUT 






T)150J|A 




Voltage 



3.1 to 5V* 
HI LEVEL 
Oto 1.9V* 
LO LEVEL 



3.1 to 5V* 
HI LEVEL 
to 1.9V* 
LO LEVEL 



Description 



With the gate pulse input of YH GATE, 
when GATE 1 turns to HI, YH = S1 
when GATE 2 turns to HI, YH = S2. 
when GATE 3 turns to HI, YH = S3. 
It is active at HI. 



This is the clamp pulse input pin for 
signals R, G, B, S1 , S2, S3, R-G and B- 
G. It is active at HI. 



1.6 to 5V* This is the Y signal dark slice level 
j control pin. 



to 0.4V* 



2.5V 



Preset mode pin (Y-PED OFF). 



When pin 20>1.6V YH output is on 
and when pin 20 <0.4V YL output is 
on. 



il~6 to 5V* This is the YLY and YLC MIX RATIO 
\ control pin. 
Color coding in complementary mode. 



to 0.4 V* Color coding in primary color mode. MIX 
i ratio of YLY and YLC is YL 100% MAT 

GAIN 1 and 2 reach the same gain as S2 

channel. 
3.0V 




YL-YH output output when pin 
20>1.6V.YTP output when pin 
20<0.4V. 



"f)340jjA 



*Note) External voltage applied 



-600 



SONY® 



CXA1339Q-Z/R 



No. 



9 
10 



11 



12 
13 



14 



15 
16 



Symbol 



Y-y CO NT 
C-y CO NT 



B-Y OUT 



B-Y HUE 
R-Y HUE 



R-Yv OUT 



B-Y GAIN 
R-Y GAIN 



Equivalent circuit 







f)l40»A 




Voltage 



1 .6 to 5V* 



to 0.4V* 



3.0V 



1.6 to 5V* 



to 0.4V* 



3.0V 



1.6 to 5V* 



to 0.4V* 



Description 



Y signal, chroma signal y control. 



Preset mode (Typ. y curve) 



When pin 20>1.6V B-Y output. When 
pin 20<0.4V B output. 



HUE control of B-Y, R-Y 



Preset mode (HUE OFF) 



When pin 20>1 .6V R-Y output. When 
pin 20<0.4V R output. 



Gain control of B-Y, R-Y. 



Preset mode. Pin 14 R-G output. Pin 
11. B-G output. 



I 



Note) External voltage applied 



601 - 



SONY® 



CXA1339Q-Z/R 



No. 



Symbol 



Equivalent circuit 



Voltage 



Description 



17 
18 



CLP C B-G 
CLP C R-G 



cc 

I -i 

rWV-" 



© S 



® 



Capacitor connecting; pin for B-G, R-G 
signal clamp. 



,: -K 



19 



GND1 



GND* 



GND pin for other than YH GATE part. 



20 



OFFSET CONT 




1.6 to 5V* 



Offset control during negative, positive 
inversion function. (For both Y and 
chroma systems) 



-TprW 1 1 



yrr rrr 4o u a(J) 



to 0.4V* 



Output of pins 6, 8, 11, 14 and 22 
changes. 



21 



C-PED 




1.6 to 5V* 



Dark slice level control of chroma 
signal. 



to 0.4V* 



Preset mode (C-PED OFF) 



22 



G OUT 



3.0V 



When pin 20>1.6V Gy output. When 
pin 20<0.4V G output. 



(t)eont 






23 



WND+VD 



r^" 



@-^~ CE} 




2.5V 

4.1 to 5V* 
WINDOW ON 
to 0.9V* 
RESET ON 



Pulse input pin for one push white 
balance system. 



Note) External voltage applied 



-602- 



SONY® 



CXA1339Q-Z/R 



No. 



24 
25 



26 
27 
28 



Symbol 



B COMP 
R COMP 



Voltage 

Vh>4V 
Vl<1 V 



DET C R 
DET C G 
DET C B 



29 C LEVEL 



1.6 to 5V* 



30 CLP C R 

31 CLP C G 

32 i CLP C B 



33 
34 



B CONT 
R CONT 




to 0.4V* 



0.4 to 2.5V* 



Description 



Comparator output Vh is the output 
when B<G and R<G. Vi is the output 
when B>G and R>G. 



Connecting of capacitor for R, G, B 
signals peak detection. 



Chroma level control. 



Preset mode (0 dB for primary color 
mode, 6 dB for complementary color 
mode) 



Connecting pin of capacitor for R, G, B 
signals clamp. 



White balance control. 



Note) External voltage applied 



603- 



SONY® 



CXA1339Q-Z/R 



No. 



Symbol 



Equivalent circuit 



Voltage 



Description 



35 
36 



B GAIN 
R GAIN 



1.6 to 5V* 



Prewhite balance control. 




to 0.4V* 



Preset mode (same gain as G channel) 



37 



MAT GAIN 1 



1 .6 to 5V* 



Control of matrix amplifier 1 



©— HUD-t 



to 0.4V* 



Preset mode (same gain as S2 channel) 



©"O" 



38 



S1 IN 




For S1 signal input. 



39 



DC IN 



vcc 



1.9V* 



Differential input vs S1 to S3 input. 




40 



S2 IN 




For S2 signal input. 



Note) External voltage applied 



-604 



SONY® 



CXA1339Q-Z/R 



No. 



Symbol 



Equivalent circuit 



Voltage 



Description 



41 



MAT GAIN 2 



1.6 to 5V* 



Control of matrix amplifier 2. 



to 0.4V* 



Preset mode (same gain as S2 channel) 



(p 



42 



S3 IN 



For S3 signal input. 




43 



GND2 



GND* 



GND pin of YH GATE part. 



44 
45 
46 



CLP C S3 
CLP C S2 
CLP C S1 



<g>— 4pri 



i 

r-VW-' 



Capacitor connecting pin for S1 , S2, 
and S3 signals clamp. 



©i: -u. 



47 



Vcc 



5 V* 



Supply pin. 



48 



CODING 



©- 



6SK 



rh ifr 



^ 
^ 



Mode control for color coding, effective 
only in complementary color mode (YL 
MIX>1 .6V). Compatible codings are as 
follows. 



4.6 to 5V* 



W, Ye, Cy mode 



2.5V 



Ye, G, Cy mode 



to 0.4 V* 



W, Ye, G mode 



*Note) External voltage applied 



-605 



SONY® 



CXA1339Q-Z/R 





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SONY® 



CXA1339Q-Z/R 



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608- 



SONY® 



CXA1339Q-Z/R 



Test Circuit I/O Waveform 
Input waveform 



S1, S2, S3 IN 
(Pins 38, 40, 42) 

CLP 
(Pin 4) 



WND+VD 
(Pin 23) 



Output waveform 



R-Y 


OUT 


(Pin 


14) 


G OUT 


(Pin 


22) 


B-Y 


OUT 


(Pin 


11) 


YH 


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(Pin 


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(Pin 


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I 



-609 



SONY® 



CXA1339Q-Z/R 



Electrical Characteristics Test Circuit 



(OVI (OVI (IV) (IV) 



mx m 



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Note) 1 . Capacitor capacity unit |tF. 

2. In brackets voltage in places not specifies in the descriptions of Electrical characteristics. 

3. V indicates test pin. (AC, DC voltage test) 



-610- 



SONY® 



CXA1339Q-Z/R 



Operation 
Color coding 

Compatible with the combination of the 4 following color filters. Set through the applicatin of voltage to 
CODING (Pin 48) and YL MIX (Pin 7). The necessary conditions for the selection of each coding are as follows. 



Filter color coding 


CODING (Pin48) 


YL MIX (Pin 7) 


R.G.B 


- 


GND 


W.Ye.Cy 


Vcc 


Higher than 1.6V 


Ye.G.Cy 


OPEN 


Higher than 1.6V 


W.Ye.G 


GND 


Higher than 1.6V 



W:White, Ye:Yellow, Cy:Cyan 



Note) R.G.B modes are selected with YL 
MIX only and have no relation with 
the CODING voltage. 



Preset mode 

By grounding a pin that has the preset function, the control setting by that pin stands at a specified value. 
This is indicated in the following table. 



No. 


Symbol 


Preset mode 


5 


Y-PED 


Becomes Y-PED OFF. 


7 


YL MIX 


Color coding at R. G. B, YL YLC 1 00%, MAT GAIN 1 and 2 reaches same gain 
as S2 channel. 


9 


Y-y CONT 


Becomes typical Y-y curve. (See Fig. 11) 


10 


C-y CONT 


Becomes typical C-y curve. (See Fig. 10) 


12 


B-Y HUE 


Becomes B-Y HUE OFF. 


13 


R-Y HUE 


Becomes R-Y HUE OFF. 


15 


B-Y GAIN 


B-Y OUT (Pin 11) output becomes B-G. 


16 


R-Y GAIN 


R-Y OUT (Pin 14) output becomes R-G. 


20 


OFFSET CONT 


Pins 6, 8, 11,14 and 22 of - output SWs are switched. 


21 


C-PED 


Becomes C-PED OFF. 


29 


C LEVEL 


C LEVEL AMP gain becomes dB at R.G.B modes. In other modes 6 dB. 


35 


B GAIN 


B GAIN AMP gain becomes same as G channel. 


36 


R GAIN 


R GAIN AMP gain becomes same as G channel. 


37 


MAT GAIN 1 


MAT GAIN Ts gain becomes same as S2 channel. 


41 


MAT GAIN 2 


MAT GAIN 2's gain becomes same as S2 channel. 



I 



611 - 



SONY® 



CXA1339Q-Z/R 



Output switching SW 

By grounding OFFSET CONT (pin 20) output SW of pins, 6, 8, 1 1 , 1 4 and 22 and output signal becomes 
as follows. 



No. 


OFFSET CONT>1.6V output 


OFFSET CONT<0.4V output 


6 


YH 


YL 


8 


YL-YH 


YTP (signal that has passed through 
PED of Y S2 channel) 


11 


B-Y 


B (B signal before entry 7) 


14 


R-Y 


R (R signal before entry 7) 


22 


G signal with y applied 


G (G signal before entry 7) 



White balance control 

1) Gain control 

There are 2 types, R GAIN (Pin 36) and B GAIN (Pin 35) for precontrol and RCONT(Pin34) and B 
CONT (Pin 33). 

Also for R CONT, B CONT The control voltage and the white balance amplifier gain reverse 
figures have a ratio relation. It is ideal as the control pin for auto white balance. 



2) One push white balance (close loop white balance) 
• An example is shown at right 
R.G.B signals that have passed through 
white balance are PEAK detected and output 
as comparison signals R and G, B and G by lnpmsignal 
means of the comparator. From the comparison 
signal, GAIN control is executed and by 
requesting R CONT B CONT to become 
R=B=G, white balance is completed. 



R CONT 












f WND+VD 






1 




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— JDetectionj— 




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CXA1121 









Detection part operation 

WND+VD (Pin 23) the operation of the detection part by means of external voltage 

application is as follows. 

WDN+VD>4.1 V: Detects input signal. 

WND+VD=2.5V: Just before getting set to 2.5V, detection data is held. 

WND+VD<0.9V: Detection data is reset. 



-612- 



SONY® 



CXA1339Q-Z/R 



MAT GAIN 1, 2 control characteristics 

Output is assumed to be dB when MAT 
GAIN 1 and 2 control is at preset (ON). 



WB R, B GAIN control characteristics 

Output is assumed to be OdB when 
R, B GAIN control is at preset (OV). 



12 3 4 5 

MAT GAIN, 1,2 control voltage (V) 

WB R, B CONT control characteristics 

Output is assumed to be 1 

when, R, B CONT control is at 1 V. 



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R, B GAIN control voltage (V) 

C LEVEL control characteristics 

Output is assumed to be OdB when 
C LEVEL control is at preset (OV). 



10 





































































































































































































m 























12 3 

R, B CONT control voltage (V) 

R-Y, B-Y GAIN control characteristics 

Output is assumed to be OdB when 
R-Y, BY GAIN control is at preset (OV). 



12 3 4 5 

C LEVEL control voltage (V) 
R-Y, B-Y HUE control characteristics 



10 
































































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2 3 4 5 

R-Y, B-Y GAIN control voltage (V) 



2 3 4 5 

R-Y, B-Y HUE control voltage (V) 



613 



SONY® 



CXA1339Q-Z/R 



C-PED control characteristics 



Y-PED control characteristics 

























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YL MIX control characteristics 

























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C-y control characteristics 

























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OFFSET control characteristics 























































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500 
Input voltage (S2 IN) (mV) 



-614- 



SONY® 



CXA1339Q-Z/R 



E 

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615 



SONY. 



CXA1 072Q-Z/R 



Camera Signal Processing 



Description 

CXA1072Q-Z and CXA1072R are encoder ICs 
for CCD color cameras. 

Luminance and color difference signals are input 
to be output as composite video signals. 
Combined use with system for CCD color 
cameras. 

Features 

• Built-in auto carrier balance (carrier balance 
adjustment unnecessary). 

• Compatible with both NTSC/PAL 

• Compatible with Negative/Positive. 

• Low consumption (200 mW) (1 50 mW in B/W 
mode) 

• Low noise 



Structure 

Bipolar silicon monolithic IC. 

Application 

CCD color camera 

Function 

• Set-up level control 

• White clip level control 

• White fader/black fader 

• View finder output 

. Character signal (superimpose) 

• Sub carrier modulation 

• Burst level control 

• PAL mode 

• Sub carrier output 

• Sharpness level control 

• Negative mode 

• Return video input 

• Auto carrier balance 

• HUE control 

• Sync level control 

• Chroma suppress Y, 
chroma suppress AGC 



Package Outline 



Unit: mm 



48 pin QFP (Plastic) 



HZ7I o.i5 




QFP-48P-L04 



48 pin VQFP (Plastic) 




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VQFP-48P-L01 



Absolute Maximum Ratings (Ta=25°C) 

• Supply voltage Vcc 7 V 

• Operating temperature Topr —20 to +75 °C 

• Storage temperature Tstg —55 to +150 °C 

• Allowable power dissipation Pd 600 mW 

Recommended Operating Condition 

• Supply voltage Vcc 4.75 to 5.25 V 



616- 



SONY® 



CX A 1 072Q-2/CX A 1 072R 



Block Diagram and Pin Configuration 



SHP LEVEL I 



<») — ®— ® — <a-® — (^h§>h§h|7hS^ 



MJ©— © ©kIxIXiX!) 




23) FADER SIG 



-*C2)EVF OUT 

@Vcc(A) 

-»@ VIDEO OUT 

®GND(D) 
— -(l8)RV SIG 



^— <2> 




13) CHARACTER 



(I)-®-®-© 



Abbreviations 



CLP 


Clamp 


RV 


Return Video 


DET 


Detecter 


EVF 


Electric View Finder 


CONT 


Control 


CIN 


Chroma Input 


BF 


Burst Frag 


PED 


Pedestal 


BLK 


Blanking 


WC 


White Clip 


N/P 


Nega/Posi 


DLD 


Delay Line Drive 


LALT 


Line Alternate 


DLE 


Delay Line End 


CSY 


Chroma Suppres Y 


SHP 


Sharpness 



617- 



SONY® 



CXA1 072Q-Z/CX A1 072R 



Pin Description and Equivalent Circuit 



No. 



Symbol 



Voltage 



Equivalent circuit 



Description 



1 
45 



B-Y IN 
R-Y IN 



3.0V 
(External) 
3.0V 
(External) 




Color difference signal input 
pin 



2 
47 



B-Y CLP 
R-Y CLP 



3.0V 
3.0V 



©@ 



'2k 



ii * — < >■ 



Connecting pin to the color 
signal input CLP capacitor. 



T 



yu 



!5>jA 



3 
46 



B-Y DET 
R-Y DET 



3.5V 
3.5V 



FT 1 



Connecting pin to the capa- 
citor for auto carrier balance. 



(I) — "-VA-MVV-" 



t 



T)l00juA (T)100jjA 



HUE CONT 



0V 
(External) 



G> 



-w 1 M > 



HUE control pin 

0V HUE OFF 

2.5V to 5V Control 



G> 



I44k V?j50jjA 



X 



FSC OUT 



Low-2.9V 
Hi-3.6V 



i 5^ 



Sub carrier output pin 






(T)500>jA 



-618 



SONY® 



CXA1072Q-Z/CXA1072R 



No. 



Symbol 



Voltage 



Equivalent circuit 



Description 



Vcc (D) 



5V 



Digital circuit supply. 



4FSC IN 



2.5V 

(When 

open) 



n 

(Y) — ,^-vyfr-- 



Pin that inputs signals with 
a frequency 4 times that of 
the sub carrier 



t 



BURST 
LEVEL 



3.7V 
(External) 



, 



Burst level control pin 
Ground when using for analog 
burst. 



70 



SYNC 



Pulse 
input 




Sync pulse input pin 

U Negative polarity 
Low: to 2V 
Hi: 3 to 5V 



10 



BF 



Pulse 
input 




Burst pulse input pin 
~\J~ Negative polarity 



Input 2.5 to 3.5V signal 
during analog burst usage. 
3.5V 
U 2.5V 



-619- 



SONY® 



CXA1072Q-Z/CXA1072R 



No. 



Symbol 



Voltage 



Equivalent circuit 



Description 



11 



BLK 



Pulse 
input 




Blanking pulse input pin 
~~ |_|~~ Negative polarity 

Low: to 2V 
Hi: 3 to 5V 



12 



N/P PULSE 



Pulse 
input 




Pulse input pin in negative 

mode. 

At high level 
negative pedestal. 

Low: to 2V 

Hi: 3 to 5V 



_TL 



13 



CHARACTER 



Pulse 
input 




Character pulse input pin 

- 2.5V 

- 2.0 

Input 2.5V to 3.5V signal 
during analog burst usage. 



14 



LALT 



Pulse 
input 




Line alternate pulse input 

pin 

NTSC mode: GND 

PAL mode: 2H period pulse 

Low: 2.2 to 2.8V 

Hi: 3.8 to 5V 



-620 



SONY® 



CXA1072Q-Z/CXA1072R 



No. 



Symbol 



Voltage 



Equivalent circuit 



Description 



15 



CSY 



2.85V 



n? 



Chroma suppress Y signal 
input pin 



@h-\-Wt 



-C^Jh 



LJ 



IOOjuA (l) 50pA 



16 



CLP2 



Pulse 
input 




©-f^-K 



Clamp pulse input pin 

_j\_ Positive polarity 

Low: to 2V 
Hi: 3 to 5V 



17 



CS AGC 



GND 
(External) 




Chroma suppress AGC signal. 
Input pin 



18 



RV SIG 



2V 




Return video signal input 
pin 



19 



GND (D) 



OV 



20 



VIDEO OUT 



2.1V 



rr 



Video output pin 



70 
(20)— f- WV— " 



ti 



500 jjA 



-621 



SONY® 



CXA1 072Q-2/CXA1 072R 



No. 



Symbol 



21 



Vcc (A) 



Voltage 



5V 



Equivalent circuit 



Description 



Analog circuit supply 



22 



EVF OUT 



2-.1V 



rt 



70 
(22)— i— W-hi 



*J> 



500jjA 



View finder output pin 



23 



FADER SIG 



GND 
(External) 




Fader signal input pin 



24 



C OUT 



2.6V 



1 & 



70 

(24)-hh-%- 



U)800ju/ 



Chroma signal ouput pin 

rvw\ 

Short waveform is output. 
In B/W mode by turning the 
pin to Vcc power saving is 
possible. 



T)50>iA 



25 



EVF SW 



5V 
(External 




EVF output select pin 

OV Return Video 

1 .5 to 3.5V Color mode 

5V B/W mode 



-622- 



SONY® 



CX A1 072Q-Z/CX A1 072R 



No. 



Symbol 



Voltage 



Equivalent circuit 



Description 



26 



C IN 



2.5V 



rr 



(g) — .^-vw-Lwv-' 



a 



j 



Chroma signal mixed input 
pin 



j)l50>jA (T)50>iA 



27 



NEGA PED 



OV 
(External 



i 



■56k >56k >1k 



@— fwvf+^' 



I 



NEGA/POSI modes select 
pin 

OV POSI 

2 to 5V Nega pedestal 

Level control 



J44k <44k n 

, 1 50ijA1 



28 



SETUP CLP 



2.7V 






70 
(28) i-m, — "■ 



i± 



50jja(* 



SETUP CLP capacitor con- 
necting pin 



29 



WC CLP 



2.8V 



lk «1k 



70 
(29) f— ty\A/— f 



35 



WC CLP capacitor connect- 
ing pin 



1 



r l 



5pA 



30 



SYNC LEVEL 



2.5V 




Sync level control pin 



-623- 



SONY® 



CXA1 072Q-Z/CXA1 072R 



No. 



Symbol 



Voltage 



Equivalent circuit 



Description 



31 



SETUP 



2.5V 
(External 



. 



18k« %12k 



Set-up level control pin 
Video output pin 



3i; — t— wv-^> 

13.5k 



T ' 8k T ^4 



)50>jA 



32 



FADER 
MODE 



OV 

(Exteranl) 




Fader mode select pin 

to 2V Black fader 

2 to 3.7V White fader 

White level 
control 



33 



WC 



3.5V 
(External) 




White clip level control pin 



34 



Y LEVEL 



3.2V 
(External 




White signal level control 
pin 



35 



NOISE SLICE 



3V 
(External) 




Noise slice level control 
pin 



-624- 



SONY® 



CX A1 072Q-Z/CXA1 072R 



No. 



Symbol 



Voltage 



Equivalent circuit 



Description 



36 



DLE 



3.4V 




Delay line connecting pin 
for sharpness signal forma- 
tion. 



37 



SHP LEVEL 



3.5V 




Sharpness level control pin 
Chroma signal mixed input 
pin 



38 



DLD 



3.4V 



f 



"-Wr 

70 



Delay line connecting pin 
for sharpness signal forma- 
tion. 



f (j)l"A Q 



lOOpA 



39 



SHP CLP 



2.5V 



rr 



Sharpness clamp capacitor 
connecting pin 



70 
(39) f- Wf— f 



i± 



3)5>iA 



40 



Yh IN 



1.2V 
(External) 



Yh signal input pin 



u 



100>iA 



625 - 



SONY® 



CXA 1 072Q-Z/CX A 1 072R 



No. 



41 



42 



43 



44 



Symbol 



Yh CLP 



Yl-Yh IN 



GND (A) 



Yl-Yh CLP 



Voltage 



2.1V 



3.0V 
(External 



OV 



3V 



48 



CHROMA 
CLP 



3.9V 



Equivalent circuit 



rr 






t"r»- 



r*) 5 ^ 




rr 



Description 



Yh clamp capacitor connec- 
ting pin 



Yl-Yh signal input pin 



Yl-Yh clamp capacitor con- 
necting pin 



@-\— Wr-* ► 



M 



5pA 



rrr 



(48)— i— M 1- 



LM 



5pA 



CHROMA clamp capacitbr 
connecting pin 



-626 



SONY® 



CXA1072Q-Z/CXA1072R 



Electrical Characteristics 



V=5V, Ta=25°C 



No. 


Item 


Symbol 


Condition 


Test point 


Min. 


Typ. 


Max. 


Unit 


1 


Supply current (color) 


Ice 


Current that flows 
into Vcc1 , Vcc2 


Vcd, Vcc2 


31 


40 


53 


mA 


2 


Supply current (B/W) 


Ice (B/W) 


Current that flows 
into Vcc1 ,Vcc2 


Vcd, Vcc2 


22 


30 


40 


mA 


3 


Yh level MIN. 


Y MIN 


Y LEVEL=5V, 
Yh IN=500 mV 


VIDEO 
OUT 


230 


320 


410 


mV 


4 


Yh level MAX. 


Y MAX 


Y LEVEL=2V, 
Yh IN=250 mV 


VIDEO 
OUT 


410 


770 


1240 


mV 


5 


Yh level MAX/MIN 
Yh CLP 2.1V 


Y CONT 


No.3 and No.4 ratio 




8 


13 


17 


dB 


6 


Yl-Yh/Yh gain 
difference 


Yl-Yh 


Yl-Yh IN=250 mV 
/l/O gain difference\ 
with Yh ) 
\IN=500 mV / 


VIDEO 
OUT 


-1.1 





1.1 


dB 


7 


EVF OUT/VIDEO 
OUT gain difference 


EVF 


Yh IN=500 mV 
/l/O gain difference\ 
with the results 
obtained from I 
VIDEO OUT test / 


EVF OUT 


-1.1 





1.1 


dB 


















8 


White clip MAX 


WC MAX 


Yh IN=500 mV 
Y LEVEL=2V, 
WC=5V 


VIDEO 
OUT 


870 


1140 


1430 


mV 


9 


White clip MIN 


WC MIN 


Yh IN=500 mV 
Y LEVEL=2V, 
WC=2V 


VIDEO 
OUT 


440 


540 


660 


mV 


10* 1 


Nega pedestal MAX 


NPED 
MAX 


NEGA PULSE input, 
NEGA PED=5V 
WC=5V, BLK=5V 


VIDEO 
OUT 


880 


1030 


1220 


mV 


11 


Nega pedestal MIN 


NPED 
MIN 


NEGA PULSE input, 
NEGA PED=2V 
W/C=5V, BLK=5V 


VIDEO 
OUT 


240 


330 


460 


mV 


12 


Nega Yh/Posj Yh 
gain difference 


NEGA Y 


NEGA PULSE input, 
NEGA PED=3.4V 
Yh IN=250 mV 
/I/O gain difference\ 
with IN=500 mV in 
posi mode / 


VIDEO 
OUT 


-1.1 





1.1 


dB 



627 



SONY® 



CX A1 072Q-2/CXA1 072R 



No. 


Item 


Symbol 


Condition 


Test point 


Min. 


Typ. 


Max. 


Unit 


13 


Sharpness upper 
side level 


SHP UP 


Yh IN=-20 mV 
Yl-Yh IN=250 mV 
SET UP=5V, 
NOISE SLICE=3.0V 
SHP LEVEL=3.5V 
SW2 ON 


VIDEO 
OUT 


30 


84 


140 


mV 


14 


Sharpness up down 
ratio 


SHP LOW 


Yh IN=20 mV 
Yl-Yh IN=250 mV 
SET UP=5V, 
NOISE SLICE=3.0V 
SHP LEVEL=3.5V, 
SW2 ON 

/Ratio of sharpness\ 
I upper side level vs. 
I sharpness lower 
\side level / 


VIDEO 
OUT 


1.5 


2.0 


2.5 


V/V 


15 


Nega sharpness 
upper side level 


N SHP UP 


Yh IN=20 mV 
NEGA PULSE input 
SET UP=5V, 
NOISE SLICE=3.0V 
SHP LEVEL=3.5V, 
SW2 ON 


VIDEO 
OUT 


30 


84 


140 


mV 


16 


Nega sharpness up 
down ratio 


N SHP 
LOW 


Yh In — 20 mV 
NEGA PULSE input 
SET UP=5V, 
NOISE SLICE=3.0V 
SHP LEVEL=3.5V 
SW2 ON 


VIDEO 
OUT 


1.5 


2.0 


2.7 


V/V 


17 


White fader 


W FADE 


BLK input, 
FADER SIG=3.5V 
FADER MODE=2.5V 


VIDEO 
OUT 


260 


350 


440 


mV 


18 


SETUP MAX 


SETUP 
MAX 


BLK input, 
FADER SIG=3.5V 
SET UP=5V 


VIDEO 
OUT 


165 


140 


185 


mV 


19 


SYNC MAX 


SYNC 
MAX 


SYNC input, 
BLK=0V 

FADER SIG=3.5V 
SYNC LEVEL=5V 


VIDEO 
OUT 


360 


430 


520 


mV 


20 


SYNC MIN 


SYNC 
MIN 


SYNC input, 
BLK=0V 

FADER SIG=3.5V 
SYNC LEVEL=0V 


VIDEO 
OUT 


100 


170 


250 


mV 



628- 



SONY® 



CXA1072Q-Z/CXA1072R 



No. 


Item 


Symbol 


Condition 


Test point 


Min. 


Typ. 


Max. 


Unit 


21 


SYNC EVF (B/W)- 
V OUT Difference 


SYNC 
(B/W) 


SYNC input, 

BLK=OV 

FADER SIG=3.5V 

SYNC LEVEL=OPEN 

Ratio with B-Y level 

No.33 


EVF OUT 


-70 





70 


mV 


22 


SYNC EVF (Color)- 
V OUT Difference 


SYNC 
(COL) 


SYNC input, 
BLK=OV 

FADER SIG=3.5V, 
EVF SW=2.5V 
SYNC LEVEL=OPEN 
/Difference with the\ 
[VIDEO OUT Sync 
I under the same , 
\conditions / 


EVF OUT 


-70 





70 


mV 


















23 


Character blanking 
level offset 
(V-OUT) 


CHA OFF 


BLK input, 
CHARACTER=2.25V 


VIDEO 
OUT 


3 


100 


170 


mV 


24 


Character blanking 
level offset 
(EVF B/W) 


CHA OFF 
(B/W) 


BLK input, 
CHARACTER=2.25V 


EVF OUT 


3 


100 


170 


mV 


25 


Character blanking 
level offset 
(EVF COL) 


CHA OFF 
(COL) 


BLK input, 
CHARACTER=2.25V 
EVF SW=2.5V 


EVF OUT 


20 


100 


190 


mV 


26*2 


Character level 
(V-OUT) 


CHA 


BLK input, 
CHARACTER=3.2V 


VIDEO 
OUT 


475 


520 


595 


mV 


27 


Character level 
(EVF B/W) 


CHA (B/W) 


BLK input, 
CHARACTER=3.2V 
/Ratio vs. VIDEO\ 
OUT character 

\Jevel / 


EVF OUT 


-1.1 





1.1 


dB 


28 


Character level 
(EVF COL) 


CHA (COL) 


BLK input, 
CHARACTER=3.2V 
EVF SW=2.5V 
/Ratio vs. VIDEO\ 
OUT character I 
Vlevel / 


EVF OUT 


-1.1 





1.1 


dB 



629- 



SONY® 



CXA1072Q-Z/CXA1072R 



No. 



29 



30 



31 



32 



33 



34 



35 



36 



37 



Item 



Return video gain 



FSC OUT amplitude 



Carrier balance 
3.58 MHz 



Carrier balance 
500 kHz 



B-Y level 



R-Y level 



CHROMA TOTAL GAIN 



CHROMA GAIN EVF/ 
V-OUT ratio 



Condition 



EVF SW=0V 

RV SIG IN=350 mV 



SW4 ON 



B-Y IN, R-Y IN=2.1V 
and 3.9V 



4FSC IN=2 MHz 
B-Y IN, R-Y IN=2.1V 
and 3.9V 



B-Y IN=300 mV 



R-Y IN=300 mV 



B-Y IN=300 mV 
SW3 ON 



CHROMA D-Range 



38 



39 



40 



41 



42 



43 



44 



CS AGC MAX 



BURST MAX 



BURST MIN 



BURST PAL Hi/ Low 



BURST linear MAX 



BURST level blanking 
offset 



CHROMA BLK level 
offset 



B-Y IN=300 mV 
SW3 ON, 
EVF SW=2.5V 



Test point 



EVF OUT 



FSC OUT 



BPF OUT 



BPF OUT 



BPF OUT 



BPF OUT 



VIDEO 
OUT 



B-Y IN=900 mV 



B-Y IN=300 mV 

CS AGC=3.5V 

(Ratio with B-Y level No.33) 



BF=0V, BLK=0V 
BURST LEVEL=5V 



BF=0V, BLK=0V 
BURST LEVEL=2.5V 



BF=0V, BLK=0V 
Ratio LALT=5 when 
LALT=2.5V 



BF=0V, BLK=0V 
BURST LEVEL=0V 



BF input, BLK=0V 



BLK input, BF=5V 



VIDEO 
OUT 
EVF OUT 



Min. 



4.5 



610 



400 



400 



1.9 



-1.1 



Typ. 



710 



1.3 



1.2 



470 



470 



BPF OUT 



BPF OUT 



BPF OUT 



BPF OUT 



BPF OUT 



BPF OUT 



C OUT 



C OUT 



990 



40 



310 



88 



-3 



340 



Max. 



7.5 



810 



3.5 



3.5 



550 



550 



2.8 



1.1 



1130 



50 



390 



110 



-55 



-55 



450 



Unit 



dB 



mV 



mVp-p 



mVp-p 



mVp-p 



mVp-p 



V/V 



dB 



1260 



60 



480 



132 



560 



55 



mVp-p 



% 



mVp-p 



mVp-p 



mVp-p 



mV 



55 



mV 



•1) 





Character signal level 



output | r jj 



Character level blanking offset 
_It~~^- SETUP 



630- 



SONY® 



CXA1072Q-Z/CXA1072R 



Test Circuit 

(Typical Setting) 



1.2V 5- 



3.0V ^- 



3.0V ^~ 



4.5V 3.2V 5V OV 2.5V 2.5V OV 



\ 



i SW3 



5V 



^ #- 




Tfr ttt trr rn 

3V ov 



I 



Note) Above conditions are given as the typical setting. The individual conditions of each item are 
indicated in the chart. 



-631 - 



SONY® 



CXA1 072Q-Z/CXA1 072R 



Test Conditions 



1. BPF 

(1) 3.58 MHz BPF 

The BPF where with an input of a 
3.58 MHz sine wave the output becomes 
1/2. 




3.58MHz 7.16MHz 



(2) 500 kHz BPF 

The BPF where with an input of a 
500 kHz sine wave the output becomes 
1/2. 



-6dB 




500kHz 1MHz 



2. Pins shown with an input signal timing chart are indicated in the test circuit as -)i 
there is also a test where the signal is input. 



However 



632 



SONY® 



CXA1 072Q-Z/CX A1 072R 



Input Signal Timing Chart 












No. 


Input signal 






1 o 10 


20 


30 


40 


50 


60 

MS 


1.B-Y IN 

9. SYNC 

10. BF 
11.BLK 

12.N/P PULSE 
13.CHARACTER 

1 6.CLP2 
18.RV SIG 
40. Yh IN 
42.Yl-Yh IN 
45.R-Y IN 
















1* 








3V 






ov 












1 5V 

I ov 












—1 5V 

1 ov 
















ov 
















T23 to 25 OV 


l~" 














T26 to 27 2.25V 














n- 


2ms 










r~ 


t* 


1 








r 


1* 


1 






1.2V 


■ 


1* 








3V 








1* 








3V 







Note) Level is indicated in the conditions shown in the chart. 



633 



SONY® 



CXA1072Q-Z/CXA1072R 




U 



£ f-VW-t-WHl 



sTrnb kj. 



E 

+^ 

(0 

>» 
(A 



E 

to 

o 

Q 
O 
O 

© 

Q. 

'Z 
*-> 
(A 

c 
o 

(0 

tf) 

c 


a 

E 
o 
o 

i- 

_o 
o 
O 

X 
00 
(0 



o 




in 




5 




o 




03 
13 


LL 

a. 






V 


03 


W 


A 


a) 


T) 


.a 






.Q 0) 
O 

T3 C 



<D "D 



0C H 



Pulse input 



634- 



SONY® 



CXA1 072Q-Z/CX A1 072R 



Application Circuit 

(During Black and White Mode) 




£>5V 



i>5V 



I 



635 



SONY® 



CXA1072Q-Z/CXA1072R 



Y-Ievle control 



White clip level control 



400 



200 

































Y 


H IN = 250m V 



































































































































































"35 500 



10 2.0 3.0 4.0 

Y level control voltage (V) 




1.0 2.0 3.0 4.0 

WC control voltage (V) 



200 




Set-t 


jp 


level < 


;ontro 


1 







































































































































































































































Sync 


evel contro 








































































300 






















































































100 

































































1.0 2.0 3.0 4.0 

Set Up control voltage (V) 

Fader level control 



1.0 2.0 3.0 4.0 

Sync level control voltage (V) 



5.0 



£ 60 






White fader level 


control 































































































































































































































Fader SIG control voltage (V) 



1.0 2.0 3.0 4.0 

White fader control voltage (V) 
(Fader Mode pin) 



5.0 



-636 



SONY® 



CX A1 072Q-2/CX A1 072R 







Character level control 
















































> 










































:ter level 

5 
o 
o 










































(0 
CO 






















O 



































































1000 






Nega 


PED contro 


1 




































































> 

E 
~- 600 

> 










































Q 

w 400 

(X 
ID 










































200 

































































1.0 2.0 3.0 4.0 

Character pin voltage (V) 



IX} 2j0 3.0 4j0 

Nega PED control voltage (V) 



400 




Burst level control 

































































































































































































































500 






An 


aloi 


3 burst leve 


1 














































400 



























































































































































































1J0 2.0 3.0 4.0 

Burst level control voltage (V) 



1.0 2.0 3.0 

BF pin voltage (V) 

Linear burst output 
BF pin input 





Chroma 


suppress 


> Y control 































































































































































































































— 4|(|j|Ar— 

Chroma suppress AGC control 



■ 



SOO 
CSY SIG level (mV) 



4X> 



CS AGC control voltage (V) 



637 



SONY® 



CX A1 072Q-Z/CX A1 072R 



HUE control 



260 

240 

oi 220 
<u 

a 20 ° 

S. 18 ° 

£ 160 
140 
120 



co 











































































































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1.0 2.0 3.0 

HUE cont (V) 



50 

Ta-Ambient temperature (°C) 



Video out pin pedestal DC 

































Y H 


IN = 


= 250 


mV 





































































































































































600 






White clip 


level 




























































































> 

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O 

5 

































































































































50 

Ta-Ambient temperature (°C) 

White fader level 

temperature characteristics 



50 

Ta-Ambient temperature (°C) 

Set-up level 

temperature characteristics 















































> 

E 










































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50 

Ta-Ambient temperature (°C) 



50 

Ta-Ambient temperature (°C) 



638 



SONY® 



CXA1072Q-Z/CXA1072R 



350 



Sync level 

temperature characteristics 



Carrier balance 3.58 MHz 
temperature characteristics 



300 















































00 

3 










































o 

I -40 

.n 










































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50 

Ta- Ambient temperature (°C) 

Burst level 

temperature characteristics 



50 

Ta-Ambient temperature (°C) 

Y level supply 

fluctuations characteristics 



$ 300 



200 

























650 












































































































600 























































































50 

Ta-Ambient temperature (°C) 

White clip level supply 

fluctuations characteristics 



4.0 5j0 6.0 

V CC - Supply voltage (V) 

White fader supply 

fluctuations characteristics 



-£ 600 











(Pre set mode) 























































































































































































Vcc • Supply voltage (V) 





600 
500 












































> 






















t 






















> 






















0) 

■a 






















0) 






















5 



































































VCC - Supply voltage (V) 



639 



SONY. 



CXL1503M/1505M 



CMOS-CCD Signal Processor 



Description 

CXL1503M and CXL1505M are CMOS-CCD signal 
processors developed for CCD camera complemen- 
tary color filter array processing system. 
CXL1503M 1HX4 301.5 bit CCD delay line 
CXL1505M 1HX4 453.5 bit CCD delay line 

Features 

• Single power supply 5V 

• Low power consumption 
CXL1503M lOOmW (Typ.) 
CXL1505M 150mW (Typ.) 

• Built-in peripheral circuits 

• Built-in CDS(Correlated Double Sampling) circuit 

Function 

• Clock driver 

• Autobias circuit (center and black) 

• Pedestal clamp circuit 

• CDS circuit 



Package Outline 



Unit : mm 



24pin SOP (Plastic) 



1171 0.15 




~W- \®\±oJT\ 



SOP-24P-L01 



Structure 

CMOS-CCD 

Absolute Maximum Ratings (Ta = 25°C) 

• Supply voltage Voo 

• Operating temperature Topr 

• Storage temperature Tstg 

• Allowable power dissipation Pd 



-10 to +60 
-55 to +150 
500 



V 

°C 

°C 

mW 



Recommended Operating Conditions (Ta = 25°C) 

• Supply voltage Vdd 5 ±5% 

Recommended Clock Conditions (Ta = 25°C) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Clock voltage Low 


Vl 







1.0 


V 




Clock voltage High 


Vh 


Vdd- 1.0 




Voo 


V 




Clock frequency 


CXL1503M 


fd 




4.77 




MHz 


NTSC: 910W3 
CCIR: 908W3 


CXL1505M 


fCL 




7.16 




MHz 


NTSC: 455f H 
CCIR: 454f H 



640- 



SONY® 



CXL1503M/CXL1505M 



Block Diagram 



XOLI XDL2 

-® e> 



voo voo vss vss Voo v»» 




Pin Configuration (Top View) 

T7" 



Pin Description 



No. 


Symbol 


I/O 


Description 


Impedance (0) 


1, 16, 17 


Vss 


- 


GND 




2 


IN C 


1 


Signal input C channel 


>100k (at no clamp) 


3 


ABBL 





Autobias DC output for Y signal 


2k to 20k 


4, 8, 20 


Vdd 


- 


5V power supply 




5 


IS 





Input source DC output 


5k 


6 


IN D 


1 


Signal input D channel 


>100k (at no clamp) 


7 


CLP 


1 


Clamp pulse input 


>100k 


9 


OUTD 





Signal output D channel 


50 to 500 


10 


Vgg 





Gate bias DC output 


2k to 10k 


11 


OUTC 





Signal output C channel 


50 to 500 


12 


N.C. 


- 


- 




13 


OUT B 





Signal output B channel 


50 to 500 


14 


CDS 





DC output for CDS 


500 to 5k 


15 


OUT A 





Signal output A channel 


50 to 500 


18 


XDL2 


1 


Clock pulse input 2 


>100k 


19 


XDL1 


1 


Clock pulse input 1 


>100k 


21 


ABCN 





Autobias DC output for C signal 


2k to 20k 


22 


IN A 


1 


Signal input A channel 


>100k (at no clamp) 


23 


DCAB 


1 


DC bias input for A and B channel 


>100k 


24 


IN B 


1 


Signal input B channel 


>100k (at no clamp) 



641 



SONY® 



CXL1503M/CXL1505M 



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642 



SONY® CXL1503M/CXL1505M 



Note 

1. Linearity testing 

For A channel and B channel, set input bias E, to ABCN +0.2(V) first, and then set it to ABCN(V) and 
ABCN -0.2(V). Then input a sine wave of 100kHz and lOOmVp-p, and compare the three output 
amplitudes. 

For C channel and D channel, set input bias E x to ABBL -0.4(V) first, and then set it to ABBL -0.2(V) 
and ABBL(V). Then input a sine wave of lOOkHzand lOOmVp-p, and compare the three output amplitudes. 

The maximum output amplitude for the respective A, B, C and D channels is taken as Sout max. and the 
minimum output amplitude as Sout min. The linearity of the respective channels is defined as 

,. Sout max— Sout min w0r>r> /ft/s 
Lin " = Sout max+Sout min X20 ° (/o) 

2. Calculation of insertion gain difference 

As the max. insertion gain among A, B, C and D channels' is taken as Gmax and the min. as Gmin., the 
insertion gain difference between channels becomes: 

( Gmax~Gmin \ 
uw-ni^^ ^ 2 ° 0X100 (%) 

3. Calculation of linearity difference 

Define Ach linearity as La, and Bch linearity as Lb we obtain the difference ALab as 

ALab= I La -Lb I (%) 

Similarly we obtain the linearity difference ALcd of Cch and Dch as 

ALcd= | Lc-Ld | (%) 

4. Crosstalk calculation 

We take CRTa as: Ach crosstalk value only during Bch input 
CRTb as: Bch crosstalk value only during Ach input 
CRTc as: Cch crosstalk value only during Dch input 
CRTd as: Dch crosstalk value only during Cch input 

The crosstalk value of respective channels becomes: 

r>D-r Crosstalk component ^, n n , n ,s 

CRTa to d = — r — u — l i — r^ i X 1 00 (%) 

Each channe output va ue v/oy 




643- 



SONY® 



CXL1503M/CXL1505M 



Clock Waveform Timing 



XDL1 



XDL2 




-644- 



SONY® 



CXL1503M/CXL1505M 



Electrical Characteristics Test Circuit 




TWrJr 



■'. •: M 



No signal 



100kHz, lOOmVp-p sine wave 



1MHz, lOOmVp-p sine wave 








© 



© fe) ]" 



1 



Application Circuit 



h|>- 



4>-© 




O Output A 



O Output B 




■O Output C 



O Output D 



645 



SONY® 



CXL1503M/CXL1505M 



Frequency response 



-2 










































^ -3 
CO 


















































































"O 






























N 


i. 










— -4 

tin 
































\ 










ertion 
































\ 








































\ 










in 

c 

-6 
































\ 





























































































10K 100K 1M 

Signal frequency (Hz) 



10M 



ABCN vs. Supply voltage 



3 

2 



,5 5 5.5 

VDD-Supply voltage (V) , 
Insertion gain vs. Supply voltage 




























































































2.5 














































































































-•S 























ABBL vs. Supply voltage 



3 
2 



VDD-Supply voltage (V) 
Linearity vs. Supply voltage 






10 
























































































"> 































































































































1 





VDD-Supply voltage (V) 



VDD-Supply voltage (V) 



646 



SONY® 



CXL1503M/CXL1505M 



Frequency response vs. Supply voltage 



ABCN vs. Ambient temperature 



2 



VDD-Supply voltage (V) 



ABBL vs. Ambient temperature 






O 20 40 60 

Ta-Ambient temperature (°C) 
Linearity vs. Ambient temperature 



10 












































^p 






















C 5 










































<D 

C 






















_J 

c 






















_l 




































































20 40 60 

Ta-Ambient temperature (°C) 



2 



O 20 40 60 

Ta-Ambient temparature (°C) 
Insertion gain vs. Ambient temperature 



o 



o 



u 
























































































2.5 
































































































































-"> 























20 40 60 

Ta-Ambient temperature (°C) 
Frequency response vs. Ambient temperature 



Ta-Ambient temperature (°C) 



647- 



SONY. 








CXL1504M 


CMOS-CCD 


1H 


Delay 


line 


for NTSC 



Description 

CXL1 504M is a delay line used in conjunction 
with an external low pass filter. Through 
negative phase input and positive phase output 
1 H delay time is obtained for NTSC signals. 

Features 

. 5V single supply 

. 14.3 MHz driver 

. Low consumption at 1 60 mW (Typ.) 

. Built-in peripheral circuits 

. Completely adjustment free 

Functions 

. 905.5 bit CCD register 

• Clock driver 

• Autobias circuit 

. Input clamp circuit 

. Sample and hold circuit 



Package Outline 



Unit: mm 



20 pin SOP (plastic) 



HaHBBBaBRff 




Q\ 0,15 






j | j.2 7 



tamcmnH^ri 



-44 H&I ± o.i a I 



SOP-20P-L01 



Structure 

CMOS-CCD 

Absolute Maximum Ratings (Ta=25°C) 

. Supply voltage Vdd +6 

. Operating temperature Topr -10 to +60 

. Storage ambient temperature Tstg -55 to +150 
. Allowable power dissipation Pd 500 

Operating Voltage Range (Ta=25°C) 

Vdd 5V+5% 



V 

°C 

°C 

mW 



Recommended Clock Conditions (Ta=25°C) 

. Input clock amplitude Vclk 0.3 to 1.0 

. Clock frequency fcLK 14.318182 

> Input clock waveform sinewave 



Vp-p (0.5 Vp-p Typ.; 
MHz 



Input Signal Amplitude 



VSIG 



560(Max.) mVp-p 



80128-ST 



-648- 



SONY® 



CXL1504M 



Block Diagram and Pin Configuration (Top View) 

SUB NC NC VOD CLK Vss 

r— @ ® ® ® © ®- 



6- 



Autobias 
circuit 



& 



E 



■®- 



Clock 
driver 



CCD (905.5 bit) 



{> 



Bias 
circuit (A) 



<s) (*> 



-©- 



-©- 



Voo 



Pulse generation 
circuit 



Output circuit, 
S/H circuit 



NC 
-©- 



Vss 



<i> 



<2> 



Bias 
circuit (B) 



"©" 



-®- 



Pin Description 



No. 


Symbol 


I/O 


Description 


Impedance [fl] 


1 


IS 





CCD bias DC output 


600 to 2 k 


2 


AB 





Autobias DC output 


2k to 20k 


3 


(NC) 


- 






4 


IN 


I 


Signal input (Negative phase signal) 


>100k (at no clamp) 


5 


Vdd 


- 


5V supply (For clock driver) 




6 


Vss 


- 


GND 




7 


Vgga 





Gate bias (A) DC output 


2k to 10k 


8 


OUT 





Signal output (positive phase signal) 


40 to 500 


9 


Vss 


- 


GND 




10 


Vggb 





Gate bias (B) DC output 


2k to 10k 


11 


Vss 


- 


GND 




12 


(NC) 


- 






13 


Vdd 


- 


5V supply (for analog system) 




14 


(NC) 


- 






15 


Vss 


- 


GND 




16 


CLK 


I 


Clock input 


4k to 50k 


17 


Vdd 


- 


5V supply (for digital system) 




18 


(NC) 


- 






19 


(NC) 


- 






20 


SUB 


- 


GND 





I 



649- 



SONY® 



CXL1504M 



Electrical Characteristics 



See the Electrical Characteristics Test Circuits 
Ta=25°C, Vdd=5V, fci_K=14.31 81 82 MHz, Vclk=500 mVp-p sinewave 



Item 


Symbol 


Test conditions 


SW conditions 


•Note) 

Bias conditions 

VbiasI (V) 


Min. 


Typ. 


Max. 


Unit 


Note 


1 


2 


3 


4 


Supply current 


Iod 


- 


a 


a 


a 


- 


- 


20 


32 


42 


mA 


1 


Insertion gain 


IG 


200 kHz 
500 mVp-p 
Sinewave 


a 


a 


a 


b 


- 


-5.0 


-3.0 


-1.0 


dB 


2 


Frequency response 


fr 


200 kHz 
«3.58 MHz 
1 50 mVp- p 

Sinewave 


b~c 


a 


b 


b 


VIN-0.2 


-2.5 


-1.3 





dB 


3 


Differential gain 


DG 


5- staircase wave 
(See Note 4) 


d 


a 


a 


c 


- 





3 


7 


% 


4 


Differential phase 


DP 


5- staircase wave 
(See Note 4) 


d 


a 


a 


c 


- 





3 


7 


deg 


4 


S/H pulse 
coupling 


CP 


No- signal input 


- 


b 


b 


a 


VIN 


- 


200 


350 


mVp-p 


5 


S/N ratio 


S/N 


50% white video signal 
(See Note 7) 


e 


a 


a 


d 


- 


54 


56 


- 


dB 


6 



Note) VIN is defined as follows. 

VIN is the input signal clamp level, it clamps the Video signal sync tip level. 



L1504 



Input O- 



^ 



Clamp level VIN 



Negative phase 
signal input 



VIN is the pin voltage for pin 4 at no-input signal. Testing is executed with a voltmeter under the 
following SW conditions. 



Item 


SW Conditions 


Test point 


1 


2 


3 


4 


VIN 


- 


b 


a 


- 


VI 



As VIN varies with each IC, they are all subject to testing. 

1) Idd is the IC supply current value during clock and signal input. 

2) IG is the OUT pin output gain when a 500 mVp-p, 200 kHz sinewave is input to IN pin. 

OUT pin output voltage [mVp-p] 

IG=20 log [dB] 

500 [mVp-p] 



650 



SONY® 



CXL1504M 



3) Indicates the dissipation at 3.58 MHz in relation to 200 kHz. 

From the OUT output voltage when a 1 50 mVp-p, 200kHz sinewave is fed to IN pin and from the 

OUT pin output voltage when a 150 mVp-p, 3.58 MHz sinewave is fed to same, calculation is 

made according to the below formula. The input part bias is tested at VIN— 0.2V. 

OUT pin output voltage (3.58 MHz) [mVp-p] 

fr=20 log [dB] 

OUT pin output voltage (200 kHz) [mVp-p] 

4) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the fig. 
below is input are tested at the vector scope. 

143mV 



B 



u__t 



357mV 



143mV 



500m V 



1H 63.56//S 
IN pin input waveform is the inverted waveform in the above Fig. 



5) The internal clock component to the output signal during no-signal input and the leakage of that 
high harmonic component are tested. The input part bias is tested at VinV. 




6) S/N ratio during 50% white video signal input shown in Fig. below is tested at video noise meter, 
in BPF 100 kHz to 4 MHz, Sub Carrier Trap mode. 



u 



Q 



178mV 



143mV 



321mV 



I 



1H 63.56//S i 

IN pin input waveform is the inverted waveform in the above Fig. 



CLOCK 



4fsc (14.3 18182MHz) sinewave 



0.3Vp-p to 1 .OVp-p 
<0.5Vp-p Typ.) 




-651 



SONY® 



CXL1504M 





E 






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00m Vp 
inewave 


00k Hz 

50mVp- 

newave 


58MHz 
50mVp- 
newave 


0) 

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652 



SONY® 



CXL1504M 



> i o 



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c 
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Q. 

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I 



-653 



SONY® 



CXL1504M 



Supply voltage vs. Insertion gain 



Supply voltage vs. Frequency response 



_, 

-2 

-3 ;^;;^^;= = — ' — === = = 

-4 

-5 



VoQ-Supply voltage (V) 
Supply voltage vs. Differential gain 



o 

-1 

-2 — 

-3 • — 



4.75 5-0 5.25 

V[)D-Supply voltage (V) 
Supply voltage vs. Supply current 



VQD-Supply voltage (V) VQD-Supply voltage (V) 

Ambient temperature vs. Insertion gain Ambient temperature vs. Frequency response 



-2 
-3 
-4 
-5 





■2 ■ 

, 3 



20 40 60 

Ta-Ambient temperature (°C) 



20 40 60 

Ta-Ambient temperature ( C) 



-654- 



SONY® 



Ambient temperature vs. Differentical gain Ambient temperature vs. Supply current 

40 

























8 










































6 










































4 
















^ ^ 


























2 


































































to 20 40 60 

Ta-Ambient temperature (°C) 



20 40 60 

Ta-Ambient temperature (°C) 



Frequency response 









































"x 








\ 








v 








~V" 








\ 








— 



100K 

f-Frequency (Hz) 




655 



SONY. 



CXA1270N 



IC for Vertical Direction Outline Compensation 



Description 

CXA1270N is a bipolar IC developed for vertical 
outline compensation of video camera. It contains all 
the required functions for vertical outline compensa- 
tion in a single chip. Also, being a small package, this 
IC is most suitable for the use in video camera. 

Features 

• Low power consumption 

• Usable both in 2H type and 1H type. 

• Executes low level noise clip. 

• Controlable output level. 

Applications 

Video camera 



20pin VSOP (Plastic) 



<* 



Structure 

Bipolar silicon monolithic IC 



Absolute Maximum Ratings (Ta = 25°C) 

• Supply voltage V cc 

• Storage temperature T stg 

• Operating temperature T opr 

• Allowable power dissipation P D 

Recommended Operating Condition 

• Supply voltage V cc 

Block Diagram and Pin Configuration 



10 

-55 to +150 

-20 to +75 

375 


V 
°C 

•c 

mW 


4.75 to 5.25 


V 




—5 — <£> — <2> 



E89631-HP 



-656- 



SONY® 



CXA1270N 



Pin Description and Equivalent Circuit 



V rr = 5V 



Pin 
No. 



Symbol 



Pin voltage 



Equivalent Circuit 



Description 



V„IN 



2.8V 
(Black level) 



Yj IN 



2.8V 
(Black level) 



Y 2 IN 



2.8V 
(Black level) 




Y signal input pin (500Vp-p [Typ] ) 



Y signal input pin (1H delay) 
(150mVp-p [Typ] ) 



Y signal input pin (2H delay) 
(150mVp-p [Typ] ) 



XY OUT 



2.1V 
(Black level) 



XYi OUT 



2.0V 
(Black level) 



© 



Vcc 



Y A mp inverse output pin 



I £ 



Yj A mp inverse output pin 



YjOUT 



2.4V 
(Black level) 



ay 



~t- 



Yi A mp output pin 



Q) 280^A 



Yi CONT 



1.5V to 3.5V 
(Outside) 



Y, CONT 



1.5V to 3.5V 
(Outside) 



<2> 

© ± 




Yj A mp gain control pin 






50*<A ( | ) ( | ) 5Q„A 



Y 2 A mp gain control pin 



SEL 



Low 
High 



OV 
5V 



©- 



* 100K 



S10K 



Switching pin of 2H mode and 1H mode 
High (5V)=2H DL mode 
Low (0V) = 1H DL mode 



10 



GND 



GND pin 



11 



DTL OUT 



2.9V 




DETAIL signal output 



657 



SONY® 



CXA1270N 



Pin 
No. 



Symbol 



12 



XAP OUT 



13 



AP OUT 



14 



SLICE 



Pin voltage 



2.8V 



2.8V 



Equivalent Circuit 



T TsooT" 

— E 1 -y J ~ 1 ^ 



20K 
280//A UJ % 



2V to 4.0V 
(Outside) 



15 



AP CONT 



16 



DTL IN 



17 



Y,OUT 



18 



CLP2 Pulse 



2V to 4.0V 
(Outside) 



3.1V 
(Black level) 



® 





VCC 

T|1.25K 
16) U=h- 



2.1V 



19 



CLPO 



Pulse 



20 






5 5K 




J)50uA 



95*A (h ; \ 



% 







®" 




Description 



V aperture signal inverse output pin 



V aperture signal output pin 



Control pin at SLICE level 



Aperture amplifier (AP AMP) gain control 
pin 



Pin which inputs luminance difference sig- 
nal (Pin 11) output 
[input DTL (DETAIL) OUT signal] 
[through external low pass filter. J 



Y 2 A mp output pin 



Clamp pulse input pin 



Clamp pulse input pin 



Supply pin (5V) 



-658- 



SONY® 



Electrical Characteristics 












Ta = 


= 25°C, V CC = 5V 


No. 


Item 


Symbol 


Test condition 


Min. 


Typ. 


Max. 


Unit 


1 


Consumption 
current 


ID 




6 


8 


10 


mA 


2 


XY OUT GAIN 


XY 


o n i Pin 4 output level 
^ u og Pin 1 input level 


-4.6 


-3.3 


-2.0 


dB 


3 


XY, OUT GAIN 


XY X L 


20 log Pi" 5 output level Y C0NT=15V 
s Pin 2 input level l 






7 


dB 


XYjH 


YiCONT=3.8V 


11 






dB 


4 


Y, OUT GAIN 


YiL 


on ir,™ Pin 6 output level Y mHT _. _„ 
20 log Pin 5 output level ^CONT-l.SV 


1 


2 


3 


dB 


5 


Y 2 OUT GAIN 


Y 2 L 


20log P ' nl ^ Out P u VT' Y 2 CONT=1.5V 
6 Pin 3 input level 2 






7 


dB 


Y 2 H 


Y 2 C0NT = 3.8V 


11 






dB 


6 


AP OUT GAIN 


AP 


Gain from Pin 16 input to Pin 13 output 

. .„. /SLICE=0V 
Conditions | ApC0NT=15V 

Input 1 — < 1— -L 
(DTL IN) 
















/ 




VoutI 
















Output 1 — r 
(AP OUT) 






6 






dB 








Input 2 ' — ± - 

(DTL IN) 
















Output 2 — ' 1— 


Vout1 
















(AP OUT) 
















AP OUT GAIN = 20 log V ?, UT o~w 0u i * 

V IN *- V IN A 
















Slice level = 
















DTL IN-(AP OUTX^o'u ^ 1 ) 

V IN ^ »IN * 










7 


SLICE 


SL 


J. 


Slice 1 

1 


svel 

AP C0NT = 3V 


60 


100 


140 


mV 


Pin 16 ,/ 
input — ' "— r — 








(Pin 16 input conversion slice level) SLICE=3V 











-659 



SONY® 



CXA1270N 



Electrical Characteristics Test Circuit 




T" T" T" ^ 6 



Note) 1. The unit of capacitor is in /iF. 
2. V indicate Test Pin. 



CLP2 —TL 

(OPTICAL BLACK) 



J~L 



n 



Application circuit (2H Type) 



(§ S 



<OED- 







Note) 1. LPF is an abbreviation for Low Pass Filter. 

2. DL is an abbreviation for Delay Line 

3. DTL is an abbreviation for DETAIL. 



-660- 



SONY® 



Operation 



Black 
White 
Black 



TV picture 



— f(n) 



f(n-1) 



f(n-2) 



S 2 (2Htype)MCn-l)-™±J^ L^lTL 



1H delay 



2H delay 



"ifL 



S] ( 1H type)= f(n) - f 2 (n - 1) 



n 



If 



It can execute vertical direction outline emphasis by composing S! or S 2 with a Y signal. 
Example) The case of 2H type 



(n-1) 



f (n-1)+S2 



-U* % * 



Tl 



Black 
White 
Black 



661 - 



SONY® 



CXA1270N 



Y! Amp control characteristics 



Y 2 Amp control characteristics 



3 10 
o 








14 
13 














































\l 
























1 1 






















m 


10 






















;o 






















i- 


9 
8 
7 
6 






















3 
O 






















>- 




































































b 























2.5 3 

Yi CONT (V) 



2.5 3 3.5 

Y 2 CONT(V) 



Slice level (Power input conversion) 



AP Amp control characteristics 



zuu 






















£ 180 

c" 160 
o 






1 


















I 




















8 120 

g- 100 

| 80 
o 

0. 

■^ 60 
CD 
> 
® 40 

CD 
O 
















i 
j 




























/ 








i 








/ 








i 








1 
























. 


C/) 20 








1 
i 











12 3 4 5 

SLICE CONT (V) 

Note) See the Electrical Characteristics P.4, No.7 



10 


1 


































8 




















6 






















m 

3 2 

Q. 

< -2 








































































































-6 
-8 















































AP CONT (V) 



662- 



SONY® 



Package Outline Unit: mm 

20pin VSOP (Plastic) 250mil 

*6.5 ±(U 



MMMM 



,1 -2 5-q.i 



0.2 2-o:05 



o , 

mrnnt 



11 



10 

0.6 5 



±0 - 12 0.15+8:81 ! 




(uTnnnnnnnnJ 



-^ 




-H 




c, 


«-* 




--». 


u 


-10 



Detailed diagram of A VSOP - 2 P — L01 

Note) Dimensions marked with * do not include residual resin 



-663 



SONY. 



CX20095A/CX20186 



Video Output 



Description Package Outline 



Unit: mm 



CX20186 



The CX20095A/CX20186 is a bipolar IC de- 
signed as a driver of 75 ft line (transmission and 
receiving line) used in the video signal system. It is 
comprised of a 75 ft line drive, receiving amplifier 
and 6dB amplifier for multi-purpose applications. 



Features 

• Low power supply voltage operation, 
Vcc = 5V (Standard). 

• Transmission/Receiving amplifier has a built-in 
sync chip clamp. 

• Bilateral communication configuration is possible 
with one line. 

• Driver amp and 6dB amp are provided with 
power-saving function. 

• Simple superimpose is possible with the trans 
amp. 



Structure 



Bipolar silicon monolithic IC 



Absolute Maximum Ratings (Ta = 25°C) 

• Supply voltage VCC 17 V 

• Operating temperature Topr —10 to +65 °C 

• Storage temperature Tstg —55 to +150 °C 

• Allowable power dissipation Pd CX20095A 500 mW 

CX20186 650 mW 



CX20095A 



14 pin SOP 



O 



6X1.27 = 7.62 



2.25MAX 



UUIJUUUU 

1 1 0-45 



J 0.1-0.05 

- dlO 15MAXI 



1.27 + 005 l| 2' 

— 0.2-0.03 -H 



655553 



14 pin DIP 



U U U U U i_l U * 



< 

CO 
<P.. 




Oto 
.15° 



6X2.54 = 15.24 




11 2±0.15 



Recommended Operating Condition 

• Supply voltage VCC 



4.8 to 5.2 



-664 



SONY® 



CX20095A/CX20186 



Block Diagram and Pin Configuration (Top view) 




RE C u E l r VE Q^CSUFFER 



TRANS 
IN 



DRIVER 
IN 



®- 



SYNC 
TIP 
CLP 



(3> 



SYNC 
TIP 
CLP 



6dBAMP ^ 
OUT <4> 



T/R (5> 



6dBAMP ( 6W 
IN v ^ 



GND 



6dB 
AMP 



CLP 
LEVEL DC 







i 



_ POWER 
SAVE 



i 



-& 



DRIVER 
AMP 




VCC 



BIAS. 
CONTROL 



TRANS. 
OUT 



SYNC 
TIP 
CLP 



^) SAG. 
Y C.T.O 



©RECEIVE 
IN 




POWER 
SAVE 



-,,_^ SAI 
^^C.D 



DRIVER 
AMP 



SAG. 
O 



665 



SONY® 



CX20095A/CX20186 



Pin Description 

Standard terminal voltage (DC voltage when no signal is input, Ta = 25°C. See Electrical Characteristics 
Measuring Circuit Diagram) Unit: V 



No. 


Name 


Voltage (V) 
standard value 


Description 


1 


RECEIVE OUT 


1.65 


When Pin 5 is at "H", the signal input from Pin 1 is output 

with gain dB. 

DC is output when Pin 5 is at "L". 


2 


TRANS IN 


1.28 


Trans amp input: As sync chip clamp may result, a low 
impedance input is required. 


3 


DRIVER IN 


1.28 


Drive amp input: As sync chip clamp may result, a low 
impedance input is required. 


4 


6 dB AMP OUT 


2.35 


The signal input from Pin 6 is output with gain 6 dB. 


5 


T/R 





Mode switching terminal Trans/Receive: Receive mode at 
"H" (over 4V) and Trans mode at "L" (less than 1 V). 


6 


6 dB AMP IN 


2.45 


6 dB amp input: Input impedance more than approx. 1 kft, 
DC 2.4V 


7 


GND 







8 


SAG.C.D.O. 


1.29 


The Pin 9 sag is corrected by adding the sag component in 

the Pin 9 output. 

Refer to Electrical Characteristics Measuring Circuit Diagram. 


9 


DRIVER OUT 


1.08 


Driver amp output: 75 D. line drive is output. 

The signal input from Pin 3 is output with gain 6 dB. 


10 


RECEIVE IN 


1.74 


Receiving amp input: As sync chip clamp may result, a low 
impedance input is required. 


11 


SAG.C.TO. 


1.30 


The Pin 1 2 sag is corrected by adding the sag component in 

the Pin 1 2 output. 

Refer to Electrical Characteristics Measuring Circuit Diagram. 


12 


TRANS. OUT 


1.10 


Trans amp output: The signal input from Pin 2 when Pin 5 is 

at "L" is output to the 75 ft line with a gain of 6 dB. 

A DC voltage determined at Pin 1 3 is output when Pin 5 is at 

"H". 


13 


BIAS. CONTROL 


2.13 


When Pin 5 is at "H", its voltage is varied to vary the Pin 1 2 
output (DC) in turn. 

By linking with Pin 5, simple superimpose can be possible in 
the Pin 1 2 output. (In this case, the Pin 1 output is affected). 


14 


VCC 


5.0 


+ 5.0V. 



666- 



SONY® 



CX20095A/CX20186 



o> 

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I 



667- 



SONY® 



CX20095A/CX20186 



Electrical Characteristics Test Circuit 



pO~Tr 




(Input signal) 



668 



SONY® 



CX20095A/CX20186 



Application Circuit 

Transmission and receiving reference circuit diagram (Trans amp. Receive amp) 



Receiving 
output O 



4.7/* 

Transmission O )P~~® 

output 



-Q+5V 




Transmission/Receiving 
line (7 5 il) 



Trans/Receive mode signal line 
H (5 V): Receive mode 
L (OV): Trans mode 



Driver amp, 6 dB amp external reference circuit diagram 



4.7 /xdBP 



Driver amp M 

input O » W 

6 dB amp q 
output 



10/idBP 
BdBamp Q » M . (6 
input 



*^tr 






HD + 5V 




75 n line 



SW1 : 6 dB amp power saving mode when switched on. 
SW2: Driver amp power saving mode when switched on. 



-669- 



SONY® 



CX20095A/CX20186 



Temperature Characteristics 



dB 
£ +1 

3 
CO 










































2L 

E 










































c 
« 

1° 

CD 










































> 
C 

5 










































Q. 

E 






















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c 

CO 























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2 +1 

CO 

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E 




















































































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CO 








































> 






















a. 






















fc 

CO 













































50 



Ambient temperature (Ta) 



Ambient temperature (Ta) 



dB 

2 

3 +1 

CO 

& 

E 
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0) 

1 o 

CO 










































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3 










































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CO 

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< 































































Ambient temperature (Ta) 



25 50 

Ambient temperature (Ta) 



'Note) Gain at 25°C is assumed to be dB. 



670 



CCD Delay Line 




6) CCD Delay Line 



Type 


Application 


Function 


Page 


CXL1009P 


Video disk 


CMOS-CCD delay line for time base 
corrector, 300mil shirink-DIP 


673 


CXL1008P/M 


VCR 


NTSC skew compensate 


682 


CXL5001P/M 


General purpose 


NTSC 1H CMOS-CCD delay line 


694 


CXL5002P/M 


General purpose 


NTSC 1/2H CMOS-CCD delay line 


701 


CXL5003P/M 


General purpose 


PAL 1H CMOS-CCD delay line 


707 


CXL5005P/M 


General purpose 


NTSC 1H CMOS-CCD delay line, with 
PLL 


714 



-672- 



SONY. 

CMOS-CCD Signal Processor for TBC 



CXL1009P 



Description 

CXL1009P is a CMOS-CCD signal processor 
developed for Time Base Corrector (TBC). 

Features 

• Low power consumption 160 mW (Typ.) 

• Wide variable frequency range (15.2 to 27.2 MHz) 

• Built-in peripheral circuits 

Functions 

• 680 bit CCD register x 2 

• Clock drivers 

• Autobias circuit (For Audio/Video) 

• Sync tip clamp circuit 

• T-type flip-flop circuit 

• Timing generator circuit 

• Output feedback circuit 

Structure 

CMOS-CCD 

Absolute Maximum Ratings (Ta=25°C) 



Package Outline 



Unit: mm 



Supply voltage 
Supply voltage 
Operating temperature 
Storage temperature 
Allowable power dissipation 



Vdd 11 V 

Vcl 6 V 

Topr -10 to +60 °C 

Tstg -55 to +150°C 

Pd 1 W 



Recommended Operating Conditions 

• Supply voltage Vdd 9 

• Supply voltage Vcl 9 

Recommended Input Signal Conditions 



V ±5% 

V ±5% 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Input amplitude 


VlNP-P 


- 


1.0 


1.28 


Vp-p 



20 pin DIP (Plastic) 







i l|j^ °' to 




DIP-20P-02 



20 pin DIP (Plastic) 




DIP-20P-121 



Recommended Clock Conditions 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Remarks 


Clock frequency 


fCK 


15.2 


21.4 


27.2 


MHz 


Pulse 

or 

Sinewave* 


Clock amplitude 


Vckp-p 


1.0 


2.0 


4.0 


Vp-p 


Duty (during pulse) 


Dy 


40 


50 


60 


% 



*Note) During pulse the clock requires a pulse as shown in Fig. 1 . 




E88Z37-YA 



673 



SONY® 



CXL1009P 



Recommended Clock Waveform (Pulse) 



6ns 
90% 

50% 



JU /o f- 

10%Jl 



36ns < T<66ns- 

>• <xt- 

6ns 
90% 



|J — W 



50% 
10% 



0.4<oK0.6 



2.0 V 



Fig. 1 



Block Diagram and Pin Configuration (Top View) 



Vod(A)(2 




AUT01 (6 



1")v$s (D) 



1l)Vss(D> 



-674- 



SONY® 



CXL1009P 



Pin Description 



No. 


Symbol 


I/O 


Description 


1 


OUT 





Output 


2 


Vdd (A) 




Power supply 1 (Analog) 


3 


FEED IN1 


I 


Feedback input 1 


4 


IN1 


I 


Input 1 


5 


Vgg1 


I 


Gatel 


6 


AUT01 





Autobias 1 


7 


Vss (D) 




GND (Digital) 


8 


Vcl 




Power supply 2 (Digital) 


9 


Vss (D) 




GND (Digital) 


10 


Vdd (D) 




Power supply 1 (Digital) 


11 


Vss (D) 




GND (Digital) 


12 


CLK 


I 


Clock input 


13 


Vcl 




Power supply 2 (Digital) 


14 


Vss (D) 




GND (Digital) 


15 


AUT02 





Autobias 2 


16 


Vgg2 


I 


Gate 2 


17 


IN2 


I 


Input 2 


18 


FEED IN2 


I 


Feedback input 2 


19 


Vdd (A) 




Power supply 1 (Analog) 


20 


Vss (A) 




GND (Analog) 



Electrical Characteristics 1 





Ta = 


25°C, Vdd = 9.0V, Vcl = 5.0V, See the Electrical Characteristics Test Circuit. 


Item 


Symbol 


Test conditions 


SW condition 


Test 
point 


Min. 


Typ. 


Max. 


Unit 


SW1 


SW2 


SW3 


SW4 


Pin voltage 


Vautc-1-dc 


Pin 6 voltage 


b 


a 


a 


a 


V6 


4.0 


5.5 


7.0 


V 


Vauto2-dc 


Pin 15 voltage 


b 


a 


a 


a 


V5 


3.5 


5.0 


6.5 


V 


VlN-DC 


Pins 4 and 1 7 voltage 


b 


b 


a 


a 


V7 


3.5 


5.0 


6.5 


V 


Vgg-dc 


Pins 5 and 16 voltage 


a 
b 
c 


a 


a 


a 


V8 


1.0 


2.0 


3.0 


V 



-675- 



SONY® 



CXL1009P 



Electrical Characteristics 2 



Ta = 25 °C, Vdd = 9.0V, Vcl = 5.0V, See the Electrical Characteristics Test Circuit. 
Test conditions: Set the voltage of pins E1 and E2 as follows: 
El = Vgg-dc, E2 = VAUT02-DC + 0.65V or Vautoi -DC 



Item 


Symbol 


Test conditions 


SW condition 


Test 
point 


Min. 


Typ. 


Max. 


Unit 


SW1 


SW2 


SW3 


SW4 


Supply 
current 


Idd 


250 kHz, 1 .OVp-p sine wave input 


b 


a 


a 


a 


A1 


- 


7 


12 


mA 


Icl 


A2 


- 


20 


28 


mA 


Insertion 
gain 


IG 


250 kHz, 1 .0Vp-p sine wave input 
irs = om™ f Output voltage (Vp-p) ] 
[ 1Vp-p J 


a to c 


a 


a 


b 


V2 


-3 





3 


dB 


Frequency 
response 


fG 


Dissipation at 3.58 MHz vs. 250 kHz 

fG = 20log (V3.58MHz/V250kMz) 

V3.58MHz: Output signal voltage 
during 3.58 MHz input 

V250kMz: Output signal voltage 
during 250 kHz input 


a toe 


a 


b 


b 


V2 


-3 


-1 





dB 


Differential 
gain 


DG 


5-staircase wave (See Fig.) input 
Y=140IRE(=1.0Vp-p) 
Measuring with vectorscope.* 1 


a toe 


a 


c 


b 


S 


- 


3 


5 


% 


Differential 
phase 


DP 


- 


3 


5 


Deg 


Noise 


S/N1 


S: lnput=250 kHz, 1.0Vp-p sine 
wave 


b 


a 


a 


c 


V3 


50 


55 


- 


dB 


N: I nput= Alternating grounding 
point (rms) 


b 


a 


d 


c 


Aliasing 
noise 


S/N2 


Input =3.58 MHz, 1.0Vp-p 
sine wave * 2 


d 


a 


b 


d 


SA 


35 


50 


- 


dB 


Insertion gain 
difference 


A\G 


250 kHz, 1 .0Vp-p sine wave * 3 


a toe 


a 


a 


b 


V2 


- 


1 


2.4 


% 


DC output 

voltage 

difference 


/jVo-DC 


250 kHz, 1.0Vp-p sine wave * 4 


a toe 


a 


a 


a 


V1 


- 


- 


0.3 


V 



676 



SONY® 



CXL1009P 



Note) 

*1. Differential gain and differential phase conditions. 



e 



5-staircase wave Fig. 

I Chroma 40IRE 



mi 



140IRE(1.0Vp-p) 



40IRE 



1H63.5/*S 



"2. Aliasing noise 

Measure with a spectrum analyzer the 4.43 MHz output signal voltage at 3.58 MHz input 
(clock frequency 16.02 MHz). 



3.58 4.43 
Frequency (MHz) 



Aliasing noise 



*3. Insertion gain difference 

With the insertion gain of clock frequencies of 15.2 MHz, 21 .4 MHz and 27.2 MHz, determine maximum value as 
IGmax [dB] and minimum value as IGmin [dB]. Insertion gain difference A IG is defined as follows. 



ZIIG 



■) fJOGmax/aO) — •) fJOGmin/20) 

1 QOGmax/20) + -\Q{\Gmin/20) X ^0° [ ">\ 



*4. DC output voltage difference 

With the DC output voltage of clock frequencies of 15.2 MHz, 21 .4MHz and 27.2 MHz, determine maximum value 
as Vo-DCmax and minimum value as Vo-DCmin. DC output voltage difference A Vo-dc is defined as follows. 




A Vo-dc - Vo-dc max - Vo-dc min [V] 



677 



SONY® 



CXL1009P 



Electrical Characteristics Test Circuit 



fCK - 15.2 MHz, 2Vp-p sine wave 
fCK = 21.4 MHz, 2Vp-p sine wave 
fCK = 27.2 MHz, 2Vp-p sine wave 
(ck = 16.02 MHz, 2Vp-p sine wave 

_ Vcl 5V 




fa LPF frequency 
characteristics 

IdB) 



^T 



250 kHz, 1 Vp-p sine wave 
3.58 MHz, 1 Vp-p sine wave 
5-staircase wave (See Fig.) 
GND 



BPF frequency 
characteristics 

IdBI 




~) «n«lyi»r J §3 



4.43M 7.6M(HZ) 050 800 5.0M 10.7M(Hz) 

Frequency Frequency 



Application Circuit (Video) 



Application Circuit (Audio) 





-678 



SONY® 



CXL1009P 



Frequency characteristics 


















































^ 


\> 




























V 


y> 




CO 
T3 
























\ 


cS — ■ 


Gain( 
ro 


























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— - fC.K= 1S9MI- 


t 






yr 




• 


f< 


:K= 21.4MH 
DK= 27.2MH 


z 








-4 











































100K 1M 

Frequency (Hz) 



10M 



Delay time vs. Clock frequency 











/ 














90 










































feo 

CD 










































£ 
£ 70 

CO 
CD 

Q 

I 60 

a 


















































































1- 
50 











































15 



25 



fcK - Clock frequency (MHz) 



Insertion gain vs. Clock frequency 



Frequency response vs. Clock frequency 



£. 






















m 1 
2. 










































ion gai 
o 
























































I 










































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15 25 

fcK - Clock frequency (MHz) 

























00 

2, 






















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o 

a. . 
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cr 
£ 

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15 25 

fcK - Clock frequency (MHz) 



Differential gain vs. Clock frequency 



Gate voltage vs. Clock frequency 



1U 






















Vgg - Gate voltage (V) 
j> b u 










• 














y 












































_c 












































o> 












































.CO 






































































































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O 




















































Q 

























































































15 25 
fcK - Clock frequency (MHz) 




15 25 
fcK - Clock frequency (MHz) 





679- 



SONY® 



CXL1009P 



Insertion gain vs. Supply voltage 



m 1 



CD -2 



















1.4M 







































































































































































































8.5 9.0 9.5 

Vdd - Supply voltage (V) 



Frequency response vs. Supply voltage 

2 



g> -1 



-2 



-3. 






































































































































































































8.5 9.0 

Vdd - Supply voltage (V) 



9.5 



Differential gain vs. Supply voltage 



Gate voltage vs. Supply voltage 



10 



















I I I 

fCK- 91 4MH7 - 


























































































































— 





























































8.5 9.0 9.5 

Vdd - Supply voltage (V) 

Insertion gain vs. Supply voltage 



-3 















I I I 












. 































































































































































































4.75 5.00 5.25 

Vcl- Supply voltage (V) 



2.5 



2.0 



































r 






























































_ 







































































































1.5 

8.5 9.0 9.5 

Vdd - Supply voltage (V) 
Frequency response vs. Supply voltage 



-1 



-2 



-3 















, I II 





















































































































































































4.75 5.00 

Vcl- Supply voltage (V) 



5.25 



680- 



SONY® 



CXL1009P 



Differential gain vs. Supply voltage 



Gate voltage vs. Supply voltage 



10 









































































































































^. 





























































4.75 5.00 

Vcl - Supply voltage (V) 



5.25 



Insert gain vs. Ambient temperature 



m 

T3 



O 

1 -2 



<2 -3 















1 1 1 























































































































































































20 40 60 
Ta- Ambient temperature (°C) 

Differential gain vs. Ambient temperature 

5 



C- 


4 


c 




ffl 




O) 




ra 


3 






c 




d) 








0) 




3= 


X 


Q 




1 
(0 


1 


a 

















I 


1.4M 























































































































































































20 40 60 
Ta - Ambient temperature (°C) 



2.5 



2.0 



(3 

















I I 











































































































































































































1.5 
4.75 5O0 5.25 

Vcl - Supply voltage (V) 

Frequency response vs. Ambient temperature 

1 

ST 
-o 

o> 
<n 

c 
o 

Q. 

£ 

O 

i-2 

0) 

~ 4 20 40 60 

Ta - Ambient temperature (°C) 

Gate voltage vs. Ambient temperature 

2.0 















I I I 























































































































































































o 
? 1.5 



O 



1.0 






































































































































































































■ 



20 40 60 
Ta- Ambient temperature (°C) 



-681 - 



SONY. 



CXL1 008P/M 



CMOS-CCD Signal Processor for Skew Compensation 



Description 

CXL1008P/M are CMOS-CCD signal proces- 
sors developed for the varying-speed video sig- 
nal for home-use 8 mm VTRs. 

Features 

• Low power consumption 1 05 mW (Typ.) 

• Built-in peripheral circuit 

• Adjustment is necessary for one part. 

Functions 

• 1/2H 359-bit, direct 20-bit CCD register 
. • Clock driver 

• Timing oscillation circuit 

• Automatic bias circuit 

• Sink chip clamp circuit 

• Dummy VD insert circuit 

• Sample hold circuit 

Structure 

CMOS-CCD 

Absolute Maximum Ratings (Ta = 25°C) 



• Supply voltage 

• Operating 
temperature 

• Storage 
temperature 

• Allowable 
power 
dissipation 



Vdd 
VCL 

Topr 
Tstg 
PD 



11 
6 

-10 to +60 
-55 to +150 



CXL1008P1000 mW 
CXL1008M500 mW 



Recommended Operating Conditions 

• Supply voltage Vdd 9V±5 



Vcl 



5V±5 



Recommended Clock Conditions 

• Clock input amplitude Vclk 0.1 5 to 1 .0 (0.3 Typ.) 

• Clock frequency fCLK 10.738635 



Package Outline 



Unit: mm 



CXL1008P 



28 pin DIP (Plastic) 



innnnnnnnr 



o 



o 



UUUUUUUUl 





33 












1. 


32 
















0.5 "■ 1 J 
j 2 ±0.15]' 


•- o 





DIP-28P-03 



CXL1008M 



28 pin SOP (Plastic) 



BflflRBflaaflBflRflff- 



■ 4Z7I 0.15 



1.2 7 0.1 5- $5 



SOP-28P-L02 



Vp-P 
MHz 



'60924 -ST 



682- 



SONY® 



CXL1008P/M 



Block Diagram 



SIG INI 



AUTO 



1 



FEED SIG 
IN DELAY 

FEED CCD SIG 

OUT OUT IN2 



ru 




SIG 
OUT 



>n 



Pin Configuration 
(Top View) 



T8 © 

EXT VD © 

JOG IN © 

Vss ® 

SIG OUT © 

V DD © 

SIG DELAY © 

REC/PB @ 

CCD OUT @ 

FEED OUT &) 

FEED IN © 

SKEW IN © 

T9 @ 

T10® 



CXL1008P/M 



iV C L 
AUTO 
SIG IN2 
SIG INI 
MUTE IN 
T7 
T6 
CLK IN 
T5 
T4 
T3 
T2 
Tl 
Vss 



■ 



/\ 



-683 



SONY® 



CXL1008P/M 



Pin Description 



No. 


Symbol 


I/O 


Condition 


Description 


Impedance 

(a) 


1 


Vss 






GND 




7 


CLK IN 


I 


0.3Vp-p 


Input the sinewave of 3 fsc (10.738635 MHz) 


>50k 


10 


MUTE IN 


I 


5V when mut- 
ing, normally 
OV 


The video signal mute is generated at High level. See the 
Logic Table of Signal Output Selection State (Table 1). 


>100k 


11 


SIG INI 


I 


1 . 1 Vp-p or 
less 


Signal input pin of CCD DL 
Enter composite video signal. 


>100k 


12 


SIG IN2 


I 


2.2 Vp-p or 
less 


Signal input pin of the through side 
Enter composite video signal. 


>100k 


13 


AUTO 







The DC level of automatic bias is output. 


10k 


14 


VcL 




+ 5V 


Power supply 1 




16 


EXT VD 


I 


When VD is 
inserted, 5V 


Use this pin when VD is inserted to the video signal in the 
external dummy VD signal input. 


>100k 


17 


JOG IN 


I 


JOG mode 

5V 
PB/REC 

mode OV 


JOG/NORMAL PB selection pin 

See the Logic Table of Signal Output Selection State (Table 

1). 


>100k 


18 


Vss 






GND 




19 


SIG OUT 







Final output 


0.6 to 1.5k 


20 


V DD 




+ 9V 


Power supply 2 




21 


SIG DELAY 


I 




After the output from pin 23 CCD OUT passes through 
LPF, input it to the same pin and insert clamp and VD. 


>100k 


22 


REC/PB 


I 


5V when PB 
OV when REC 


Operate the clock at High when PB. 
Stop the clock at Low when REC. 


>100k 


23 


CCD OUT 







Direct output from CCD DL 


0.6 to 1.5k 


24 


FEED OUT 







Feedback DC output 


10k 


25 


FEED IN 


I 




Smoothing capacitor connection pin of the bias commutation 
loop on the output circuit 


>100k 


26 


SKEW IN 


I 




Select Direct DL and 1/2H DL signals when High and 

Low, respectively. 

See the CCD/DL mode selection logic table (Table 2). 


>100k 



Note) T1 through T10 test pins must be connected as shown in the example of the application 
circuit because of the IC internal circuit. 

Precautions 

Countermeasures for electrostatics are necessary because some pins have low electrostatic strength 
(particularly Pin 26: SKEW IN). 



-684- 



SONY® 



CXL1008P/M 



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-685 



SONY® 



CXL1008P/M 



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-686 



SONY® 



CXL1008P/M 



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SONY® 



CXL1008P/M 



Note) 

1 . Current value when the clock is in operation in the PB or JOG mode. 

In the REC mode, the clock is stopped (Pin 22 is at low) to save power. 

2. With the signal input pin voltage value, the video signal sync tip is clamped. 

3. Vdo1 is a CCD OUT output voltage when the SIG IN1 input voltage is Vdi1 
Vdo2 is a SIG OUT output voltage when the SIG IN2 input voltage is Vdi2. 

Vdo1 and Vdo2 represent outputs for the sync tip clamp level when a white level signal is in- 
put as shown in the diagram. 



Output signal 



Vdo 




l.OVp-pi 
Vdi Input signal 



4. ADab denotes an output voltage difference of CCD OUT when the direct DL and 1/2H DL are 
switched. 

5. IGCCD is a gain when a 1.1 Vp-p 100 kHz sinewave is input to SIG INI . 

Output amplitude (Vp-p) 



IGCCD = 20 log 



1.1 Vp-p 



It is measured by giving a Vdi1 + 0.6 bias with VBias. 

IGin2 and IGPL are SIG OUT gains when 2.2 Vp-p 100 kHz sinewave is input to each of SIG IN2 

and SIG DELAY pins. 



IGin2 = 20 log 



Output amplitude (Vp-p) 



2.2 Vp-p 
It is measured by giving a Vdi2 + 1.1V bias with VBias. 



SONY® 



CXL1008P/M 



6. AGab is a gain difference between the direct DL and 1/2H DL. 

7. It represents a loss at 3.58 MHz compared with 100 kHz. 

It is measured by raising the SIG IN1 input pin by 0.6V higher than the sync tip clamp level (Vdi1 ) 
with VBias. 



3.85 MHz 300 m Vp-p sinewave ' 
100 kHz 300 mVp-p sinewave 



SIG INI DC 



V Bi as =Vdil+0.6V 



Fccd=20 log 



V3.58 MHz output 



V100 kHz output 

8. It represents a loss at 10 MHz compared with 100 kHz. 

It is measured by raising the SIG IN2 or SIG DELAY pin by 1.1V higher than the sync tip 
clamp level (Vdi2 or Vdi3) with VBias. 

9. AFab is a frequency response difference between the direct DL and 1/2H DL. 



10. 



U 



OB 



il 



U3I 



Chroma 40 IRE 



/l.l Vp-pat 
^2.2 Vp-p at 



DGccd \ 

DGin2 or DGdl) 



40 IRE 



1H 63.5^s 

DG is measured with a vectorscope in each mode of the 5-stage waves. 

11. Measure S/N of the BPF 100 kHz to 4.2 MHz in the subcarrier trap mode with a video noise 
meter. 



12. 



SIG DELAY 
Input waveform 




EXT VD input 



SIG OUT 
Output waveform 





2Vp-p 
t _ 




Set a voltage value at Vvd when inserting EXT VD to the 2 Vp-p signal output waveform sync 
tip of SIG OUT. 



689 



SONY® 



CXL1008P/M 



CLOCK 



3fsc (10. 738635MHz) Sinewave 
0.15 to l.OVp-p 



Function Outline 



Output signal selection sig IN2 

(PB) 



SIG DELAY 
(JOG) 



5^ 



^f 



SIG OUT 



50mV 
REF 



The video output signal is selected by selecting the output switch for three signals: Pin 10 
(MUTE IN), Pin 17 (JOG IN) and Pin 16 (EXT VD). 
Logic Table of Signal Output Selection State 



Input control signal state 


Video signal output selection state 


JOG IN 


MUTE IN 


EXT VD 


PB 


JOG 


VD insert 


MUTE 








. 


O 


X 


X 


X 








1 


O 


X 


X 


X 





1 





X 


X 


X 


o 





1 


1 


X 


X 


X 


o 


1 








X 


o 


X 


X 


1 





1 


X 


X 


o 


X 


1 


1 





X 


X 


X 


o 


1 


1 


1 


X 


X 


o 


o 



Table 1 

Note) 1. Figures "0" and "1" of the input control signal state are equivalent to "Low" and 
"High" of logic. 

2. Items marked with the symbol "o" in the video signal output selection state are 

select ed. 

3. PB = JOG IN . MUTE IN 

JOG = JOG IN . MUTE IN . EXT VD 



VD insert = JOG IN 
MUTE = MUTE IN 



EXT VD 



CCD selection 



Logic Table of Signal 
Output Selection State 



SIG 
INI 



1/2H (359bit) 



D (20bit) 




CCD OUT 



Control signal 


CCD DL mode 


SKEW IN 


D 


1/2H 





X 


o 


1 


o 


X 



SKEW IN 



Table 2 



690 



SONY® 



CXL1008P/M 



SKEWo_ 





CXL1008P/M 




3fsc 
0.3VP-P 
SINE WAVE 



Transistor to be used 
PNP:2SA1175 



tW» — * O SIGNAL INPUT 



Frequency characteristics (Ta = 25°C) 



en 



10K IOOK 

f-Frequency [Hz] 





691 - 



SONY® 



CXL1008P/M 



Supply voltage (Vcl) vs. 
Insert gain (IGCCD) 



o 



2 
3 



Vcl — Supply voltage [V] 

Supply voltage (Vcl) vs. 
Differential gain (DGCCD) 






Vcl — Supply voltage [V] 
Supply voltage (Vdd) vs. 







Insert gain (IGCCD) 













































































































































































































Supply voltage (Vcl) vs. 
Frequency characteristics (fCCD) 



Q 
O 
O 4.75 






5.00 3.25 

Vcl — Supply voltage [V] 
Supply voltage (Vcl) vs. 
Output pin voltage (Vdol) 



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Vcl — Supply voltage [V] 

Supply voltage (Vdd) vs. 
Frequency characteristics (fCCD) 



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Vdd — Supply voltage [V] 



Vdd — Supply voltage [V] 



692- 



SONY* 



CXL1008P/M 



Supply voltage (Vdd) vs. 
Differential gain (DGCCD) 



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Ambient temperature (Ta) vs. 
Insert gain (IGCCD) 

























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Ta — Ambient temperature [°C] 

Ambient temperature (Ta) vs. 
Differential gain (DGccd) 



Supply voltage (Vdd) vs. 
Output pin voltage (Vdo1) 



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Ambient temperature (Ta) vs. 
Frequency characteristics (fCCD) 



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Ta — Ambient temperature [°C] 

Ambient temperature (Ta) vs. 
Output pin voltage (fCCD)(Vdo1) 



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Ta — Ambient temperature [°C] 



20 40 60 

Ta — Ambient temperature [°C] 



693 



SONY. 



CXL5001P/CXL5001M 



CMOS-CCD 1 H Delay Line for NTSC 



Description 

The CXL5001 P/CXL5001 M are general purpose CCD 
delay line ICs which provide 1 H delay time of NTSC. 

Features 

• Low power dissipation 80 mW (typical) 
. Small size package (8-pin DIP, MFP) 

• Low differential gain DG=3% (typical) 

• Input signal amplitude 180IP.E (=1.28Vp-p, max.) 

• Low input clock amplitude operation 1 50 mVp-p (min.) 

• On chip peripheral circuits. 

Functions 

• 680 bit CCD register 

• Clock drivers 

• Autobias circuit 

• Synchronized tip clamp circuit 

• Sample and hold circuit 

Absolute Maximum Ratings (Ta=25°C) 



Package Outline 



Unit: mm 



• Power supply voltage 1 Vdd 1 1 


V 


• Power supply voltage 2 Vcl 6 


V 


• Operating temperature Topr —10 to +60 


"C 


• Storage temperature Tstg —55 to +150 


°C 


• Allowable power dissipation Po CXL5001 P 480 


mW 


CXL5001 M 350 


mW 


Recommended Operating Conditions 




Vdd 9V±5% 




Vcl 5V±5% 





Recommended Clock Conditions 

• Input clock amplitude Vck 1 50 mVp-p to 1 .0 Vp-p 

(Typical 250 mVp-p) 

• Clock frequency fc« 10.7 MHz 

Structure 
CMOS-CCD 



CXL5001P 



8 pin DIP 




CXL5001M 



8 pin MFP 



6-5 MAX 



2.25 M AX 




0.45 + ^+1-27 +0Q5 

i i 2-003 

3x1.27 = 3.81 



SEB 



-X-gTo; 



694 



SONY® 



CXL5001P/CXL5001M 



Block Diagram 



IN AUTO 

KD — ®- 



- f AUTOBIAS CIRCUIT 



FEED 

-0- 



L CLAMP CIRCUIT 



OUT 



1BIT) ^ 



ref. 



(1BIT) 



680 BIT SHIFT REGISTERJ -|^>4s^^M>i|AM^ 



<D — d> 

Vss V cl 



CLOCK DRIVERS 



4 



CLK 



DUTY CONTROL 
CIRCUIT 






Pin Description 



Pin No. 


Symbol 


Description 


Impedance 

[n] 


Pin No. 


Symbol 


Description 


Impedance 

[n] 


1 


Vss 


GND 




5 


OUT 


Signal output 


600 to 1 k 


2 


Vcl 


5V power supply 




6 


FEED 


Feedback DC output 


>100k 


3 


CLK 


Clock input 


>100k 


7 


AUTO 


Autobias DC output 


10k 


4 


Vdd 


9V power supply 




8 


IN 


Signal input 


>100k 



-695 



SONY® 



CXL50O1P/CXL5001IVI 



Electrical Characteristics 



(Ta=25°C, Vdd=9.0V, Vcl=5.0V, fcK=10.7 MHz. Vck=250 mVp-p sine wave, 
See "Electrical characteristics measuring circuit") 



Item 


Symbol 


Measuring condition 


SW condition 


Measuring 
point 


Min. 


Typ. 


Max. 


Unit 


SW1 


SW2 


Supply current 


loo 


INPUT=250 kHz, 
1 .28 Vp-p. 


a 


a 


A1 


- 


4 


5 


mA 


lei 


A2 


— 


9 


11 


mA 


Insertion gain 


IG 


INPUT=250 kHz, 
1 .28 Vp-p 
IG=20log (Output 
voltage (Vp-p)/ 
1.28[Vp-p]) 


a 


a 


V1 


-3 





3 


dB 


Frequency 
response 


fG 


fG=20log (V3.58MH*/ 

V250kHz) (Note 1) 


b.c 


b 


V1 


-3.0 


-2.1 


— 


dB 


Differential gain 


DG 


5-staircase wave input 
Y=140IRE (=1.0 Vp-p) 
Measure S point with 
vectorscope (Note 2) 


e 


a 


S 


— 


3 


5 


% 


Differential phase 


DP 


- 


3 


5 


deg 


Allowable input 
amplitude 


VlN-AC 




— 


— 


— 


— 


— 


1.28 


Vp-p 


Noise 


S/N 


S: input=250 kHz 
1.0 Vp-p 
output (Vp-p) 


f 


a 


V2 


55 


60 


- 


dB 


N: input=DC 
output (Vrms) 


d 


a 


V2 


Output DC voltage 


VlN-AC 




d 


a 


V3 


3.5 


5.0 


6.5 


V 


Vauto-dc 




V4 


3.5 


5.0 


6.5 


V 


Vfeed-oc 


INPUT=250 kHz, 
1 .28 Vp-p. 


a 


a 


V5 


1.3 


2.3 


3.3 


V 


Vout-oc 


V6 


1.7 


2.7 


3.7 


V 



696- 



SONY® 



CXL5001P/CXL5001M 








> 








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in 


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CM 


n 









-697- 



SONY® 



CXL5001P/CXL5001M 



Note 1) Frequency characteristics measuring condition 



V3.58 mhz (Output signal voltage [Vp-p] at 3.58 MHz input) 
V250 kHz (Output signal voltage [Vp-p] at 250 kHz input) 

Set pin 8 (IN) voltage [V] = Vin-dc + 640 mV. 



3.58 MHz, 300 mVp-p sine wave 
250 kHz, 300 mVp-p sine wave 




640 mV (adjust with VgiAS' 



Note 2) Differential gain and differential phase measuring condition 



5-staircase wave signal 

— ;■ f Chroma 40IRE 



u 



ea 



nil 



140IRE(1.0Vp P ) 



40IRE 



1H 63.5^s 
DG and DP are measured at output S point by vectorscope. 



Note 3) LPF frequency characteristics 



Note 4) BPF frequency characteristics 



(Delay time — 140ns) 



[dB] 




5.8 10.7 
Frequency [MHz] 



[dBl 



-50 




50 200 4.1M10.7M 

Frequency [Hz] 



-698 



SONY® 



Application 



Composite video signal input o- 



CXL5001P/CXL5001M 



OX<F 0.01 ^f4= io.l„F 





L.P.F 



1H delay signal output 



Delay time = 140ns 
2SA1175 



Frequency response vs. Ambient temperature 



4 - 
20 



Input = 300 mVp-p 
3.58 MHz sine wave 



4—4- 



20 40 60 

Ta-Ambient temperature [ J Cl 



Frequency response vs. Power supply voltage 






■ ] 


[ 


1 

j. 


T 


j Input = 300mVp-p 
3.58 MHz sine wave 


1 


--r- 


-L. 


4- 


t— 









4 


-i 


i 


-i r f- 4-^---- 


? 


— — - 


- i — 


— 


_^_- 


— — ' — -t r — * — 






3 





..4... 


- i 


-T 


-i-_4--; - 






-r 


-+- 




__i. ^ _..i * .— 


4 






- ■-(■■ - 


-— 


, ; 



8.5 9.0 9.5 

VOD" Power supply voltage [V] 



0.01MF 



f , 10.7MHz 
CLK y 250mV sine wave 



Frequency response vs. Power supply voltage 



-\--\ 



Input = 300mVp-p 
3.58 MHz sine wave 



4 -4 



i- -- 



-f- 4 r 



4.7 5.0 5.3 

v CL" Power supply voltage [V] 

Insertion gain vs. Ambient temperature 



1 




i 




1 

.... 


Input = 
250 kH 


1.28 Vp-p 
z sine wave 





! 








■ ■ : ■■]'" 


T ! ^ 








1 


| i ■■ 


4 - 4 
, I ! , 










2 


--■■! - + -- 


f — 


*~ H 








\ 


1 

1 1 

1 








3 


-■'" '"-' 


— _j 

1 


, \ 

i 
! 









I 



20 20 40 60 

Ta-Ambient temperature [°C] 



699 



SONY® 



CXL5001P/CXL5001M 



Insertion gain vs. Power supply voltage 



Insertion gain vs. Power supply voltage 













I 


riput 


1.28 Vp-p 


— 


__ 


— 






250 kHz sine wave 


























































-■ 










.... . 










- — 

















_.. 




































4.7 5.0 5.3 

v CL" Power supply voltage [V] 

Differential gain vs. Ambient temperature 



2 - 















i i 


















i 


















i 






j 
















t r 








i \ 






I ! i 






. ' 


r ~~ r 




— 

- 








i i i : 




' ' ! | ! ! ! I ' 


! | ■- 

I 


i 


ill i 


i 



-20 20 40 60 

Ta-Ambient temperature [°C] 




8.5 9.0 9.5 

VDD" Povver supply voltage [V] 

Differential gain vs. Power supply voltage 




4.7 5.0 5.3 

VcL.-Power supply voltage [V] 



Differential gain vs. Power supply voltage 



Frequency response 



















| 


























4 






















3 










































2 


















O ' 


















1 
























1 





























1 












1 



8.5 9.0 

Vrjo- Po¥ver supply voltage [V] 



9.5 



10k 100k 

Frequency [Hz] 





1 J 






1 


III 






1 
| 


iji ! I 


i: ! ! 







— 1- 




j; 


t i 








1 








' 




,! 


! 
i 


Jl 












v 1 


in 


-1 


1 — M 




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i , 






OQ 

2 2 

c 










: 


. 


' 












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i 


















j 










: 


i\ 




<3 
















■ 












i 






-3 








r-4- 


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— H 


''■ 


















, 










W^ 


1 






1 










lu 




1 




! ! 


-4 








il 


li 
















iiil 




i !lii, 



1M 



-700- 



SONY. 



CXL5002P/M 



CMOS-CCD 1/2H Delay Line for NTSC 



Description 

CXL5002P/CXL5002M are general purpose CCD 
delay line ICs which provide 1/2H delay time of 
NTSC. 

Features 

• Low power dissipation 70mW (Typ.) 

• Small size package (8 pin DIP, SOP) 

• Low differential gain DG = 3 % (Typ.) 

• Input signal amplitude 180IRE (=1.28Vp-p, Max.) 

• Low input clock amplitude operation 150mVp-p 
(Min.) 

• On chip peripheral circuits. 

Structure 

CMOS-CCD 

Functions 

• 340 bit CCD register 

• Clock drivers 

• Autobias circuit 

• Synchronous Signal tip clamp circuit 

• Sample and hold circuit 



Package Outline 



Unit : mm 



Absolute Maximum Ratings (Ta = 25°C) 



• Supply voltage 1 Vdd 

• Supply voltage 2 Vcl 

• Operating temperature Topr 

• Storage temperature Tstg 

• Allowable power dissipation 

Po CXL5002P 
CXL5002M 



11 
6 

- 1 to +60 

- 55 to + 1 50 

480 
350 



V 
V 
°C 
V 

mW 
mW 



Recommended Operating Conditions 

Vdd 9V ± 5 % 

Vcl 5V ± 5 % 



CXL5002P 



8 pin DIP 



251 



<v 




0"tol5' 







* 


S3 


2 




in 


t- 


o 


co 






















z 




0.5 * 04 


z 




, 2 *o.i 5 | 




CO 





DIP-8P-01 



CXL5002M 



8 pin SOP 



BESET 



O 



■^ Hffl 0.15 



bnmH 



SOP-8P-L01 



Recommended Clock Conditions 

• Input clock amplitude Vck 150mVp-p to 1.0Vp-p (250mVp-p Typ.) 

• Clock frequency fc< 10.7 MHz 



I 



50657A - ST 



-701 



SONY® 



CXL5002P/CXL5002M 



Block Diagram 



IN AUTO 

Ks)— (p- 



AUTOBIAS CIRCUIT 



FEED 



OUT 



L CLAMP CIRCUIT — 



lBIT)^" 



ref. 



(1BIT) 



340 BIT SHIFT REGISTER] -{AM>|s^>-JAM>iJAM^- 
01 u ^ —101 1 02 



<D — d> 

Vss V CL 



CLOCK DRIVERS 



<3> 



CLK 



DUTY CONTROL 
CIRCUIT 



■<5> 

Vnn 



Pin Description 



No. 


Symbol 


Description 


Impedance 

[n] 


No. 


Symbol 


Description 


Impedance 

[n] 


1 


Vss 


GND 




5 


OUT 


Signal output 


600 to 1 k 


2 


Vcl 


5V power supply 




6 


FEED 


Feedback DC output 


>100k 


3 


CLK 


Clock input 


>100k 


7 


AUTO 


Autobias DC output 


10k 


4 


Vdd 


9V power supply 




8 


IN 


Signal input 


>100k 



-702- 



SONY, 



CX L5002P/CX L5002M 



Electrical Characteristics 



(Ta=25°C, Vdd=9.0V, Vcl=5.0V, fcK=10.7 MHz. Vck=250 mVp-p sine wave. 
See ,, See "Electrical characteristics test circuit") 



Item 


Symbol 


Measuring condition 


SW condition 


Measuring 
point 


Min ' 


Typ. 


Max. 


Unit 


SW1 


SW2 




Supply current 


Idd 


INPUT=250 kHz, 
1.28 Vp-p. 


a 


a 


A1 


- 


4 


5 


mA 


Icl 


A2 


— 


7 


9 


mA 


Insertion gain 


IG 


INPUT=250 kHz, 
1.28 Vp-p 
IG=20log (Output 
voltage [Vp-p]/ 
1.28[Vp-p]) 


a 


a 


V1 


-3 





3 


dB 


Frequency 
response 


fG 


fG=20log (V3.58 mhz/ 

V250kHz) *1 


b,c 


b 


V1 


-3.0 


-2.1 


— 


dB 


Differential gain 


DG 


5-staircase wave input 
Y=140IRE (=1.0 Vp-p) 
Measure S point with 
vectorscope *2 


e 


a 


S 


— 


3 


5 


% 


Differential phase 


DP 


- 


3 


5 


deg 


Allowable input 
amplitude 


VlN-AC 




— 


— 


— 


— 


— 


1.28 


Vp-p 


Noise 


S/N 


S: input=250 kHz 
1 .0 Vp-p 
output (Vp-p) 


f 


a 


V2 


55 


60 


- 


dB 


N: input=DC 
output (Vrms) 


d 


a 


V2 


Output DC voltage 


VlN-AC 




d 


a 


V3 


3.5 


5.0 


6.5 


V 


Vauto-dc 




V4 


3.5 


5.0 


6.5 


V 


Vfeed-dc 


INPUT— 250 kHz, 
1.28 Vp-p. 

• 


a 


a 


V5 


1.3 


2.3 


3.3 


V 


VOUT-DC 


V6 


1.7 


2.7 


3.7 


V 



■ 



703 



SONY® 



CX L5002P/CX L5002M 



Electrial Characteristics Test Circuit 



250 kHz, 1.28 Vp-p sine wave 



m =r4= (V5) 



250 kHz, 300 mVp-p sine wave 



3.58 MHz, 300 mVp-p sine wave 3 



Ground 



5-staircase wave 



250 kHz, 1 .0 Vp-p sine wave 




O 



BPF 



CLK 
f-K = 10.7MHz 
VV K =250mVp. .:> sine wave 

*2. Differential gain and differential measuring phase 
measuring condition 
V3.58 MHz (Output signal voltage [Vp-p] at 3.58 MHz input) 
V250kHz (Output signal voltage [Vp-p] at 250 kHz input) 



Note *1. Frequency characteristics measuring condition 



Set pin 8 (IN) voltage [V] = Vin-dc + 640 mV. 



5-staircase wave signal 

--if Chroma 40! RE 



3.58 MHz, 300 mVp-p sine wave 
250 kHz, 300 mVp-p sine wave 



[VI 




U 



ee 



140IRE(1.0VV-p) 

]_QI 4oire 



1H 63.5^/s 



640 mV (adjust with VgiAS' 



DG and DP are measured at output 
S point by vectorscope. 



*3. LPF frequency characteristics 



*4. BPF frequency characteristics 



[dB] 



50 



5.8 10.7 
Frequency [MHz] 



[dB] 




50 200 4.1M 10.7M 

Frequency [Hz] 



704- 



SONY. 



CX L5002P/CX L5002M 



Application Circuit 



Composite video signal input o 




signal output 



0.01/iF 
-II o f,,= 10.7MHz 



Frequency response vs. Ambient temperature 
















Input = 300 mVp-p 
3.58 MHz sine wave 


1 

9 


--- 




— -- 






^-- 



























3 










































4 













































20 20 40 60 

Ta-Ambient temperature [°C] 

Frequency response vs. Supply voltage 





1 




i—- 






■-- 


— 


In 
3 


3Ut = 

58 M 


300 
Hz si 


mVp 
ie we 


P 
ve 


--H 









— 































r— 

— f - 

i 

— -i~ — 

! 


3 


































-4 


















i 























8.5 9.0 

VdD _Su PP'V voltage [V] 



9.5 



Vr k — 250mVi. ( > sine wave 



Frequency response vs. Supply voltage 


1 













In 


put = 


300 


mVp-p 












3.58 MHz sine wave 



































































































































































4.7 5.0 5.3 

VcL-Supply voltage [V] 

Insertion gain vs. Ambient temperature 



Input = 1.28 Vp-p 
250 kHz sine wave 



20 20 40 60 

Ta-Ambient temperature [°C] 



705 - 



SONY® 



CXL5002P/CXL5002M 



Insertion gain vs. Supply voltage 



Insertion gain vs. Supply voltage 



1 












1 


iput 1.28 Vp-p 












250 kHz sine wave 













































1 


















































2 










































3 











































4.7 5.0 5.3 

Vrj|_- Supply voltage [Vl 

Differential gain vs. Ambient temperature 



4 

2 

1 

I 



-20 20 40 60 

Ta-Ambient temperature [°Cl 



1 












In 


put 


.28 Vp-p 














250 kHz sine wave 













































1 




-— 








---. 




















2 










._.. 




















































3 























8.5 9.0 

Vfjo-Supply voltage [V] 

Differential gain vs. Supply voltage 



9.5 





4 
3 
2 

1 

n 










































— 


# 




















c 

CD 

"to 
































































5 






















o 






















1 




















1 



















4.7 5.0 5.3 

V CL -Supply voltage [V] 



Differential gain vs. Supply voltage 



Frequency response 



4 
3 
2 

1 





8.5 90 

Voo-Supply voltage [V] 



































I 


u 


































-1 
































i 


































-2 






















• 










































-3 


































































-4 



































































9.5 



10k 100k 

f- Frequency- [Hz] 



1M 



706 



SONY. 



CXL5003P/M 



CMOS-CCD 1 H Delay Line for PAL 



Package Outline 



CXL5003P 8 Pin DIP (Plastic) 



r 

£5= 







3 
IT) 
O 


OO 

c~ 
en* 




















as* - 1 ! 




z 

O 
CO 




j 2*0.15 







Description 

CXL5003P/.CXL5003M are general purpose 
CCD delay line ICs which provide. 1H delay time of 
PAL. 

Features 

. Low power dissipation 110 mW (Typ.) 
. Small size package (8-pin DIP, SOP) 

• Low differential gain DG=3% (Typ.) 

. Input signal amplitude 180IRE (=1.28 Vp-p, 

Max.) 
. Low input clock amplitude operation 150 mVp-p 

(Min.) 
. On chip peripheral circuits 

Structure 

CMOS-CCD 

Functions 

. 848 bit CCD register 

• Clock drivers 

. Autobias circuit 

. Synchronized tip clamp circuit 

• Sample and hold circuit 

Absolute Maximum Ratings (Ta=25°C) 

. Supply voltage Vdd 11 v 

. Supply voltage Vcl 6 V 

. Operating temperature Topr —10 to +60 °C 
. Storage temperature Tstg —55 to +150°C 
. Allowable power dissipation 

Pd CXL5003P 480 mW 
CXL5003M 350 mW 

Recommended Operating Conditions 

• Supply voltage Vdd 9V±5% 

Vcl 5V±5% 



Recommended Clock Conditions 

. Input clock amplitude Vck 150 mVp-p to 1.0 Vp-p (250 mVp-p Typ. 
. Clock frequency fcK 13.3 MHz 



Unit: mm 




O'tol5' 



DIP-8P-01 



CXL5003M 8 Pin SOP (Plastic) 

+ 0.4 + 0.4 

6.1-0.1 1.B5-0.15 



8 5 

MM 



o 



g^ Hff I 0-1 5 
0.1-0.0 5 



hrunnd 



sop-8P-Loi 



■ 



707 



SONY® 



CXL5003P/CXL5003M 



Block Diagram 



IN AUTO 

r® ®- 



FEED 



AUTOBIAS CIRCUIT 



OUT 



1BIT)^J" 



ref. 



(1BIT) 



- CLAMP CIRCUIT | — [680 BIT SHIFT REGISTEr^| 4^M>-|^^ 

01 M^ ' ^^^ ^ 



CLOCK DRIVERS 



<D — ®- 

Vss V 



-<S>- 

CLK 



101 



,02 



DUTY CONTROL 
CIRCUIT 

I 



V,,n 



Pin Description 



No. 


Symbol 


Description 


Impedance 

[n] 


No. 


Symbol 


Description 


Impedance 

in] 


1 


Vss 


GND 




5 


OUT 


Signal output 


600 to 1k 


2 


Vcl 


5V power supply 




6 


FEED 


Feedback DC output 


>100k 


3 


CLK 


Clock input 


>100k 


7 


AUTO 


Autobias DC output 


10k 


4 


VOD 


9V power supply 




8 


IN 


Signal input 


>100k 



-708 



SONY® 



CXL5003P/CXL5003M 



Electrical Characteristics 



(Ta=25°C, Vdd=9.0V, Vcl=5.0V, fck=13.3 MHz, Vck=250 mVp-p 
sine wave, See "Electrical characteristics test circuit") 



Item 


Symbol 


Measuring condition 


SW condition 


Measuring 
point 


Min. 


Typ. 


Max. 


Unit 


SW1 


SW2 


Supply current 


Idd 


INPUT=250 kHz, 
1.28 Vp-p. 


a 


a 


A1 


— 


4 


5 


mA 


Icl 


A2 


— 


14 


16 


mA 


Insertion gain 


IG 


INPUT=250 kHz, 
1 .28 Vp-p 
IG=20log (Output 
voltage [Vp-p]/ 
1.28[Vp-pl) 


a 


a 


V1 


-3 





3 


dB 


Frequency 
response 


fG 


fG=20 log (V4.43 MHz/ 
V250kHz) *1 


b.c 


b 


V1 


-3.0 


-2.1 


— 


dB 


Differential gain 


DG 


5-staircase wave input 
Y=140IRE (=1.0 Vp-p) 
Measure S point with 
vectorscope *2 


e 


a 


S 


— 


3 


5 


% 


Differential phase 


DP 


- 


3 


5 


deg 


Allowable input 
amplitude 


VlN-AC 




— 


— 


— 


— 


— 


1.28 


Vp-p 


Noise 


S/N 


S: input=250 kHz 
1.0 Vp-p 
output (Vp-p) 


f 


a 


V2 


55 


60 


- 


dB 


N: input=DC 
output (Vrms) 


d 


a 


V2 


Output DC voltage 


VlN-AC 




d 


a 


V3 


3.5 


5.0 


6.5 


V 


Vauto-dc 




V4 


3.5 


5.0 


6.5 


V 


Vfeed-dc 


INPUT-250 kHz, 
1 .28 Vp-p. 


a 


a 


V5 


1.3 


2.3 


3.3 


V 


VOUT-DC 


V6 


1.7 


2.7 


3.7 


V 



709 



SONY® 



CXL5003P/CXL5003M 



Electrical Characteristics Test Circuit 



250 kHz, 1 .28 Vp-p sine wave 3 . 



250 kHz, 300 mVp-p sine wave :> 



4.43 MHz, 300 mVp-p sine wave 3 



5-staircase wave 



250 kHz, 1 .0 Vp-p sine wave 



=L 0.01/uF 



i CLK 
fcK -13.3 MHz 
VcK=250mV P .P sinei 




Note *1. Frequency characteristics measuring condition 



V4.43 mhz (Output signal voltage [Vp-p] at 4.43 MHz input) 
V250kHz (Output signal voltage [Vp-p] at 250 kHz input) 

Set pin 8 (IN) voltage [V] = Vin-dc + 640 mV. 

[V] 
4.43 MHz, 300 mVp-p sine wave 
250 kHz, 300 mVp-p sine wave 




640 mV (adjust with VglAS' 



-710- 



SONY® 



CXL5003P/CXL5003M 



e 2. Differential gain and differential phase measuring condition 

5-staircase wave signal 

--;: f Chroma 40IRE 



u 



ea 



140IRE(1.0V P P ) 

LQI 4oire 



1H 63.5a«s 
DG and DP are measured at output S point by vectorscope. 



*3. LPF frequency characteristics 



*4. BPF frequency characteristics 



(Delay time — 170ns) 



[dB] 




5.8 13.3 
Frequency [MHz] 




50 200 5.1 M 13.3M 

Frequency [Hz] 



Application Circuit 






5.1k; 



0-l" F 0.01*F=f= ± - l » f 

Composite video signal input o 1|- 



L.P.F 



1H delay signal output 



lMn 




Delay time = 170ns 
2SA1175 



■ 



j| o fCK= 13.3 MHz 



CLK 



VCK=250mVp-p sine wave 



-711 



SONY® 



CXL5003P/CXL5003M 



Frequency response vs. 

Ambient temperature 















_. .. 
In 


1 
put = 


300 


1 
mVp-p 














3. 


58 M 


^z sine wave 




































































































3 










































4 











































Ta-Ambient temperature [°Cl 

Frequency response vs. 

Supply voltage 















1 
Input = 


300 


mVp 


P 














3.E 


8M 


Hz si 


ne w 


ave 
















































































































3 










































4 











































Frequency response vs. 

Supply voltage 















In 


put = 


1 

300 


1 
mVp-p 














3.58 MHz sine wave 








































































































3 























































































4.7 5.0 5.3 

Va-Supply voltage [V] 

Insertion gain vs. 

Ambient temperature 















In 


nut 


1 
= 1.28 Vc 
















250 kHz sine wave 










































































































2 










































3 











































VDD-Supply voltage [V] 



Ta-Ambient temperature [°Cl 



Insertion gain vs. Supply voltage 



Insertion gain vs. Supply voltage 













I 


nput 


I 
1.28 Vp- 


P 












2 


50 k 


Hzs 


ne w 


ave 















































































































































































4.7 5.0 

VcL-Supply voltage [V] 















1 


nput 


1 
1.28 Vp- 


3 














2 


50 k 


Hzs 


ne w 


ave 



































































1 






























2 










































-3 











































9.0 

VDD-Supply voltage [V] 



-712- 



SONY® 



CXL5003P/CXL5003M 



Differential gain vs. Ambient temperature 



-20 20 40 60 

Ta-Ambient temperature [°C] 



Differential gain vs. Supply voltage 



4.7 5.0 5.3 

Vci.-Supply voltage [V] 



Differential gain vs. Supply voltage 



Frequency response 





1 


II 


II II 








if ^ N ' 








\ 








\ 1 








\ 1 






































II 


II II 



f-Frequency [Hz] 



VDD-Supply voltage [V] 



-713- 



sony. CXL5005P/CXL5005M 



CMOS-CCD 1 H Delay Line for NTSC with PLL 



Description 

CXL5005P/CXL5005M are general purpose CCD 
delay line ICs which provide 1 H delay time of NTSC. 

The ICs are operative with a color sub-carrier 
frequency (3.58 MHz), as they contain a PLL. 

Features 

• Low power consumption 90 mW (Typ.) 
. Small size package (14-pin DIP, SOP) 
. Low differential gain DG— 3% (Typ.) 

. Input signal amplitude 1 80 IRE (=1 .28 Vp-p, 

Max.) 

. Low input clock amplitude operation 200 mVp-p 

(Min.) 

• On chip peripheral circuits. 

• 3xfsc output pin is provided. 

Structure 

CMOS-CCD 

Functions 

. 680 bit CCD resister 
« Clock drivers 

• Autobias circuit 

• Synchronized tip clamp circuit 
. Sample and hold circuit 

. PLL (Phase Locked Loop) 

Absolute Maximum Ratings (Ta=25°C) 

. Supply voltage Vdd 1 1 V 

• Supply voltage Vcl 6 V 
. Operating temperature Topr —10 to +60 °C 
. Storage temperature Tstg — 55to+150°C 

• Allowable power dissipation 

Pd CXL5005P 800 mW 
CXL5005M 400 mW 

Recommended Operating Conditions 

• Supply voltage Vdd 9 V±5% 

Vcl 5 V±5% 

Recommended Clock Conditions 

• Input clock amplitude Vclk 200 mVp-p to 

1.0 Vp-p 
(300mVp-p Typ.) 

• Clock frequency fci_K 3.579545 MHz 



Package Outline 



Unit: mm 



CXL5005P 



14Pin DIP (Plastic 







3 
O 


53 
















0.5 1M 


1 3 




1.2 1W5 







14Pin DIP (Plastic) 







3 
O* 


3 






rm 


Trm 


till 




3 




0.4 6 t0 -° e 




1.5 2 T 







CXL5005M 14Pin SOP (Plastic) 

+ 0.4 * 0.4 

9.9-0.1 . _. 1.8 5-0.15 



BflflHBflir 



0.4 5 1<u 



J[~ \Q\ 0.15" 

o.i -go 5 



HJ 



SOP-14P-L01 



E88Z40-ST 



714 



SONY 



CXL5005P/CXL5005M 



Block Diagram 



-©- 



» <& © © 



AUTOBIAS 
CIRCUIT 



CLAMP 
CIRCUIT 



VCO 



<D d> 



-@ ©- 



OUTPUT & S/H 
(I BIT) 



680 BIT SHIFT 
REGISTER 



f») t»z 



CLOCK DRIVER 



^> 



<1> 



PHASE 
COMPARATOR 



1/3 COUNTER 



©- 



VCL 



^ 



Pin Description 



No. 


Symbol 


Description 


Impedance 


No. 


Symbol 


Description 


Impedance 

mi 


1 


Vss 


GND 




8 


Vcl 


5V power supply 




2 


Vcl 


5V power supply 




9 


CLK 


Clock input 


* 5k 


3 


VCOin 


VCO input 


>100k 


10 


NC 






4 


Vdd 


9V power supply 




11 


OUT 


Signal output 


600 to 1 k 


5 


PCout 


Phase Comparator output 


ftr 5k 


12 


FEED 


Feedback DC output 


>100k 


6 


NC 






13 


AUTO 


Autobias DC output 


10k 


7 


VCOout 


VCO output 


v 5k 


14 


IN 


Signal input 


>100k 



-715 - 



SONY. 



CXL5005P/CXL5005M 



Electrical Characteristics (Ta=25°C, Vdd=9.0V, Vcl=5.0V, fcK=3.58 MHz. Vck=300 mVp-p sine wave, 

Test poit See"Electrcal characteristics test circuit") 



Item 


Symbol 


Test condition 


SW condition 


Test 
point 


Min. 


Typ. 


Max. 


Unit 


SW1 


SW2 


Supply current 


loo 


INPUT=250 kHz. 
1 .28 Vp-p. 


a 


a 


A1 


— 


4 


5 


mA 


Icl 


A2 


— 


9 


12 


mA 


Insertion gain 


IG 


INPUT=250 kHz. 
1.28 Vp-p 
IG=20log (Output 
voltage [Vp-pJ/ 
1.28[Vp-p]) 


a 


a 


VI 


-3 





3 


dB 


Frequency 
response 


fG 


fG=20log (VasaiW 
V250kHz) (Note 1) 


b.c 


b 


V1 


-3.0 


-2.1 


— 


dB 


Differential gain 


DG 


5-staircase wave input 
Y=140IRE (=1.0 Vp-p) 
Measure S point with 
vectorscope (Note 2) 


e 


a 


S 


— 


3 


5 


% 


Differential phase 


DP 


- 


3 


5 


deg 


Allowable input 
amplitude 


VlN-AC 




— 


— 


— 


— 


— 


1.28 


Vp-p 


Noise 


S/N 


S: input=250 kHz 
1.0 Vp-p 
output (Vp-p) 


f 


a 


V2 


55 


60 


- 


dB 


N: input=DC 
output (Vrms) 


d 


a 


V2 


Output DC voltage 


VlN-AC 




d 


a 


V3 


3.5 


5.0 


6.5 


V 


Vauto-dc 




V4 


3.5 


5.0 


6.5 


V 


Vfeed-dc 


INPUT-250 kHz, 
1.28 Vp-p. 


a 


a 


V5 


1.3 


2.3 


3.3 


V 


VOUT-DC 


V6 


1.7 


2.7 


3.7 


V 



716 



SONY- 



CXL5005P/CXL5005M 



Electrical Characteristics Test Circuit 



250 kHz, 1 .28 Vp-p sine wave 3 



250 kHz, 300 mVp-p sine wave d 



3.58 MHz, 300 mVp-p sine wave 3 



5-staircase wave 



250 kHz, 1 .0 Vp-p sine wave 




LK /CLK = 3.58MHz 

9 VrjLK = 300mVp-p sine wave 



Note 1) Frequency characteristics measuring condition 

V3 58MH* (Output signal voltage [Vp-p] at 3.58 MHz input) 
V250kHz (Output signal voltage [Vp-p] at 250 kHz input) 

Set pin 14 (IN) voltage [V] = Vin-dc + 640 mV. 



560C 















L PF 




BPF 






r 










note 

2SA1175 


3) 




note 4) 






Vectorscope 



dB 



3.58 MHz, 300 mVp-p sine wave 
250 kHz, 300 mVp-p sine wave 



640 mV (adjust with Vg^s' 



2) Differential gain and differential phase measuring condition 

5-staircase wave signal 

— r f Chroma 40I RE 



u 



ea 



140IRE(1.0V, ..) 

1XII 40IRE 



1H 63.5/iS 
DG and DP are measured at output S point by vectorscope. 
3) LPF frequency characteristics 4) BPF frequency characteristics 

(Delay time — 140ns) 



dB 





50- 




5.8 10.7 
Frequency [MHz] 



50 200 4.1M10.7M 

Frequency [Hz] 



717- 



SONY, 



CXL5005P/CXL5005M 



Application Circuit 



Composite video signal 
input 



/CLK = 3.58MHz 
V CLK = 300mVp-p 
sine wave 




1 H delay signal 



Frequency response vs. Ambient temperature 



Frequency response vs. Supply voltage 
















In 


put •" 
58 M 


300 


mV 


3-p 












<~ 3. 
































































































-3 























































































40 60 



Ta-Ambient temperature [ C C] 

Frequency response vs. Supply voltage 













1 — 1 

Input = 


1 

300 


mVp-p 












3.5 


8M 


Hz si 


ne w 


ave 
































































































































































... 



8.5 90 9.5 

VQD'Suuply volta 9 e [VI 















— r 

Input = 


300 


I 
mVp-p 














3.E 


8 M 


Hzs 


ne wave 














































2 










































3 























































































4.7 5.0 5.3 

Vci_' Supply voltage [V] 

Insertion gain vs. Ambient temperature 













lr 


..... 
put 


1 1 
= 1.28 Vp-p 












2 


50 k 


Hz si 


le w 


sve 
































































































































































40 60 



Ta-Ambient temperature [°C] 



718 



SONY" 



CXL5005P/CXL5005M 



Insertion gain vs. Supply voltage 



Insertion gain vs. Supply voltage 













In 


put 


1 
.28 Vp-p 














2E 


Okl- 


(z sir 


e wa 


ve 



































































































































































v CL j Jj uu P'Y voltage [V] 

Differential gain vs. Ambient temperature 



20 40 60 

Ta-Ambient temperature [°C] 













In 


put 


1 
.28 Vp-p 














250 kHz sine wave 



































































































































































Vqd-SuupIv voltage [V] 

Differential gain vs. Supply voltage 





4 
3 

2 
1 



































































£ 






















'5 

O) 






















c 






















x 






















6 

Q 

































































4.7 5.0 5.3 

Vc[_-Suuply voltage [V] 



Differential gain vs. Supply voltage 



8.5 9.0 

VoD"SuuplV voltage [V] 



Frequency response 




f - Frequency [Hz] 



-719- 



Sony Corporation 



Application Engineering Dept : Semiconductor Group 

4-14-1 Asahi-cho Atsugi-shi Kanagawa-ken 243 Japan 
O : (0462) 30-5399 
Fax : (0462) 30-6143 

Semiconductor Business Dept : Components Marketing Group 

4-10-18 Takanawa Minato-ku Tokyo 108 Japan 
O : (03) 448-3426 
Fax : (03) 448-7493 
Telex : Sony Corp J24666 



Sony Semiconductor Integrated Circuit Data Book 

1990. Apr. 1st Edition 
Edited and Published by Application Engineering Department 

Semiconductor Group 
Sony Corporation 
Product by Hikari Shashin Insatsu Corporation 



Printed in Singapore 

at Stamford Press Pte Ltd 






SONY. 



Sony Semiconductor 



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